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1. 发明申请

US20110173577A1 Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields 审中-公开
标题翻译：用于最大化过程敏感电路产量的模式过程调优和设计优化技术
公开(公告)号：US20110173577A1
公开(公告)日：2011-07-14
申请号：US12024390
申请日：2008-02-01
申请人： Ching-Te K. Chuang , Fook-Luen Heng , Rouwaida Kanj , Keunwoo Kim , Jin-Fuw Lee , Saibal Mukhopadhyay , Sani Richard Nassif , Rama Nand Singh
发明人： Ching-Te K. Chuang , Fook-Luen Heng , Rouwaida Kanj , Keunwoo Kim , Jin-Fuw Lee , Saibal Mukhopadhyay , Sani Richard Nassif , Rama Nand Singh
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following steps. Based on a physical layout diagram of the circuit, a virtual representation of the fabricated circuit is obtained that accounts for one or more variations that can occur during a circuit production process. A quality-based metric is used to project a production yield for the virtual representation of the fabricated circuit. The physical layout diagram and/or the production process are modified. The obtaining, using and modifying steps are repeated until a desired projected production yield is attained.
摘要翻译：提供了改进电路设计和生产的技术。一方面，提供了一种用于虚拟制造过程敏感电路的方法。该方法包括以下步骤。基于电路的物理布局图，获得制造电路的虚拟表示，其考虑了在电路生产过程中可能发生的一个或多个变化。基于质量的度量用于为制造的电路的虚拟表示投影产量。物理布局图和/或生产过程被修改。重复获得，使用和修改步骤，直到达到期望的预计产量。

2. 发明授权

US08682634B2 Analyzing a patterning process using a model of yield 失效
标题翻译：使用产量模型分析图案化过程
公开(公告)号：US08682634B2
公开(公告)日：2014-03-25
申请号：US13613061
申请日：2012-09-13
申请人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E Rosenbluth , Rama N. Singh , Kehan Tian
发明人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E Rosenbluth , Rama N. Singh , Kehan Tian
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F2217/10
摘要： Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.
摘要翻译：提出了包括访问电路产量正向模拟的结果的技术，结果至少包括电路产量结果，包括模拟设备形状。使用电路产量结果，确定至少模拟装置形状的高级特征。基于确定的高水平特征和使用电路产量结果，构建了一种预测产量的紧凑模型，该紧凑模型包括多个可调参数，并构建了用于预测产量的紧凑模型，包括调整可调参数直到满足至少一个第一预定标准。构建最优化问题，其至少包括用于产量，目标和多个约束的紧凑模型。使用优化问题，根据多个约束修改目标，直到满足至少一个第二预定标准。

3. 发明授权

US08880382B2 Analyzing a patterning process using a model of yield 有权
公开(公告)号：US08880382B2
公开(公告)日：2014-11-04
申请号：US13352713
申请日：2012-01-18
申请人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E Rosenbluth , Rama N. Singh , Kehan Tian
发明人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E Rosenbluth , Rama N. Singh , Kehan Tian
IPC分类号： G06G7/48
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F2217/10
摘要： Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.

4. 发明申请

US20130185046A1 Analyzing A Patterning Process Using A Model Of Yield 失效
标题翻译：使用产量模型分析模式化过程
公开(公告)号：US20130185046A1
公开(公告)日：2013-07-18
申请号：US13613061
申请日：2012-09-13
申请人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E. Rosenbluth , Rama N. Singh , Kehan Tian
发明人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E. Rosenbluth , Rama N. Singh , Kehan Tian
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F2217/10
摘要： Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.
摘要翻译：提出了包括访问电路产量正向模拟的结果的技术，结果至少包括电路产量结果，包括模拟设备形状。使用电路产量结果，确定至少模拟装置形状的高级特征。基于确定的高水平特征和使用电路产量结果，构建了一种预测产量的紧凑模型，该紧凑模型包括多个可调参数，并构建了用于预测产量的紧凑模型，包括调整可调参数直到满足至少一个第一预定标准。构建最优化问题，其至少包括用于产量，目标和多个约束的紧凑模型。使用优化问题，根据多个约束修改目标，直到满足至少一个第二预定标准。

5. 发明授权

US07673195B2 Circuits and methods for characterizing device variation in electronic memory circuits 有权
标题翻译：用于表征电子存储器电路中的器件变化的电路和方法
公开(公告)号：US07673195B2
公开(公告)日：2010-03-02
申请号：US11866502
申请日：2007-10-03
申请人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
发明人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
IPC分类号： G11C29/00 , G11C7/06
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/5002
摘要： A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.
摘要翻译：电路包括比较器电路，其被配置为使得当其第一和第二输入在第一状态和第二输入之间转变时，其输出从第一数字逻辑电平切换到第二数字逻辑电平，其中第一输入具有大于施加电压的施加电压第二输入和第二状态，其中第一输入具有小于第二输入处的施加电压的施加电压。多个单元各自具有在场效应晶体管之间的输出节点处互连的至少一个串联连接的场效应晶体管。解码逻辑被配置为选择用于测量的给定的一个单元，并且将所述单元中的给定单元的输出节点选择性地互连到比较器电路的第一输入。电压供应电路被配置为（i）向被选择用于测量的给定一个单元的一对晶体管的栅极施加电压，使得该对晶体管在线性区域中工作，并且具有可变电压差＆Dgr ;在它们的栅 - 源电压之间，和（ii）改变＆Dgr; 直到比较器电路输出从第一数字逻辑电平切换到第二数字逻辑电平。

6. 发明申请

US20090310430A1 METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS 有权
标题翻译：用于表征电子存储器电路中器件变化的方法
公开(公告)号：US20090310430A1
公开(公告)日：2009-12-17
申请号：US12542187
申请日：2009-08-17
申请人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
发明人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
IPC分类号： G11C29/00 , G01R19/00 , G11C11/00 , G01R31/08
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/5002
摘要： A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.
摘要翻译：电路包括比较器电路，其被配置为使得当其第一和第二输入在第一状态和第二输入之间转变时，其输出从第一数字逻辑电平切换到第二数字逻辑电平，其中第一输入具有大于施加电压的施加电压第二输入和第二状态，其中第一输入具有小于第二输入处的施加电压的施加电压。多个单元各自具有在场效应晶体管之间的输出节点处互连的至少一个串联连接的场效应晶体管。解码逻辑被配置为选择用于测量的给定的一个单元，并且将所述单元中的给定单元的输出节点选择性地互连到比较器电路的第一输入。电压供应电路被配置为（i）向被选择用于测量的给定一个单元的一对晶体管的栅极施加电压，使得该对晶体管在线性区域中工作，并且具有可变的电压差在其栅极至源极电压之间，和（ii）改变增量，直到比较器电路输出从第一数字逻辑电平切换到第二数字逻辑电平。

7. 发明申请

US20090190426A1 CIRCUITS, METHODS AND DESIGN STRUCTURES FOR ADAPTIVE REPAIR OF SRAM ARRAYS 审中-公开
标题翻译： SRAM阵列自适应修复的电路，方法和设计结构
公开(公告)号：US20090190426A1
公开(公告)日：2009-07-30
申请号：US12019132
申请日：2008-01-24
申请人： Ching-Te K. Chuang , Jae-Joon Kim , Niladri N. Mojumder , Saibal Mukhopadhyay
发明人： Ching-Te K. Chuang , Jae-Joon Kim , Niladri N. Mojumder , Saibal Mukhopadhyay
IPC分类号： G11C29/44
CPC分类号： G11C29/50 , G11C11/41 , G11C29/028 , G11C29/12005 , G11C2029/5004 , G11C2029/5006
摘要： The circuit includes a static random access memory array having a plurality of cells, in turn having a plurality of devices; as well as a global sensor having at least one output, coupled to the static random access memory array, and configured to sense at least one of global readability and global write-ability. Also included is a decision-making circuit coupled to the at least one output of the global sensor. The decision-making circuit is configured to determine, from the at least one output of the global sensor, whether adaptation signals are required to correct global readability and/or write-ability. An adaptation signal generation block is also included and is coupled to the decision-making circuit and the array, and configured to supply the adaptation signals to the array, responsive to the decision-making circuit determining that the adaptation signals are required. At least the array and the global sensor, and preferably the decision-making circuit and the adaptation signal generation block as well, are implemented on a single integrated circuit chip. An associated method and design structure(s) are also provided.
摘要翻译：电路包括具有多个单元的静态随机存取存储器阵列，又具有多个器件; 以及具有耦合到静态随机存取存储器阵列并被配置为感测全局可读性和全局写入能力中的至少一个的至少一个输出的全局传感器。还包括耦合到全球传感器的至少一个输出的决策电路。决策电路被配置为从全局传感器的至少一个输出确定是否需要自适应信号来校正全局可读性和/或写入能力。还包括适配信号生成块，并且耦合到决策电路和阵列，并且被配置为响应于决策电路确定需要自适应信号而将适配信号提供给阵列。至少阵列和全局传感器，以及优选地，决策电路和自适应信号生成块也被实现在单个集成电路芯片上。还提供了相关联的方法和设计结构。

8. 发明申请

US20090189703A1 CIRCUITS AND DESIGN STRUCTURES FOR MONITORING NBTI (NEGATIVE BIAS TEMPERATURE INSTABILITY) EFFECT AND/OR PBTI (POSITIVE BIAS TEMPERATURE INSTABILITY) EFFECT 有权
标题翻译：用于监测NBTI（负偏差温度不稳定性）的电路和设计结构影响和/或PBTI（正偏差温度不稳定性）效应
公开(公告)号：US20090189703A1
公开(公告)日：2009-07-30
申请号：US12021459
申请日：2008-01-29
申请人： Ching-Te K. Chuang , Jae-Joon Kim , Tae-Hyoung Kim , Pong-Fei Lu , Saibal Mukhopadhyay , Rahul M. Rao , Shao-yi Wang
发明人： Ching-Te K. Chuang , Jae-Joon Kim , Tae-Hyoung Kim , Pong-Fei Lu , Saibal Mukhopadhyay , Rahul M. Rao , Shao-yi Wang
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates.
摘要翻译：环形振荡器具有大于或等于3的奇数NOR门，每个具有第一和第二输入端子，电压源端子和输出端子。所有NOR门的第一输入端互连，每个NOR门的输出端连接到紧邻的一个NOR门的第二输入端。在应力模式期间，电压供应和控制块向互连的第一输入端施加应力使能信号，并向电压端提供增加的电源电压。在测量模式期间，该模块接地互连的第一输入端，并向电源端施加正常的电源电压。还包括类似的基于NAND栅极的电路，组合NAND和NOR方面的电路，电路与环形振荡器，其中逆变器可以直接耦合或通过反向路径耦合，以及用于测量偏置温度不稳定性效应的电路通过门。

9. 发明授权

US08086917B2 Methods for characterizing device variation in electronic memory circuits 有权
标题翻译：表征电子存储器电路中器件变化的方法
公开(公告)号：US08086917B2
公开(公告)日：2011-12-27
申请号：US12542187
申请日：2009-08-17
申请人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
发明人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/5002
摘要： A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.
摘要翻译：电路包括比较器电路，其被配置为使得当其第一和第二输入在第一状态和第二输入之间转变时，其输出从第一数字逻辑电平切换到第二数字逻辑电平，其中第一输入具有大于施加电压的施加电压第二输入和第二状态，其中第一输入具有小于第二输入处的施加电压的施加电压。多个单元各自具有在场效应晶体管之间的输出节点处互连的至少一个串联连接的场效应晶体管。解码逻辑被配置为选择用于测量的给定的一个单元，并且将所述单元中的给定单元的输出节点选择性地互连到比较器电路的第一输入。电压供应电路被配置为（i）向被选择用于测量的给定一个单元的一对晶体管的栅极施加电压，使得该对晶体管在线性区域中工作，并且具有可变电压差＆Dgr ;在它们的栅 - 源电压之间，和（ii）改变＆Dgr; 直到比较器电路输出从第一数字逻辑电平切换到第二数字逻辑电平。

10. 发明申请

US20090091346A1 CIRCUITS AND METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS 有权
标题翻译：用于表征电子存储器电路中设备变化的电路和方法
公开(公告)号：US20090091346A1
公开(公告)日：2009-04-09
申请号：US11866502
申请日：2007-10-03
申请人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
发明人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
IPC分类号： G01R31/26
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/5002
摘要： A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.
摘要翻译：电路包括比较器电路，其被配置为使得当其第一和第二输入在第一状态和第二输入之间转变时，其输出从第一数字逻辑电平切换到第二数字逻辑电平，其中第一输入具有大于施加电压的施加电压第二输入和第二状态，其中第一输入具有小于第二输入处的施加电压的施加电压。多个单元各自具有在场效应晶体管之间的输出节点处互连的至少一个串联连接的场效应晶体管。解码逻辑被配置为选择用于测量的给定的一个单元，并且将所述单元中的给定单元的输出节点选择性地互连到比较器电路的第一输入。电压供应电路被配置为（i）向被选择用于测量的给定一个单元的一对晶体管的栅极施加电压，使得该对晶体管在线性区域中工作，并且具有可变的电压差在其栅极至源极电压之间，和（ii）改变增量，直到比较器电路输出从第一数字逻辑电平切换到第二数字逻辑电平。

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