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1. 发明授权

US07742327B2 Computer-readable medium encoding a back-gate controlled asymmetrical memory cell and memory using the cell 失效
标题翻译：使用该单元编码背栅控制的非对称存储单元和存储器的计算机可读介质
公开(公告)号：US07742327B2
公开(公告)日：2010-06-22
申请号：US12265042
申请日：2008-11-05
申请人： Ching Te Chuang , Jae-Joon Kim , Keunwoo Kim
发明人： Ching Te Chuang , Jae-Joon Kim , Keunwoo Kim
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.
摘要翻译：为非对称存储单元中的背栅极控制提供技术。在一个方面，电池包括五个晶体管，并且可以用于静态随机存取存储器（SRAM）应用。本发明的存储器电路可以包括多个位线结构，与多个位线结构相交以形成多个单元位置的多个字线结构以及位于多个单元位置的多个单元。每个单元可以在对应的一个字线结构的控制下选择性地耦合到相应的一个位线结构。每个单元可以包括具有第一和第二场效应晶体管（FETS）的第一反相器和具有与第一反相器交叉耦合以形成存储触发器的第三和第四FET的第二反相器。第一反相器中的FETS之一可以配置有独立的前门和后门，并且可以用作存取晶体管和其中一个逆变器的一部分。

2. 发明申请

US20090067223A1 COMPUTER-READABLE MEDIUM ENCODING A BACK-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE CELL 失效
标题翻译：使用电池编码背栅控制不对称存储单元和存储器的计算机可读介质
公开(公告)号：US20090067223A1
公开(公告)日：2009-03-12
申请号：US12265042
申请日：2008-11-05
申请人： Ching Te Chuang , Jae-Joon Kim , Keunwoo Kim
发明人： Ching Te Chuang , Jae-Joon Kim , Keunwoo Kim
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.
摘要翻译：为非对称存储单元中的背栅极控制提供技术。在一个方面，电池包括五个晶体管，并且可以用于静态随机存取存储器（SRAM）应用。本发明的存储器电路可以包括多个位线结构，与多个位线结构相交以形成多个单元位置的多个字线结构以及位于多个单元位置的多个单元。每个单元可以在对应的一个字线结构的控制下选择性地耦合到相应的一个位线结构。每个单元可以包括具有第一和第二场效应晶体管（FETS）的第一反相器和具有与第一反相器交叉耦合以形成存储触发器的第三和第四FET的第二反相器。第一反相器中的FETS之一可以配置有独立的前门和后门，并且可以用作存取晶体管和其中一个逆变器的一部分。

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