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1. 发明授权

US08285765B2 System and method for implementing simplified arithmetic logic unit processing of value-based control dependence sequences 有权
标题翻译：用于实现基于价值的控制依赖序列的简化算术逻辑单元处理的系统和方法
公开(公告)号：US08285765B2
公开(公告)日：2012-10-09
申请号：US11608907
申请日：2006-12-11
申请人： Lei Chen , Hung C. Ngo , Kevin J. Nowka
发明人： Lei Chen , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G06F7/38
CPC分类号： G06F9/3885 , G06F7/575 , G06F9/30021 , G06F9/30094 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3844 , G06F9/3857
摘要： A system and method for implementing arithmetic logic unit (ALU) support for value-based control dependence sequences. According to a first embodiment of the present invention, an ALU generates a carry-out signal designating one of a first and second value as a larger value. In response to the carry-out signal, the ALU updates a storage location with a third value, which is the larger value. According to a second embodiment of the present invention, an ALU generates a carry-out signal designating one of a first and second value as a larger value. In response to the carry-out signal, the ALU updates a storage location with a third value. The third value is a fourth value, if the carry-out signal designates the first value as the larger value or the third value is a fifth value, if the carry-out signal designates the second value as the larger value.
摘要翻译：用于实现算术逻辑单元（ALU）的系统和方法支持基于值的控制依赖序列。根据本发明的第一实施例，ALU产生指定第一和第二值中的一个作为较大值的进位输出信号。响应于进位信号，ALU用第三个值更新存储位置，该值是较大的值。根据本发明的第二实施例，ALU产生指定第一和第二值中的一个作为较大值的进位信号。响应于进位信号，ALU用第三个值更新存储位置。如果进位信号指定第二值作为较大值，则第三值是第四值，如果进位信号指定第一值作为较大值或第三值是第五值。

2. 发明申请

US20120205721A1 Design Structure for High Density Stable Static Random Access Memory 有权
标题翻译：高密度稳定静态随机存取存储器的设计结构
公开(公告)号：US20120205721A1
公开(公告)日：2012-08-16
申请号：US13450004
申请日：2012-04-18
申请人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
发明人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
IPC分类号： H01L27/105
CPC分类号： H01L27/11 , H01L27/0207 , H01L27/1108 , H01L27/1203 , H01L29/78648 , Y10S257/905
摘要： A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit includes a plurality of bit line structures, a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding bit line structure under control of a corresponding word line structure, each of said cells comprising a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor, wherein said at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of said bit line structures, and said at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.
摘要翻译：一种有形地体现在用于设计，制造或测试集成电路的机器可读介质中的设计结构包括多个位线结构，与所述多个位线结构相交以形成多个单元位置的多个字线结构，以及位于所述多个单元位置处的多个单元，每个所述单元在对应的字线结构的控制下选择性地耦合到对应的位线结构，每个所述单元包括具有至少第一n- 型场效应晶体管和至少第一p型场效应晶体管，其中所述至少第一n型场效应晶体管形成有尺寸适于减小所述位线结构的电容的相对厚的掩埋氧化物层，并且至少所述第一p型场效应晶体管形成有较薄的掩埋氧化物层。

3. 发明授权

US07719315B2 Programmable local clock buffer 失效
标题翻译：可编程本地时钟缓冲器
公开(公告)号：US07719315B2
公开(公告)日：2010-05-18
申请号：US11554666
申请日：2006-10-31
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H03K19/00
CPC分类号： G06F1/10 , G01R31/318552
摘要： A programmable clock generator circuit receives control signals and a global clock and generates a pulsed data clock and a scan clock in response to gating signals. The clock generator has data clock and scan clock feed-forward paths and a single feedback path. Delay control signals program delay elements in the feedback path and logic gates reshape and generate a feedback clock signal. The global clock and the feedback clock signal are combined to generates a pulsed local clock signal. A scan clock feed-forward circuit receives the local clock and generates the scan clock. A data clock feed-forward circuit receives the local clock and generates the data clock with a logic controlled delay relative to the local clock signal. The feedback clock is generated with controlled delay thereby modifying the pulse width of the data and scan clocks independent of the controlled delay of the data clock feed-forward path.
摘要翻译：可编程时钟发生器电路接收控制信号和全局时钟，并响应门控信号产生脉冲数据时钟和扫描时钟。时钟发生器具有数据时钟和扫描时钟前馈路径和单个反馈路径。延迟控制信号在反馈路径中的程序延迟元件和逻辑门重新形成并产生反馈时钟信号。全局时钟和反馈时钟信号被组合以产生脉冲本地时钟信号。扫描时钟前馈电路接收本地时钟并产生扫描时钟。数据时钟前馈电路接收本地时钟并产生相对于本地时钟信号的逻辑控制延迟的数据时钟。以受控的延迟产生反馈时钟，从而修改数据的脉冲宽度和扫描时钟，而与数据时钟前馈路径的受控延迟无关。

4. 发明申请

US20080267341A1 High Performance, Low Power, Dynamically Latched Up/Down Counter 失效
标题翻译：高性能，低功耗，动态锁定上/下计数器
公开(公告)号：US20080267341A1
公开(公告)日：2008-10-30
申请号：US11739756
申请日：2007-04-25
申请人： Jethro C. Law , Trong V. Luong , Hung C. Ngo , Peter J. Klim
发明人： Jethro C. Law , Trong V. Luong , Hung C. Ngo , Peter J. Klim
IPC分类号： H03K25/00
CPC分类号： H03K23/40 , H03K21/026
摘要： A high performance, low power up/down counter is set forth. The counter presented is controlled by two clock pulses, an up pulse and a down pulse, and updates all bits of the counter in parallel. These bits are then latched using a scannable pulsed limited output switching dynamic logic latch. By using a limited switch dynamic logic latch, the counter is able to utilize the speed of dynamic logic without requiring the traditional dynamic logic power. The area saved and speed gained by using a dynamic latch is significant compared to a typical edge-triggered flip-flop. Additionally, by computing all the next count state bits in parallel, the counter reduces an overall count computation delay by eliminating the counter ripple.
摘要翻译：提出了一个高性能，低功耗的上/下计数器。提供的计数器由两个时钟脉冲，上升脉冲和下降脉冲控制，并并行更新计数器的所有位。然后使用可扫描的脉冲限制输出开关动态逻辑锁存器锁存这些位。通过使用有限开关动态逻辑锁存器，计数器能够利用动态逻辑的速度，而不需要传统的动态逻辑电源。与典型的边沿触发触发器相比，通过使用动态锁存器保存的区域和速度是显着的。此外，通过并行计算所有下一个计数状态位，计数器通过消除计数器纹波来减少总计数计算延迟。

5. 发明申请

US20080201672A1 CASCADED PASS-GATE TEST CIRCUIT WITH INTERPOSED SPLIT-OUTPUT DRIVE DEVICES 失效
标题翻译：带插入式分接输出驱动器件的嵌入式门电路测试电路
公开(公告)号：US20080201672A1
公开(公告)日：2008-08-21
申请号：US11762257
申请日：2007-06-13
申请人： Ching-Te Chuang , Jente B. Kuang , Hung C. Ngo
发明人： Ching-Te Chuang , Jente B. Kuang , Hung C. Ngo
IPC分类号： G06F17/50
CPC分类号： G01R31/31725
摘要： A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.
摘要翻译：包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

6. 发明申请

US20080100360A1 PULSED LOCAL CLOCK BUFFER (LCB) CHARACTERIZATION RING OSCILLATOR 失效
标题翻译：脉冲本地时钟缓冲器（LCB）特征振荡器
公开(公告)号：US20080100360A1
公开(公告)日：2008-05-01
申请号：US11553014
申请日：2006-10-26
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H03K3/017
CPC分类号： H03K3/017 , G01R31/31727 , G06F1/10 , H03K3/0315 , H03K5/133 , H03K5/135 , H03K5/156
摘要： In an exemplary embodiment of the present invention, a local clock buffer (LCB) fabricated in a semiconductor receives a global clock signal as input. The LCB implements a pulse width controller that is operationally coupled to the LCB and an output driver forming a ring oscillator. The output driver outputs a pulse width adjusted signal. The pulse width of the pulse width adjusted signal is adjustable by way of the pulse width controller and is related in frequency to the global clock signal. A second ring oscillator (also referred to as the nclk loop) can also be implemented to server as the global clock signal. The pulse width controller can be used to precisely adjust the pulse width of the pulse width adjusted signal. A pulse width multiplier can be implemented to allow direct observation and measurement of the pulse width of the pulse width adjusted signal.
摘要翻译：在本发明的示例性实施例中，在半导体中制造的本地时钟缓冲器（LCB）接收全局时钟信号作为输入。 LCB实现了可操作地耦合到LCB的脉冲宽度控制器和形成环形振荡器的输出驱动器。输出驱动器输出脉宽调整信号。脉冲宽度调整信号的脉冲宽度可通过脉冲宽度控制器进行调节，并与频率相关于全局时钟信号。第二个环形振荡器（也称为nclk回路）也可以实现为服务器作为全局时钟信号。脉冲宽度控制器可用于精确调整脉宽调整信号的脉宽。可以实现脉冲宽度乘法器，以便直接观察和测量脉冲宽度调整信号的脉冲宽度。

7. 发明授权

US07129754B2 Controlled load limited switch dynamic logic circuitry 失效
标题翻译：受控负载限制开关动态逻辑电路
公开(公告)号：US07129754B2
公开(公告)日：2006-10-31
申请号：US11082805
申请日：2005-03-17
申请人： Hung C. Ngo , Jayakumaran Sivagnaname , Kevin J. Nowka , Robert K. Montoye
发明人： Hung C. Ngo , Jayakumaran Sivagnaname , Kevin J. Nowka , Robert K. Montoye
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： An LSDL circuit replaces the normal clock control of the pre-charge device for the dynamic node with a control signal that is logic zero whenever the circuit is in an active mode and is a logic one when the circuit is in standby mode. The pre-charge device holds the dynamic node at a pre-charged logic one state independent of the clock. During the logic one evaluate time of the clock, the logic tree determines the asserted state of the dynamic node. During the evaluate time, the asserted state is latched by the static LSDL section. The dynamic node then re-charges to the pre-charge state. Since the pre-charge device is not de-gated during the evaluate time, the dynamic node cannot be inadvertently discharged by noise causing an error. Likewise, since the clock does not couple to the pre-charge device a load is removed from the clock tree lowering clock power.
摘要翻译：只要电路处于活动模式，LSDL电路用动态节点的预充电装置的正常时钟控制替代逻辑零的控制信号，并且当电路处于待机模式时，逻辑为逻辑1。预充电装置将动态节点保持在与时钟无关的预充电逻辑1状态。在逻辑1期间评估时钟的时间，逻辑树确定动态节点的被断言状态。在评估时间期间，断言状态由静态LSDL部分锁存。然后动态节点重新充电到预充电状态。由于在评估时间期间预充电装置没有被去门，所以动态节点不能被无意中的噪声放电，导致错误。类似地，由于时钟不耦合到预充电装置，所以从时钟树中降低时钟功率的负载被去除。

8. 发明授权

US06975134B2 Buffer/driver circuits 失效
标题翻译：缓冲/驱动电路
公开(公告)号：US06975134B2
公开(公告)日：2005-12-13
申请号：US10821048
申请日：2004-04-08
申请人： Jente B. Kuang , Hung C. Ngo , Kevin J. Nowka
发明人： Jente B. Kuang , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03K17/16 , H03K19/00 , H03K19/003 , H03K19/017
CPC分类号： H03K19/00361 , H03K19/0016 , H03K19/01721
摘要： A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer/driver without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer/driver may be an inverter, non-inverter, or provide a multiple input logic function.
摘要翻译：具有用于驱动多个负载的大输出装置的缓冲器/驱动器配置有三个并行路径。第一个逻辑路径由小型设备组成，并配置为提供缓冲器/驱动器的逻辑功能，而无需驱动大负载。第二和第三逻辑路径具有直到上一个反相级的第一逻辑路径的逻辑功能。每个路径中的最后一个反相级是用于驱动缓冲区输出逻辑状态的单个器件。第二和第三逻辑路径具有电源门控，允许上拉和下拉器件的输入漂移去除栅极泄漏电压应力。当第二和第三逻辑路径是电源门控时，第一逻辑路径提供保持器功能以保持缓冲器输出的逻辑状态。缓冲器/驱动器可以是逆变器，非逆变器，或提供多输入逻辑功能。

9. 发明授权

US08069195B2 Method and system for a wiring-efficient permute unit 失效
标题翻译：布线效率置换单元的方法和系统
公开(公告)号：US08069195B2
公开(公告)日：2011-11-29
申请号：US11968692
申请日：2008-01-03
申请人： Bruce M. Fleischer , Hung C. Ngo , Jun Sawada
发明人： Bruce M. Fleischer , Hung C. Ngo , Jun Sawada
IPC分类号： G06F7/00
CPC分类号： G06F9/30032 , G06F7/762 , G06F7/766 , G06F9/30036 , G06F9/3824 , G06F9/3826
摘要： A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple multiplexors (MUXs) coupled to multiple logical AND gates. The multiple logical AND gates are coupled to multiple logical OR gates. The logical AND gates are physically separated from the logical OR gates. The logical AND gates receive input from one or more output data signals from the selectors. The logical OR gates combine the one or more output signals from the logical AND gates and provide output data from the permute unit.
摘要翻译：一种在置换单元中提供布线效率的方法。多个选择器从多个寄存器文件接收输入数据和共享控制信号。置换单元包括耦合到多个逻辑与门的多个多路复用器（MUX）。多个逻辑与门被耦合到多个逻辑或门。逻辑“与”门与逻辑或门物理分离。逻辑与门接收来自选择器的一个或多个输出数据信号的输入。逻辑或门组合来自逻辑与门的一个或多个输出信号，并提供来自置换单元的输出数据。

10. 发明授权

US07525393B2 Digital frequency multiplier circuit 失效
标题翻译：数字倍频电路
公开(公告)号：US07525393B2
公开(公告)日：2009-04-28
申请号：US11740612
申请日：2007-04-26
申请人： Hung C. Ngo , Fadi H. Gebara , Jethro C. Law , Trong V. Luong
发明人： Hung C. Ngo , Fadi H. Gebara , Jethro C. Law , Trong V. Luong
IPC分类号： H03L7/00
CPC分类号： H03L7/093 , H03L7/0991 , H03L7/18
摘要： A digital frequency multiplier circuit is disclosed. The digital frequency multiplier circuit includes a digitally controlled oscillator (DCO), a phase detector and a control circuit. The DCO generates an internal feedback signal. The phase detector detects a phase difference between the internal feedback signal and an external reference clock signal. Coupled between the phase detector and the DCO, the control circuit adjusts the DCO to align the internal feedback signal with the external reference clock signal after a phase difference between the internal feedback signal and the external reference clock signal has been detected. The control circuit also locks a modulation frequency of the DCO and monitors the state of the digital frequency multiplier circuit in order to maintain the lock.
摘要翻译：公开了一种数字倍频器电路。数字倍频器电路包括数字控制振荡器（DCO），相位检测器和控制电路。 DCO产生内部反馈信号。相位检测器检测内部反馈信号和外部参考时钟信号之间的相位差。在相位检测器和DCO之间耦合，在内部反馈信号和外部参考时钟信号之间的相位差被检测到之后，控制电路调节DCO以使内部反馈信号与外部基准时钟信号对准。控制电路还锁定DCO的调制频率，并监视数字倍频电路的状态以保持锁定。

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