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1. 发明授权

US6150238A Method for fabricating a trench isolation 有权
标题翻译：沟槽隔离方法
公开(公告)号：US6150238A
公开(公告)日：2000-11-21
申请号：US313129
申请日：1999-05-17
申请人： Chih-Ta Wu , Wen-Jet Su , Tun-Fu Hung , Ming-Ren Chi
发明人： Chih-Ta Wu , Wen-Jet Su , Tun-Fu Hung , Ming-Ren Chi
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： A method for fabricating a trench isolation is disclosed. First, a first insulated layer having a void is formed within the trench of the semiconductor. Next, the upper portion of said first insulated layer is etched to remove the void of said first insulated layer. Then, a second insulated layer having a void is formed over the first insulated layer. Next, the upper portion of said second insulated layer is etched to remove the void of said second insulated layer, thereby forming a trench isolation including the remainder of said first and second insulated layers.
摘要翻译：公开了一种用于制造沟槽隔离的方法。首先，在半导体的沟槽内形成具有空隙的第一绝缘层。接下来，蚀刻所述第一绝缘层的上部以去除所述第一绝缘层的空隙。然后，在第一绝缘层上形成具有空隙的第二绝缘层。接下来，蚀刻所述第二绝缘层的上部以去除所述第二绝缘层的空隙，由此形成包括所述第一和第二绝缘层的剩余部分的沟槽隔离。

2. 发明授权

US06265233B1 Method for determining crack limit of film deposited on semiconductor wafer 有权
标题翻译：确定沉积在半导体晶圆上的薄膜裂纹极限的方法
公开(公告)号：US06265233B1
公开(公告)日：2001-07-24
申请号：US09326096
申请日：1999-06-04
申请人： Jason C. S. Chu , Jerry C. S. Lin , Roger Tun-Fu Hung , Chih-Ta Wu
发明人： Jason C. S. Chu , Jerry C. S. Lin , Roger Tun-Fu Hung , Chih-Ta Wu
IPC分类号： G01R3126
CPC分类号： H01L22/34 , H01L21/02164 , H01L21/02271 , H01L21/31612
摘要： A method for determining a crack limit of a target film deposited on a wafer in production after a post annealing procedure is disclosed. The crack limit is determined by adopting and adjusting the thermal shrinkage rates of a plurality of target films deposited on bare wafers and annealed. The test results on bare wafers can be applied to the production wafers to prevent from film cracking and/or inspect instrumental conditions.
摘要翻译：公开了一种用于确定在后退火程序之后在生产中沉积在晶片上的靶膜的裂纹极限的方法。通过采用和调整沉积在裸晶片上并退火的多个靶膜的热收缩率来确定裂纹极限。裸晶片上的测试结果可以应用于生产晶片，以防止膜破裂和/或检查仪器条件。

3. 发明授权

US06242365B1 Method for preventing film deposited on semiconductor wafer from cracking 有权
标题翻译：防止沉积在半导体晶片上的膜破裂的方法
公开(公告)号：US06242365B1
公开(公告)日：2001-06-05
申请号：US09325915
申请日：1999-06-04
申请人： Jason C. S. Chu , Jerry C. S. Lin , Roger Tun-Fu Hung , Chih-Ta Wu
发明人： Jason C. S. Chu , Jerry C. S. Lin , Roger Tun-Fu Hung , Chih-Ta Wu
IPC分类号： H01L21322
CPC分类号： H01L22/34 , H01L21/02164 , H01L21/02271 , H01L21/31612
摘要： A method for preventing a target film deposited on a wafer in production from cracking after a post annealing procedure is disclosed. The method is performed by previously determining a crack limit before the target film is deposited on the wafer in production. The crack limit is determined by adopting and adjusting the thermal shrinkage rates of a plurality of target films deposited on bare wafers and annealed. After the crack limit is determined, a system-adjusting step and a reconfirmation step are performed, if necessary, to make sure the system conditions determined by the test results on bare wafers are suitably applied to the production wafers to prevent from film cracking. Moreover, the instrumental conditions can be inspected and tuned accordingly.
摘要翻译：公开了一种在后退火处理中防止沉积在晶片上的目标膜破裂的方法。该方法通过在生产中将靶膜沉积在晶片上之前预先确定裂纹极限来进行。通过采用和调整沉积在裸晶片上并退火的多个靶膜的热收缩率来确定裂纹极限。在确定裂纹极限之后，如果需要，执行系统调整步骤和再确认步骤，以确保通过裸晶片上的测试结果确定的系统条件适用于生产晶片以防止膜破裂。此外，工具条件可以相应地进行检查和调整。

4. 发明授权

US07622347B2 Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor 失效
标题翻译：自对准金属电极消除金属绝缘子半导体（MIS）电容器的自然氧化效应
公开(公告)号：US07622347B2
公开(公告)日：2009-11-24
申请号：US11622506
申请日：2007-01-12
申请人： Min-Hsiung Chiang , Chih-Ta Wu , Tsung-Hsun Huang
发明人： Min-Hsiung Chiang , Chih-Ta Wu , Tsung-Hsun Huang
IPC分类号： H01L21/8242
CPC分类号： H01L27/0629 , H01L27/1085 , H01L27/10867 , H01L29/6659
摘要： A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.
摘要翻译：一种形成电容器的方法，包括以下步骤。在电容器区域中的衬底上形成初始电容器，由此衬底的一部分使得初始电容器与隔离浅沟槽隔离（STI）结构分离。性传播感染在结构上形成第一介电层。将第一电介质层图案化为：形成遮蔽复合电容器的部分; 并且暴露STI和至少部分将初步电容器与浅沟槽隔离结构分开的衬底部分。金属部分至少形成在衬底部分上。在图案化的第一介电层部分，金属部分和STI上形成第二电介质层，由此至少在衬底部分上形成的金属部分防止在至少衬底部分上形成自然氧化物。本发明还包括由此形成的结构。

5. 发明申请

US20050272217A1 Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor 有权
标题翻译：自对准金属电极消除金属绝缘子半导体（MIS）电容器的自然氧化效应
公开(公告)号：US20050272217A1
公开(公告)日：2005-12-08
申请号：US10861148
申请日：2004-06-04
申请人： Min-Hsiung Chiang , Chih-Ta Wu , Tsung-Hsun Huang
发明人： Min-Hsiung Chiang , Chih-Ta Wu , Tsung-Hsun Huang
IPC分类号： H01L21/20 , H01L21/336 , H01L21/8242 , H01L27/06
CPC分类号： H01L27/0629 , H01L27/1085 , H01L27/10867 , H01L29/6659
摘要： A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.
摘要翻译：一种形成电容器的方法，包括以下步骤。在电容器区域中的衬底上形成初始电容器，由此衬底的一部分使得初始电容器与隔离浅沟槽隔离（STI）结构分离。性传播感染在结构上形成第一介电层。将第一电介质层图案化为：形成遮蔽复合电容器的部分; 并且暴露STI和至少部分将初步电容器与浅沟槽隔离结构分开的衬底部分。金属部分至少形成在衬底部分上。在图案化的第一介电层部分，金属部分和STI上形成第二电介质层，由此至少在衬底部分上形成的金属部分防止在至少衬底部分上形成自然氧化物。本发明还包括由此形成的结构。

6. 发明授权

US06803291B1 Method to preserve alignment mark optical integrity 有权
标题翻译：保持对准标记光学完整性的方法
公开(公告)号：US06803291B1
公开(公告)日：2004-10-12
申请号：US10394089
申请日：2003-03-20
申请人： Shih-Chi Fu , Feng-Jia Shih , Chia-Tung Ho , Chih-Ta Wu , Ching-Sen Kuo , Jieh-Jang Chen , Gwo-Yuh Shiau , Chia-Shiung Tsia
发明人： Shih-Chi Fu , Feng-Jia Shih , Chia-Tung Ho , Chih-Ta Wu , Ching-Sen Kuo , Jieh-Jang Chen , Gwo-Yuh Shiau , Chia-Shiung Tsia
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for protecting an alignment mark area during a CMP process including forming at least a first material layer over a process surface of a semiconductor wafer including active areas and alignment mark trenches formed in the at least one alignment mark area; forming at least a second material layer over the first material layer including the active areas and the at least one alignment mark area; lithographically patterning and etching the at least a second material layer to form at least a plurality lines of the at least a second material layer adjacent to the alignment mark trenches; and, carrying out a CMP process to remove at least a portion of the at least a second material layer.
摘要翻译：一种用于在CMP工艺期间保护对准标记区域的方法，包括在半导体晶片的工艺表面上形成至少第一材料层，所述半导体晶片包括形成在所述至少一个对准标记区域中的有源区和对准标记沟槽; 在包括所述有源区域和所述至少一个对准标记区域的所述第一材料层上形成至少第二材料层; 对所述至少第二材料层进行光刻图案化和蚀刻，以形成与所述对准标记沟槽相邻的所述至少第二材料层的至少多条线; 以及执行CMP处理以去除所述至少第二材料层的至少一部分。

7. 发明授权

US07851324B2 Method of forming metal-insulator-metal structure 有权
标题翻译：金属绝缘体金属结构形成方法
公开(公告)号：US07851324B2
公开(公告)日：2010-12-14
申请号：US11586528
申请日：2006-10-26
申请人： Yu-Jen Wang , Chia-Shiung Tsai , Yeur-Luen Tu , Lan-Lin Chao , Chih-Ta Wu , Hsing-Lien Lin , Chung Chien Wang
发明人： Yu-Jen Wang , Chia-Shiung Tsai , Yeur-Luen Tu , Lan-Lin Chao , Chih-Ta Wu , Hsing-Lien Lin , Chung Chien Wang
IPC分类号： H01L29/94
CPC分类号： H01L28/60 , H01L21/321
摘要： A method of manufacturing a semiconductor device includes forming a metal-insulator-metal (MIM) device having a metal organic chemical vapor deposited (MOCVD) lower electrode and an atomic layer deposited (ALD) upper electrode.
摘要翻译：一种制造半导体器件的方法包括形成具有金属有机化学气相沉积（MOCVD）下电极和原子层沉积（ALD）上电极的金属 - 绝缘体 - 金属（MIM）器件。

8. 发明授权

US07554145B2 Magnetic memory cells and manufacturing methods 有权
标题翻译：磁记忆体和制造方法
公开(公告)号：US07554145B2
公开(公告)日：2009-06-30
申请号：US11610760
申请日：2006-12-14
申请人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
IPC分类号： H01L29/76
CPC分类号： H01L43/12 , H01L27/228
摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.
摘要翻译：改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。然后可以在掩模层和导电通孔上形成导电存储器线。

9. 发明申请

US20070111438A1 SELF-ALIGNED METAL ELECTRODE TO ELIMINATE NATIVE OXIDE EFFECT FOR METAL INSULATOR SEMICONDUCTOR (MIS) CAPACITOR 失效
标题翻译：自对准的金属电极消除金属绝缘子半导体（MIS）电容器的氧化氮氧化物
公开(公告)号：US20070111438A1
公开(公告)日：2007-05-17
申请号：US11622506
申请日：2007-01-12
申请人： Min-Hsiung Chiang , Chih-Ta Wu , Tsung-Hsun Huang
发明人： Min-Hsiung Chiang , Chih-Ta Wu , Tsung-Hsun Huang
IPC分类号： H01L21/8242
CPC分类号： H01L27/0629 , H01L27/1085 , H01L27/10867 , H01L29/6659
摘要： A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.
摘要翻译：一种形成电容器的方法，包括以下步骤。在电容器区域中的衬底上形成初始电容器，由此衬底的一部分使得初始电容器与隔离浅沟槽隔离（STI）结构分离。性传播感染在结构上形成第一介电层。将第一电介质层图案化为：形成遮蔽复合电容器的部分; 并且暴露STI和至少部分将初步电容器与浅沟槽隔离结构分开的衬底部分。金属部分至少形成在衬底部分上。在图案化的第一介电层部分，金属部分和STI上形成第二电介质层，由此至少在衬底部分上形成的金属部分防止在至少衬底部分上形成自然氧化物。本发明还包括由此形成的结构。

10. 发明授权

US07202130B2 Spacer for a split gate flash memory cell and a memory cell employing the same 有权
标题翻译：分离栅闪存单元的间隔器和采用其的存储单元
公开(公告)号：US07202130B2
公开(公告)日：2007-04-10
申请号：US10775290
申请日：2004-02-10
申请人： Yuan-Hung Liu , Chih-Ta Wu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A spacer, a split gate flash memory cell, and related method of forming the same. In one aspect, a composite spacer includes a first spacer insulating layer having a first deposition distribution that varies as a function of a location on a substrate. The composite spacer also includes a second spacer insulating layer having a second deposition distribution that varies in substantial opposition to the first deposition distribution. In another aspect, a composite spacer includes a first spacer insulating layer having a substantially uniform deposition distribution across a surface thereof. The composite spacer also includes a second spacer insulating layer having a varying deposition distribution with a thinner composition in selected regions of the memory cell. In another aspect, a coupling spacer provides for a conductive layer that extends between a floating gate and a substrate insulating layer adjacent a source recessed into the substrate of the memory cell.
摘要翻译：间隔物，分裂栅极闪存单元及其相关方法。在一个方面，一种复合间隔物包括具有第一沉积分布的第一间隔绝缘层，其随着基底上的位置而变化。复合间隔物还包括具有与第一沉积分布基本相反的第二沉积分布的第二间隔绝缘层。在另一方面，复合间隔物包括在其表面上具有基本均匀的沉积分布的第一间隔绝缘层。复合间隔物还包括具有在存储单元的选定区域中具有较薄组成的不同沉积分布的第二间隔绝缘层。在另一方面，耦合间隔物提供导电层，该导电层在浮置栅极和与凹入到存储器单元的衬底中的源极相邻的衬底绝缘层之间延伸。

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