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1. 发明授权

US06552428B1 Semiconductor package having an exposed heat spreader 失效
标题翻译：具有暴露的散热器的半导体封装
公开(公告)号：US06552428B1
公开(公告)日：2003-04-22
申请号：US09416314
申请日：1999-10-12
申请人： Chien Ping Huang , Tom Tang , Kevin Chiang , Jenq-Yuan Lai , Candy Tien , Vicky Liu
发明人： Chien Ping Huang , Tom Tang , Kevin Chiang , Jenq-Yuan Lai , Candy Tien , Vicky Liu
IPC分类号： H01L2310
CPC分类号： H01L21/565 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48227 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2224/05599 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package with an exposed heat spreader includes a substrate having a semiconductor chip adhered to a first surface of the substrate. The heat spreader includes an upper portion, a lower portion with an opening formed in the center for receiving the semiconductor chip, and a connecting portion for connecting the upper portion and the lower portion in a manner that the upper portion is raised to a height above the opening of the lower portion. The lower portion is formed with a plurality of positioning members outwardly extending from edges of the lower portion to prevent the heat spreader from being dislocated during a molding process, and further includes downward flutes formed on the periphery of the opening for enabling resin flow underneath the heat spreader. The upper portion of the heat spreader is exposed to an exterior of the semiconductor package to improve heat dissipation.
摘要翻译：具有暴露的散热器的半导体封装包括具有粘附到基板的第一表面的半导体芯片的基板。散热器包括上部，具有形成在用于容纳半导体芯片的中心的开口的下部，以及用于连接上部和下部的连接部分，其上部部分被升高到上方的高度下部的开口。下部形成有从下部的边缘向外延伸的多个定位构件，以防止在模制过程中散热器脱位，并且还包括形成在开口的周边上的向下的凹槽，以使树脂在下面的流动散热器散热器的上部暴露于半导体封装的外部，以改善散热。

2. 发明授权

US06246115B1 Semiconductor package having a heat sink with an exposed surface 有权
标题翻译：具有具有暴露表面的散热器的半导体封装
公开(公告)号：US06246115B1
公开(公告)日：2001-06-12
申请号：US09425145
申请日：1999-10-21
申请人： Tom Tang , Chien Ping Huang , Kevin Chiang , Jeng-Yuan Lai , Candy Tien , Vicky Liu
发明人： Tom Tang , Chien Ping Huang , Kevin Chiang , Jeng-Yuan Lai , Candy Tien , Vicky Liu
IPC分类号： H01L2310
CPC分类号： H01L21/565 , H01L23/3128 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： An integrated circuit package with a fully-exposed heat sink is provided. The integrated circuit package includes a substrate having a first side being formed with first conductive traces and a second side being formed with second conductive traces. At least one chip is mounted on the substrate and electrically connected to the first conductive traces. A plurality of solder balls are provided at the terminal ends of the second conductive traces to allow external connection of the chip. The fully-exposed heat sink is mounted on the substrate. The heat sink is formed with a plurality of supportive legs arranged in such a manner as to allow a bottom surface of the heat sink to be separated from the chip and a top surface of the heat sink to be tightly attached to a cavity in a mold used to form an encapsulant for enclosing the chip. A plurality of positioning tongues are formed on the heat sink for securing the heat sink in position when performing a molding process for forming the encapsulant. With this integrated circuit package, no jig is required in the assembly of the integrated circuit package. Moreover, since there is no need to use adhesives to adhere the supportive legs onto the substrate, the integrated circuit package would not suffer from delamination as in the case of the prior art. The fully-exposed heat sink allows an increased heat-dissipating efficient as compared to the prior art.
摘要翻译：提供了一个具有完全暴露的散热器的集成电路封装。集成电路封装包括具有形成有第一导电迹线的第一侧的基板，和形成有第二导电迹线的第二侧。至少一个芯片安装在基板上并电连接到第一导电迹线。多个焊球设置在第二导电迹线的末端，以允许芯片的外部连接。完全曝光的散热器安装在基板上。散热器形成有多个支撑腿，其布置成允许散热器的底表面与芯片分离，并且散热器的顶表面紧密地附接到模具中的空腔中用于形成封装芯片的密封剂。多个定位舌片形成在散热器上，用于在执行用于形成密封剂的成型工艺时将散热器固定就位。使用该集成电路封装，集成电路封装的组装中不需要夹具。此外，由于不需要使用粘合剂将支撑腿粘附到基板上，所以与现有技术的情况相同，集成电路封装不会遭受分层。与现有技术相比，完全暴露的散热器允许增加散热效率。

3. 发明授权

US06218731B1 Tiny ball grid array package 有权
标题翻译：微小球栅阵列包
公开(公告)号：US06218731B1
公开(公告)日：2001-04-17
申请号：US09383835
申请日：1999-08-26
申请人： Chien-Ping Huang , Tzong-Dar Her , Kevin Chiang
发明人： Chien-Ping Huang , Tzong-Dar Her , Kevin Chiang
IPC分类号： H01L2348
CPC分类号： H01L23/13 , H01L23/3128 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L2224/06136 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/4824 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/01079 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A tiny ball grid array package based on a substrate. The substrate has at least an insulation layer and two copper foils laminated together. A hole is formed near the center of the substrate. A second one of the copper foils is patterned into multiple conductive traces formed on a surface of the substrate, while a first one of the copper foils has a surface partly exposed. The first copper foil is coupled with the conductive traces by vias, meanwhile, the first copper foil is grounded to form a ground plane, so as to improve the electrically properties and the heat dissipation efficiency. Bonding pads are formed in one surface of a chip. This surface is thermal-conductively connected to the grounded level, and the bonding pads are located in the hole. The bonding pads are electrically connected to a near end of a conductive trace by a conductive wire, and solder balls are attached at a far end of the conductive trace. A molding material fills the hole and covers a surrounding area of the hole to protect the bonding pads, the conductive wire, and the conductive traces, so as to cover ajunction area of the chip and the ground plane.
摘要翻译：基于基板的小型球栅阵列封装。基板至少具有绝缘层和两个铜箔层压在一起。在基板的中心附近形成有孔。铜箔中的第二个被图案化成形成在基板的表面上的多个导电迹线，而铜箔中的第一个具有部分暴露的表面。第一铜箔通过通孔与导电迹线耦合，同时第一铜箔接地以形成接地平面，从而提高电性能和散热效率。接合焊盘形成在芯片的一个表面中。该表面导热连接到接地层，焊盘位于孔中。接合焊盘通过导线电连接到导电迹线的近端，并且焊球附着在导电迹线的远端。成型材料填充孔并覆盖孔的周围区域以保护接合焊盘，导线和导电迹线，以便覆盖芯片和接地平面的接合区域。

4. 发明授权

US06703691B2 Quad flat non-leaded semiconductor package and method of fabricating the same 有权
标题翻译：四边形非铅半导体封装及其制造方法
公开(公告)号：US06703691B2
公开(公告)日：2004-03-09
申请号：US09991305
申请日：2001-11-14
申请人： Nan-Jang Chen , Kevin Chiang , Chien-Ping Huang , Tzong-Da Ho
发明人： Nan-Jang Chen , Kevin Chiang , Chien-Ping Huang , Tzong-Da Ho
IPC分类号： H01L23495
CPC分类号： H01L24/49 , H01L23/3107 , H01L23/4334 , H01L23/4951 , H01L24/48 , H01L2224/05554 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/4826 , H01L2224/49175 , H01L2224/49433 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01047 , H01L2924/10161 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A QFN (Quad Flat Non-leaded) semiconductor packaging technology is proposed, which can be used to package a semiconductor chip of a central-pad type having at least one row of bond pads arranged along a center line on one surface of the semiconductor chip. The proposed semiconductor packaging technology is based on a specially-designed leadframe which is formed with a plurality of leads, a chip-support-and-grounding structure, and at least one ground wing; wherein the chip-support-and-grounding structure serves both as a die pad and a ground bus for the packaged chip, and the ground wing is electrically linked to the chip-support-and-grounding structure. After encapsulation process is completed, the ground wing as well as the outer lead portions are exposed to the bottom outside of the encapsulation body, which can be then bonded a PCB's ground plane during SMT (Surface Mount Technology) process, thus enhancing the grounding effect and the electrical performance of the packaged chip during operation.
摘要翻译：提出了一种QFN（四方扁平无铅）半导体封装技术，其可用于封装中心焊盘型半导体芯片，该半导体芯片具有沿着半导体芯片的一个表面上的中心线布置的至少一行接合焊盘。所提出的半导体封装技术基于特殊设计的引线框架，该引线框架形成有多个引线，芯片支撑和接地结构以及至少一个地面翼; 其中芯片支撑和接地结构既用作封装芯片的管芯焊盘和接地总线，并且接地翼与芯片支撑和接地结构电连接。封装工艺完成后，地面翼和外引线部分暴露在封装体外侧的底部，然后在SMT（表面贴装技术）工艺中将PCB的接地平面接合，从而提高接地效果以及操作期间封装芯片的电气性能。

5. 发明授权

US06359341B1 Ball grid array integrated circuit package structure 失效
标题翻译：球栅阵列集成电路封装结构
公开(公告)号：US06359341B1
公开(公告)日：2002-03-19
申请号：US09489167
申请日：2000-01-21
申请人： Chien Ping Huang , Kevin Chiang , Tzong Da Ho
发明人： Chien Ping Huang , Kevin Chiang , Tzong Da Ho
IPC分类号： H01L2940
CPC分类号： H01L23/13 , H01L23/3677 , H01L23/49816 , H01L23/50 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/73265 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/30107 , H01L2924/3025 , H05K3/341 , H05K3/3436 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A BGA (Ball Grid Array) integrated circuit package is proposed, which is characterized in the use of a ground metallic layer adhered to a substrate. Moreover, the ground metallic layer can provide the semiconductor chip with a heat-dissipation path, allowing heat from the semiconductor chip during operation to be dissipated to the atmosphere via the ground metallic layer, so that the overall heat-dissipation efficiency can be increased. The ground metallic layer is formed with a chip-receiving cavity for accommodating a semiconductor chip mounted on the substrate. As the semiconductor chip is surrounded and in close proximity to the ground metallic layer, it can help reduce undesired simultaneous switching noise, crosstalk, and electromagnetic interference in the integrated circuit package.
摘要翻译：提出了一种BGA（球栅阵列）集成电路封装，其特征在于使用附着在基板上的接地金属层。此外，接地金属层可以为半导体芯片提供散热路径，允许来自半导体芯片的工作中的热量经由接地金属层散发到大气中，从而可以提高总的散热效率。接地金属层形成有用于容纳安装在基板上的半导体芯片的芯片接收腔。当半导体芯片被围绕并且紧邻接地金属层时，它可以帮助减少集成电路封装中的不期望的同时开关噪声，串扰和电磁干扰。

6. 发明授权

US06438503B1 Estimation of device temperature 有权
标题翻译：器件温度估计
公开(公告)号：US06438503B1
公开(公告)日：2002-08-20
申请号：US09307619
申请日：1999-05-07
申请人： Kevin Chiang
发明人： Kevin Chiang
IPC分类号： G01K108
CPC分类号： G01K7/42
摘要： Method and system for estimating processing time delay &Dgr;td of a selected signal processing device and temperature T of the device. A selected input signal is received by a first sub-system that includes the selected device and by a second sub-system having a controllable time delay, producing first and second sub-system output signals. The first and second sub-system output signals are compared to estimate the time delay of the selected device. A known relationship T=f(&Dgr;td) is used to estimate temperature of the selected device and to determine whether this temperature is higher than a permitted or threshold device operating temperature. First and second signals, having the same or different shape parameters, may be processed by the system, and a statistical average of estimated device time delay can be computed to estimate device temperature.
摘要翻译：用于估计所选信号处理装置的处理时间延迟DELTAtd和装置的温度T的方法和系统。选择的输入信号由包括所选设备的第一子系统和具有可控时延的第二子系统接收，产生第一和第二子系统输出信号。将第一和第二子系统输出信号进行比较以估计所选设备的时间延迟。已知关系T = f（DELTAtd）用于估计所选设备的温度并确定该温度是否高于许可或阈值设备工作温度。具有相同或不同形状参数的第一和第二信号可以被系统处理，并且可以计算估计的装置时间延迟的统计平均值以估计装置温度。

7. 发明授权

US06405293B1 Selectively accessible memory banks for operating in alternately reading or writing modes of operation 失效
标题翻译：选择性地可访问的存储体，用于交替读取或写入操作模式
公开(公告)号：US06405293B1
公开(公告)日：2002-06-11
申请号：US09532372
申请日：2000-03-21
申请人： Kevin Chiang , Shengquan Wu , Scott Li-Huan Jen
发明人： Kevin Chiang , Shengquan Wu , Scott Li-Huan Jen
IPC分类号： G06F1200
CPC分类号： G11C7/1006 , G11C7/1042 , G11C7/22 , G11C8/12
摘要： Two banks of memory are selectively accessed from a first interface terminal and a second interface terminal through multiplexer circuitry whereby one memory bank can be read by one terminal while the other memory bank is being updated from the other interface terminal. The multiplexer circuitry is controlled by a control register which responds to an operation code whereby either memory bank can be updated while the other memory bank is being read for hardware parameters, for example.
摘要翻译：通过多路复用器电路从第一接口终端和第二接口终端选择性地访问两组存储器，由此一个存储体可由一个终端读取，而另一个存储器组正在从另一个接口终端更新。多路复用器电路由控制寄存器控制，该控制寄存器响应于操作代码，从而可以在例如为硬件参数读取另一个存储体的同时可以更新存储体。

8. 发明授权

US06378105B1 Reed-Solomon multiplication method 有权
标题翻译：里德 - 所罗门乘法
公开(公告)号：US06378105B1
公开(公告)日：2002-04-23
申请号：US09317810
申请日：1999-05-24
申请人： Kevin Chiang
发明人： Kevin Chiang
IPC分类号： H03M1300
CPC分类号： H03M13/6502 , H03M13/1515
摘要： A method for computing Reed-Solomon error control checkbytes in reduced time and with reduced gate count. Two syndromes, s0 and s1, are computed for a sequence of data elements, using a selected primitive a that satisfies a selected primitive polynomial relation p(&agr;)=0. Each of two checkbytes, c0 and c1, is expressed as a linear combination of the syndromes s0 and s1, where each coefficient of each linear combination is expressed as a single power of the primitive &agr;, which is stored at the checkbyte generator for multiple use. This approach reduces gate count and associated time delay in formation of the usual Reed-Solomon multiplier coefficients.
摘要翻译：一种减少时间和减少门数的Reed-Solomon错误控制码字的计算方法。使用满足所选择的原始多项式关系p（α）= 0的所选择的原语a对于数据元素序列计算两个综合征s0和s1。两个校验码c0和c1中的每一个被表示为校正子s0和s1的线性组合，其中每个线性组合的每个系数被表示为原始α的单个功率，其存储在多个使用的校验字生成器。这种方法减少了形成通常的里德 - 所罗门乘数系数时的门数和相关的时间延迟。

9. 发明授权

US06207492B1 Common gate and salicide word line process for low cost embedded DRAM devices 有权
标题翻译：用于低成本嵌入式DRAM器件的普通门和自杀字线工艺
公开(公告)号：US06207492B1
公开(公告)日：2001-03-27
申请号：US09587466
申请日：2000-06-05
申请人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Chen-Jong Wang , Kevin Chiang
发明人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Chen-Jong Wang , Kevin Chiang
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L27/10873
摘要： A process for forming logic devices with salicide shapes on gate structures, as well as on heavily doped source/drain regions, while simultaneously forming embedded DRAM devices with salicide shapes only on gate structures, has been developed. The process features silicon oxide blocking shapes, formed in the spaces between gate structures, in the embedded DRAM device region. The silicon oxide blocking shapes are formed using a high density plasma deposition procedure which deposits a thick silicon oxide layer in the narrow spaces between gate structures in the embedded DRAM device region, and a thin silicon oxide layer in the wider spaces between gate structures in the logic device region, and on the top surface of all gate structures. A blanket, dry etch procedure is then employed to remove the thin silicon oxide layers from the top surface of all gate structures, as well as from the spaces between gate structures in the logic device region, while forming the desired silicon oxide blocking shapes between gate structures in the embedded DRAM device region, therefore allowing subsequent salicide shapes to be formed only on the top surface of gate structures, and on heavily doped source/drain regions in the logic device region.
摘要翻译：已经开发了用于在栅极结构上以及重掺杂的源极/漏极区域上形成具有硅化物形状的逻辑器件的过程，同时仅在栅极结构上形成具有硅化物形状的嵌入式DRAM器件。该工艺在嵌入式DRAM器件区域中具有形成在栅极结构之间的空间中的氧化硅阻挡形状。使用高密度等离子体沉积方法形成氧化硅阻挡形状，该方法在嵌入式DRAM器件区域中的栅极结构之间的狭窄空间中沉积厚的氧化硅层，并且在栅极结构中的较宽空间中沉积薄的氧化硅层逻辑器件区域，并在所有栅极结构的顶表面上。然后采用全面的干蚀刻方法从所有栅极结构的顶表面以及逻辑器件区域中的栅极结构之间的空间中移除薄氧化硅层，同时在栅极之间形成期望的氧化硅阻挡形状结构，因此允许仅在栅极结构的顶表面上以及在逻辑器件区域中的重掺杂的源/漏区上形成随后的自对准硅化物形状。

10. 发明授权

US07342430B1 Write strategy with multi-stage delay cell for providing stable delays on EFM clock 失效
标题翻译：采用多级延迟单元编写策略，为EFM时钟提供稳定的延迟
公开(公告)号：US07342430B1
公开(公告)日：2008-03-11
申请号：US11238737
申请日：2005-09-29
申请人： Kevin Chiang
发明人： Kevin Chiang
IPC分类号： G06F1/04
CPC分类号： G06F1/06
摘要： Present invention provides a method and apparatus for generating multiple phase shifted clocks with clocks delayed from EFM clock.
摘要翻译：本发明提供一种用于产生具有从EFM时钟延迟的时钟的多个相移时钟的方法和装置。

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