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1. 发明授权

US06405293B1 Selectively accessible memory banks for operating in alternately reading or writing modes of operation 失效
标题翻译：选择性地可访问的存储体，用于交替读取或写入操作模式
公开(公告)号：US06405293B1
公开(公告)日：2002-06-11
申请号：US09532372
申请日：2000-03-21
申请人： Kevin Chiang , Shengquan Wu , Scott Li-Huan Jen
发明人： Kevin Chiang , Shengquan Wu , Scott Li-Huan Jen
IPC分类号： G06F1200
CPC分类号： G11C7/1006 , G11C7/1042 , G11C7/22 , G11C8/12
摘要： Two banks of memory are selectively accessed from a first interface terminal and a second interface terminal through multiplexer circuitry whereby one memory bank can be read by one terminal while the other memory bank is being updated from the other interface terminal. The multiplexer circuitry is controlled by a control register which responds to an operation code whereby either memory bank can be updated while the other memory bank is being read for hardware parameters, for example.
摘要翻译：通过多路复用器电路从第一接口终端和第二接口终端选择性地访问两组存储器，由此一个存储体可由一个终端读取，而另一个存储器组正在从另一个接口终端更新。多路复用器电路由控制寄存器控制，该控制寄存器响应于操作代码，从而可以在例如为硬件参数读取另一个存储体的同时可以更新存储体。

2. 发明授权

US06725420B1 Pattern detection for computer segments 有权
标题翻译：计算机部分的模式检测
公开(公告)号：US06725420B1
公开(公告)日：2004-04-20
申请号：US09953459
申请日：2001-09-14
申请人： Kevin Chiang , Shengquan Wu
发明人： Kevin Chiang , Shengquan Wu
IPC分类号： G06F1100
CPC分类号： G06F11/0754
摘要： Method and system for compensating for a segment length of one or more of three consecutive mark and space segments utilized in a computer system. The three segments are received at a first pre-processor, the first segment is separated and issued separately from the remaining two segments, and the first segment length is compared with a permitted range of lengths. If the first segment length is not within the permitted range, a first error signal is issued, preferably indicating the non-complying first length. This process is repeated at second and third pre-processors. A segment processor receives the three individual segments and the error signals and non-complying lengths, if any, and compensates or corrects for any non-complying segment lengths before further processing occurs.
摘要翻译：用于补偿计算机系统中使用的三个连续标记和空间段中的一个或多个的段长度的方法和系统。在第一预处理器处接收三个段，第一段与剩余的两个段分开并发出，并将第一段长度与允许的长度范围进行比较。如果第一段长度不在允许范围内，则发出第一错误信号，优选地指示不符合第一长度。第二和第三预处理器重复此过程。片段处理器接收三个单独的段和错误信号以及不符合长度（如果有的话），并且在进一步处理之前补偿或校正任何不符合段的长度。

3. 发明授权

US06658068B1 Detection of EFM stream component widths 有权
标题翻译：检测EFM流分量宽度
公开(公告)号：US06658068B1
公开(公告)日：2003-12-02
申请号：US09418897
申请日：1999-10-15
申请人： Kevin Chiang , Shengquan Wu , Jhy-ping Shaw
发明人： Kevin Chiang , Shengquan Wu , Jhy-ping Shaw
IPC分类号： H04L2706
CPC分类号： H04L27/156 , H03K5/1252 , H03K5/19
摘要： Method and system for determining varying widths of each of a sequence of signal components (marks and spaces) in an incoming digital signal stream and for indicating which mark widths and which space widths fall outside acceptable ranges. A pre-mark and pre-space are added to the front end of the recieved stream for alignment purposes. The width of each signal component (mark or space) is determined and compared with an acceptable range of mark widths or space widths. Each mark or space that lies outside an acceptable range has an indicium associated with this mark or space, indicating this non-compliance. The modified digital signal stream, including the indicia, is re-issued after a selected time delay for subsequent signal processing. A method for measurement or estimation of mark width and space width is presented.
摘要翻译：用于确定输入数字信号流中的一系列信号分量（标记和空格）的变化宽度的方法和系统，以及用于指示哪些标记宽度和哪些空格宽度落在可接受的范围之外。为了对准目的，将预标记和预先空格添加到收到的流的前端。确定每个信号分量（标记或空间）的宽度，并与标记宽度或空格宽度的可接受范围进行比较。位于可接受范围之外的每个标记或空格都具有与该标记或空格相关联的标记，表明该不合规。包括标记在内的经修改的数字信号流在选择的时间延迟之后被重新发布用于随后的信号处理。提出了一种用于测量或估计标记宽度和空间宽度的方法。

4. 发明授权

US06560672B1 Write strategy and timing 有权
标题翻译：写策略和时机
公开(公告)号：US06560672B1
公开(公告)日：2003-05-06
申请号：US09596329
申请日：2000-06-16
申请人： Kevin Chiang , Shengquan Wu , Li-Huan Jen
发明人： Kevin Chiang , Shengquan Wu , Li-Huan Jen
IPC分类号： G06F1200
CPC分类号： G11B20/12
摘要： A method for set-up of a group of parameter values needed in a CD-R or CD-RW write cycle, where the time allotted for set-up is as low as six clock cycles. In a clock cycle from a preceding write cycle, first and second parameter values are read into first and second registers, and a third parameter value is read into a first SRAM. In clock cycles 1-5 of the present write cycle, fourth, fifth, sixth, seventh and eighth parameter values are read into second, third, fourth, fifth and sixth SRAMs. In clock cycle no. 6 or later of the present write cycle, three sums (or differences) of selected combinations of these eight parameter values are calculated and stored, new first and second parameter values are read into first and second registers, and a new third parameter value is read into another SRAM. The method is generalized to K parameters stored in registers, N parameters stored in SRAMs and calculation of M selected linear combinations of the K+N parameter values.
摘要翻译：用于设置CD-R或CD-RW写周期中所需的一组参数值的方法，其中分配用于设置的时间低至六个时钟周期。在从前一个写周期的时钟周期中，将第一和第二参数值读入第一和第二寄存器，并将第三参数值读入第一个SRAM。在本写入周期的时钟周期1-5中，第四，第五，第六，第七和第八参数值被读入第二，第三，第四，第五和第六SRAM。在时钟周期 6或更新的当前写入周期，计算并存储这8个参数值的选定组合的三个和（或差），新的第一和第二参数值被读入第一和第二寄存器，并且读取新的第三参数值进入另一个SRAM。该方法推广到存储在寄存器中的K个参数，N个参数存储在SRAM中，并计算M个选择的K + N参数值的线性组合。

5. 发明授权

US06438503B1 Estimation of device temperature 有权
标题翻译：器件温度估计
公开(公告)号：US06438503B1
公开(公告)日：2002-08-20
申请号：US09307619
申请日：1999-05-07
申请人： Kevin Chiang
发明人： Kevin Chiang
IPC分类号： G01K108
CPC分类号： G01K7/42
摘要： Method and system for estimating processing time delay &Dgr;td of a selected signal processing device and temperature T of the device. A selected input signal is received by a first sub-system that includes the selected device and by a second sub-system having a controllable time delay, producing first and second sub-system output signals. The first and second sub-system output signals are compared to estimate the time delay of the selected device. A known relationship T=f(&Dgr;td) is used to estimate temperature of the selected device and to determine whether this temperature is higher than a permitted or threshold device operating temperature. First and second signals, having the same or different shape parameters, may be processed by the system, and a statistical average of estimated device time delay can be computed to estimate device temperature.
摘要翻译：用于估计所选信号处理装置的处理时间延迟DELTAtd和装置的温度T的方法和系统。选择的输入信号由包括所选设备的第一子系统和具有可控时延的第二子系统接收，产生第一和第二子系统输出信号。将第一和第二子系统输出信号进行比较以估计所选设备的时间延迟。已知关系T = f（DELTAtd）用于估计所选设备的温度并确定该温度是否高于许可或阈值设备工作温度。具有相同或不同形状参数的第一和第二信号可以被系统处理，并且可以计算估计的装置时间延迟的统计平均值以估计装置温度。

6. 发明授权

US06378105B1 Reed-Solomon multiplication method 有权
标题翻译：里德 - 所罗门乘法
公开(公告)号：US06378105B1
公开(公告)日：2002-04-23
申请号：US09317810
申请日：1999-05-24
申请人： Kevin Chiang
发明人： Kevin Chiang
IPC分类号： H03M1300
CPC分类号： H03M13/6502 , H03M13/1515
摘要： A method for computing Reed-Solomon error control checkbytes in reduced time and with reduced gate count. Two syndromes, s0 and s1, are computed for a sequence of data elements, using a selected primitive a that satisfies a selected primitive polynomial relation p(&agr;)=0. Each of two checkbytes, c0 and c1, is expressed as a linear combination of the syndromes s0 and s1, where each coefficient of each linear combination is expressed as a single power of the primitive &agr;, which is stored at the checkbyte generator for multiple use. This approach reduces gate count and associated time delay in formation of the usual Reed-Solomon multiplier coefficients.
摘要翻译：一种减少时间和减少门数的Reed-Solomon错误控制码字的计算方法。使用满足所选择的原始多项式关系p（α）= 0的所选择的原语a对于数据元素序列计算两个综合征s0和s1。两个校验码c0和c1中的每一个被表示为校正子s0和s1的线性组合，其中每个线性组合的每个系数被表示为原始α的单个功率，其存储在多个使用的校验字生成器。这种方法减少了形成通常的里德 - 所罗门乘数系数时的门数和相关的时间延迟。

7. 发明授权

US06207492B1 Common gate and salicide word line process for low cost embedded DRAM devices 有权
标题翻译：用于低成本嵌入式DRAM器件的普通门和自杀字线工艺
公开(公告)号：US06207492B1
公开(公告)日：2001-03-27
申请号：US09587466
申请日：2000-06-05
申请人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Chen-Jong Wang , Kevin Chiang
发明人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Chen-Jong Wang , Kevin Chiang
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L27/10873
摘要： A process for forming logic devices with salicide shapes on gate structures, as well as on heavily doped source/drain regions, while simultaneously forming embedded DRAM devices with salicide shapes only on gate structures, has been developed. The process features silicon oxide blocking shapes, formed in the spaces between gate structures, in the embedded DRAM device region. The silicon oxide blocking shapes are formed using a high density plasma deposition procedure which deposits a thick silicon oxide layer in the narrow spaces between gate structures in the embedded DRAM device region, and a thin silicon oxide layer in the wider spaces between gate structures in the logic device region, and on the top surface of all gate structures. A blanket, dry etch procedure is then employed to remove the thin silicon oxide layers from the top surface of all gate structures, as well as from the spaces between gate structures in the logic device region, while forming the desired silicon oxide blocking shapes between gate structures in the embedded DRAM device region, therefore allowing subsequent salicide shapes to be formed only on the top surface of gate structures, and on heavily doped source/drain regions in the logic device region.
摘要翻译：已经开发了用于在栅极结构上以及重掺杂的源极/漏极区域上形成具有硅化物形状的逻辑器件的过程，同时仅在栅极结构上形成具有硅化物形状的嵌入式DRAM器件。该工艺在嵌入式DRAM器件区域中具有形成在栅极结构之间的空间中的氧化硅阻挡形状。使用高密度等离子体沉积方法形成氧化硅阻挡形状，该方法在嵌入式DRAM器件区域中的栅极结构之间的狭窄空间中沉积厚的氧化硅层，并且在栅极结构中的较宽空间中沉积薄的氧化硅层逻辑器件区域，并在所有栅极结构的顶表面上。然后采用全面的干蚀刻方法从所有栅极结构的顶表面以及逻辑器件区域中的栅极结构之间的空间中移除薄氧化硅层，同时在栅极之间形成期望的氧化硅阻挡形状结构，因此允许仅在栅极结构的顶表面上以及在逻辑器件区域中的重掺杂的源/漏区上形成随后的自对准硅化物形状。

8. 发明授权

US07342430B1 Write strategy with multi-stage delay cell for providing stable delays on EFM clock 失效
标题翻译：采用多级延迟单元编写策略，为EFM时钟提供稳定的延迟
公开(公告)号：US07342430B1
公开(公告)日：2008-03-11
申请号：US11238737
申请日：2005-09-29
申请人： Kevin Chiang
发明人： Kevin Chiang
IPC分类号： G06F1/04
CPC分类号： G06F1/06
摘要： Present invention provides a method and apparatus for generating multiple phase shifted clocks with clocks delayed from EFM clock.
摘要翻译：本发明提供一种用于产生具有从EFM时钟延迟的时钟的多个相移时钟的方法和装置。

9. 发明申请

US20080007313A1 Digital clock generator 审中-公开
标题翻译：数字时钟发生器
公开(公告)号：US20080007313A1
公开(公告)日：2008-01-10
申请号：US11801022
申请日：2007-05-08
申请人： Kevin Chiang
发明人： Kevin Chiang
IPC分类号： G06F1/04
CPC分类号： G06F1/08 , H03K3/0315 , H03K5/00006 , H03K5/06 , H03K2005/00058
摘要： A digital clock generator uses an on-chip digital delay chain to generate clock signal with variable frequency. An external charging circuit with variable charge rate may be used to select target frequency by generating digital pulse with variable width. An external reference clock may be used to calibrate the digital clock frequency. The external reference clock may be enabled only for calibration.
摘要翻译：数字时钟发生器使用片上数字延迟链来产生具有可变频率的时钟信号。可以通过产生具有可变宽度的数字脉冲来使用具有可变电荷率的外部充电电路来选择目标频率。外部参考时钟可用于校准数字时钟频率。外部参考时钟只能用于校准。

10. 发明授权

US06574776B1 Simultaneous processing for error detection and P-parity ECC encoding 有权
标题翻译：用于错误检测和P奇偶校验ECC编码的同时处理
公开(公告)号：US06574776B1
公开(公告)日：2003-06-03
申请号：US09289247
申请日：1999-04-09
申请人： Kevin Chiang
发明人： Kevin Chiang
IPC分类号： G06F1100
CPC分类号： H03M13/2909 , G06F11/1008 , G11B20/1833 , H03M13/1515 , H03M13/6561
摘要： Method and system for receiving each data element of an N×M array once and simultaneously forming an EDC error detection term and two ECC P-parity checkbytes for the array. Each data element is read once from memory and is received by an EDC processor and by an ECC processor and processed in parallel by the two processors to form the EDC error detection term and two ECC P-parity checkbytes.
摘要翻译：用于接收NxM阵列的每个数据元素一次并同时形成EDC错误检测项和阵列的两个ECC P奇偶校验位的方法和系统。每个数据元素从存储器读取一次，并由EDC处理器和ECC处理器接收并由两个处理器并行处理以形成EDC错误检测项和两个ECC P奇偶校验位。

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