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    • 5. 发明授权
    • Layout method for thin and fine ball grid array package substrate with plating bus
    • 精细球栅阵列封装基板与电镀母线布局方法
    • US06479894B2
    • 2002-11-12
    • US09949536
    • 2001-09-10
    • Chien-Ping HuangTzong-Da Ho
    • Chien-Ping HuangTzong-Da Ho
    • H01L2352
    • H05K3/242H01L23/49838H01L2924/0002H05K3/0052H01L2924/00
    • A layout method is proposed for semiconductor package substrate with plating bus, such as TFBGA (Thin & Fine Ball Grid Array) substrate, which can help allow each singulated package unit from the substrate to be substantially free of trace short-circuits due to misaligned cutting during singulation process. The proposed layout method is characterized in the provision of a plating bus of a special layout pattern for interconnecting all the via lands alongside each singulation line. The plating bus includes a plurality of crosswise segments, each being used to to interconnect one crosswise-opposite pair of the via lands across the singulation line; and a plurality of diagonal segments, each being used to interconnect one neighboring pair of the crosswise segments diagonally to each other across the singulation line. The proposed layout method allows each singulated package unit from the substrate to be substantially free of trace short-circuits due to misaligned cutting during singulation process. Moreover, it also allows the layout design work to be less complex than prior art.
    • 提出了一种具有电镀母线(例如TFBGA(Thin&Fine Ball Grid Array)薄膜)的半导体封装衬底的布局方法,其可以帮助允许来自衬底的每个单个封装单元由于不对准切割而基本上无痕迹短路 在分割过程中。 所提出的布局方法的特征在于提供一种专用布局图案的电镀母线,用于将所有通孔焊盘与每条分离线连接。 电镀母线包括多个横向段,每个横向段用于将一个横向相对的一对通孔焊盘互相穿过该分离线; 以及多个对角线段,每个对角线段用于将一对相邻的横向线段彼此对角地互相穿过单线。 所提出的布局方法允许来自基板的每个单个封装单元在切割过程中由于不对齐切割而基本上没有痕迹短路。 此外,它还允许布局设计工作比现有技术更不复杂。