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1. 发明授权

US06207492B1 Common gate and salicide word line process for low cost embedded DRAM devices 有权
标题翻译：用于低成本嵌入式DRAM器件的普通门和自杀字线工艺
公开(公告)号：US06207492B1
公开(公告)日：2001-03-27
申请号：US09587466
申请日：2000-06-05
申请人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Chen-Jong Wang , Kevin Chiang
发明人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Chen-Jong Wang , Kevin Chiang
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L27/10873
摘要： A process for forming logic devices with salicide shapes on gate structures, as well as on heavily doped source/drain regions, while simultaneously forming embedded DRAM devices with salicide shapes only on gate structures, has been developed. The process features silicon oxide blocking shapes, formed in the spaces between gate structures, in the embedded DRAM device region. The silicon oxide blocking shapes are formed using a high density plasma deposition procedure which deposits a thick silicon oxide layer in the narrow spaces between gate structures in the embedded DRAM device region, and a thin silicon oxide layer in the wider spaces between gate structures in the logic device region, and on the top surface of all gate structures. A blanket, dry etch procedure is then employed to remove the thin silicon oxide layers from the top surface of all gate structures, as well as from the spaces between gate structures in the logic device region, while forming the desired silicon oxide blocking shapes between gate structures in the embedded DRAM device region, therefore allowing subsequent salicide shapes to be formed only on the top surface of gate structures, and on heavily doped source/drain regions in the logic device region.
摘要翻译：已经开发了用于在栅极结构上以及重掺杂的源极/漏极区域上形成具有硅化物形状的逻辑器件的过程，同时仅在栅极结构上形成具有硅化物形状的嵌入式DRAM器件。该工艺在嵌入式DRAM器件区域中具有形成在栅极结构之间的空间中的氧化硅阻挡形状。使用高密度等离子体沉积方法形成氧化硅阻挡形状，该方法在嵌入式DRAM器件区域中的栅极结构之间的狭窄空间中沉积厚的氧化硅层，并且在栅极结构中的较宽空间中沉积薄的氧化硅层逻辑器件区域，并在所有栅极结构的顶表面上。然后采用全面的干蚀刻方法从所有栅极结构的顶表面以及逻辑器件区域中的栅极结构之间的空间中移除薄氧化硅层，同时在栅极之间形成期望的氧化硅阻挡形状结构，因此允许仅在栅极结构的顶表面上以及在逻辑器件区域中的重掺杂的源/漏区上形成随后的自对准硅化物形状。

2. 发明授权

US06436762B1 Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins 有权
标题翻译：使用湿式回蚀技术改善DRAM电路上电容器电气故障的位线的方法，以改善位线电容器覆盖边界
公开(公告)号：US06436762B1
公开(公告)日：2002-08-20
申请号：US09855238
申请日：2001-05-14
申请人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Min-Hsiung Chiang , Hsiao-Hui Tseng , Chung-Wei Chang
发明人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Min-Hsiung Chiang , Hsiao-Hui Tseng , Chung-Wei Chang
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/8234 , H01L21/20
CPC分类号： H01L27/10888 , H01L27/10811 , H01L28/91
摘要： A method is described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After forming FETs for the memory cells, an interpolysilicon oxide (IPO) layer is deposited, and first and second plug contacts are formed in the IPO to the FET source/drain areas for capacitors and bit line contacts, respectively. A capacitor node oxide is deposited, and first openings are etched in which crown capacitor bottom electrodes are formed. After etching back the node oxide a thin interelectrode dielectric layer is formed and a conformal conducting layer is deposited to form capacitor top electrodes. A photoresist mask is used to etch openings in the conducting layer over the second plug contacts, and an isotropic etch is used to recess the openings under the mask to increase the spacing between the capacitor top electrodes and the bit line contacts to improve the overlay margin. The photoresist mask is removed and an interlevel dielectric (ILD) layer is deposited. Bit-line contact openings are etched in the ILD layer aligned over the recessed openings and in the node oxide to the second contact plugs. Bit-line contact plugs are formed extending through the recessed openings, and a first conducting layer is deposited and patterned to form bit lines and to complete the memory cells for the DRAM.
摘要翻译：描述了一种用于制造具有改进的位线和电容器顶部电极之间的覆盖边缘的电容器下位线（CUB）DRAM单元的方法。在形成用于存储单元的FET之后，沉积多晶硅氧化物（IPO）层，并且在IPO中分别将第一和第二插头触点形成到用于电容器和位线触点的FET源极/漏极区域。沉积电容器节点氧化物，并且蚀刻第一开口，其中形成冠电容器底部电极。在蚀刻回节点氧化物之后，形成薄的电极间电介质层，并且淀积保形导电层以形成电容器顶部电极。使用光致抗蚀剂掩模来蚀刻导电层上的第二插头触点上的开口，并且使用各向同性蚀刻来凹陷掩模下方的开口以增加电容器顶部电极和位线触点之间的间隔，以改善覆盖边缘。去除光致抗蚀剂掩模并沉积层间电介质（ILD）层。在ILD层中蚀刻位线接触开口，其在凹入的开口上以及在节点氧化物中对齐到第二接触插塞。位线接触插塞形成为延伸穿过凹入的开口，并且第一导电层被沉积和图案化以形成位线并且完成用于DRAM的存储单元。

3. 发明授权

US06306767B1 Self-aligned etching method for forming high areal density patterned microelectronic structures 有权
标题翻译：用于形成高密度图案的微电子结构的自对准蚀刻方法
公开(公告)号：US06306767B1
公开(公告)日：2001-10-23
申请号：US09584111
申请日：2000-05-31
申请人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Wen-Chuan Chiang , Ming-Hsiang Chiang
发明人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Wen-Chuan Chiang , Ming-Hsiang Chiang
IPC分类号： H01L21302
CPC分类号： H01L27/10888 , H01L21/32139 , H01L27/10811
摘要： Within a method for forming a patterned layer there is first provided a topographic substrate. There is then formed conformally over the topographic substrate a blanket target layer formed of a target material, where the blanket target layer has a lower substantially horizontal portion, an upper substantially horizontal portion and an intermediate portion therebetween. There is then formed upon the lower substantially horizontal portion of the blanket target layer a first masking layer formed of a first masking material and formed upon the upper substantially horizontal portion of the blanket target layer a second masking layer formed of a second masking material. There is then etched, while employing an etch method having an enhanced sequential selectivity for the first masking material and the target material with respect to the second masking material, the first masking layer and the lower substantially horizontal portion of the blanket target layer to form a patterned target layer which leaves exposed a portion of the substrate beneath the lower horizontal portion of the blanket target layer while leaving unetched the upper substantially horizontal portion of the blanket target layer. The method is particularly useful for forming patterned capacitor plate layers.
摘要翻译：在形成图案层的方法中，首先提供地形衬底。然后，在地形基底上形成由目标材料形成的覆盖目标层，其中覆盖层目标层具有下部基本水平的部分，上部基本水平的部分和在其间的中间部分。然后，在覆盖目标层的下部基本水平的部分上形成由第一掩模材料形成并形成在覆盖目标层的上部基本水平的部分上的第一掩蔽层，第二掩蔽层由第二掩蔽材料形成。然后蚀刻，同时采用对于第一掩蔽材料和靶材料相对于第二掩蔽材料具有增强的顺序选择性的蚀刻方法，覆盖目标层的第一掩蔽层和下部基本水平的部分，以形成图案化目标层，其在衬底目标层的下部水平部分的下方露出衬底的一部分，同时保留未覆盖的覆盖目标层的上部基本水平的部分。该方法对于形成图案化电容器板层特别有用。

4. 发明授权

US06613690B1 Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers 有权
标题翻译：用于形成具有减少的多晶硅桁架的掩埋堆叠电容器结构的方法
公开(公告)号：US06613690B1
公开(公告)日：2003-09-02
申请号：US10197318
申请日：2002-07-17
申请人： Chung-Wei Chang , Kuo-Chyuan Tzeng , Chen-Jong Wang , Min-Hsiang Chiang , Chi-Hsing Lo
发明人： Chung-Wei Chang , Kuo-Chyuan Tzeng , Chen-Jong Wang , Min-Hsiang Chiang , Chi-Hsing Lo
IPC分类号： H01L21302
CPC分类号： H01L27/1087 , H01L21/32139 , H01L27/10835 , H01L28/91
摘要： A process for forming a buried stack capacitor structure in a recessed region of a shallow trench isolation (STI) region, has been developed. The process features a unique sequence of procedures eliminating possible polysilicon stringers or residuals which if left remaining would result in leakage or shorts between conductive elements. The unique sequence of procedures include: deposition of a silicon oxide layer on the polysilicon layer from which the storage node structure will be defined from; photoresist plugs used to protect the portions of the silicon oxide and the underlying polysilicon layer located in the recessed region, during definition of the polysilicon storage node structure; and definition of the polysilicon storage node structure via a wet etch procedure, using the silicon oxide layer for protection of the underlying polysilicon storage node structure.
摘要翻译：已经开发了在浅沟槽隔离（STI）区域的凹陷区域中形成掩埋堆叠电容器结构的工艺。该方法具有唯一的程序序列，可以消除可能的多晶硅桁条或残余物，如果留下剩余物会导致导电元件之间的泄漏或短路。独特的程序顺序包括：在多晶硅层上沉积氧化硅层，从其上定义存储节点结构; 用于在多晶硅存储节点结构的定义期间用于保护位于凹陷区域中的氧化硅部分和下面的多晶硅层的光阻胶塞; 以及通过湿蚀刻程序定义多晶硅存储节点结构，使用氧化硅层来保护下面的多晶硅存储节点结构。

5. 发明授权

US08659121B2 Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof 有权
标题翻译：具有无取向去耦电容器的半导体器件及其制造方法
公开(公告)号：US08659121B2
公开(公告)日：2014-02-25
申请号：US13188343
申请日：2011-07-21
申请人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Wen-Chuan Chiang , Chen-Jong Wang
发明人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Wen-Chuan Chiang , Chen-Jong Wang
IPC分类号： H01L23/62
CPC分类号： H01L27/0207 , H01L28/40
摘要： Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes at least one integrated circuit and at least one decoupling capacitor. The at least one decoupling capacitor is oriented in a different direction than the at least one integrated circuit is oriented.
摘要翻译：公开了具有无取向去耦电容器的半导体器件及其制造方法。在一个实施例中，半导体器件包括至少一个集成电路和至少一个去耦电容器。至少一个去耦电容器被定向在与至少一个集成电路取向的方向不同的方向上。

6. 发明授权

US06661050B2 Memory cell structure with trench capacitor and method for fabrication thereof 有权
标题翻译：具有沟槽电容器的存储单元结构及其制造方法
公开(公告)号：US06661050B2
公开(公告)日：2003-12-09
申请号：US10102280
申请日：2002-03-20
申请人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang
发明人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/11 , H01L29/66181 , Y10S257/906
摘要： Within both a memory cell structure and a method for fabricating the memory cell structure there is employed a storage capacitor formed within a trench adjoining an active region of a semiconductor substrate. Within the memory cell structure and the method for fabrication thereof, both the active region of the semiconductor substrate and the trench are contained within a doped well within the semiconductor substrate.
摘要翻译：在存储单元结构和用于制造存储单元结构的方法中，采用在与半导体衬底的有源区相邻的沟槽内形成的存储电容器。在存储单元结构及其制造方法中，半导体衬底的有源区和沟槽都包含在半导体衬底内的掺杂阱中。

7. 发明授权

US08748284B2 Method of manufacturing decoupling MIM capacitor designs for interposers 有权
标题翻译：制造用于插入件的解耦MIM电容器设计的方法
公开(公告)号：US08748284B2
公开(公告)日：2014-06-10
申请号：US13209195
申请日：2011-08-12
申请人： Kuo-Chyuan Tzeng , Kuo-Chi Tu , Chen-Jong Wang , Hsiang-Fan Lee
发明人： Kuo-Chyuan Tzeng , Kuo-Chi Tu , Chen-Jong Wang , Hsiang-Fan Lee
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L23/147 , H01L23/3114 , H01L23/49822 , H01L23/5223 , H01L24/83 , H01L27/06 , H01L27/0805 , H01L2224/131 , H01L2224/13144 , H01L2224/16235 , H01L2224/16238 , H01L2924/0002 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/00 , H01L2924/014 , H01L2924/00014
摘要： Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device.
摘要翻译：公开了用于插入件的去耦金属绝缘体金属（MIM）电容器设计及其制造方法。在一个实施例中，形成去耦电容器的方法包括提供封装装置，以及在包装装置的至少两个金属化层中形成去耦MIM电容器。

8. 发明授权

US08716100B2 Method of fabricating metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers 有权
标题翻译：在最厚的金属间介电层内制造金属绝缘体金属（MIM）电容器的方法
公开(公告)号：US08716100B2
公开(公告)日：2014-05-06
申请号：US13212922
申请日：2011-08-18
申请人： Kuo-Chyuan Tzeng , Luan C. Tran , Chen-Jong Wang , Kuo-Chi Tu , Hsiang-Fan Lee
发明人： Kuo-Chyuan Tzeng , Luan C. Tran , Chen-Jong Wang , Kuo-Chi Tu , Hsiang-Fan Lee
IPC分类号： H01L21/20
CPC分类号： H01L28/86 , H01L23/5223 , H01L28/40 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KÅ˜30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.
摘要翻译： MIM电容器的实施例可以嵌入到具有足够厚度（例如，10K〜30K）的厚IMD层中以获得高电容，其可以在更薄的IMD层之上。可以在三个相邻的金属层之间形成MIM电容器，这两个相邻的金属层具有两个分开三个相邻金属层的厚的IMD层。诸如TaN或TiN的材料用作底部/顶部电极和Cu屏障。厚IMD层上方的金属层可以用作顶部电极连接。厚IMD层下面的金属层可以用作底部电极连接。电容器可以是不同的形状，例如圆柱形或凹形。可以使用多种材料（Si3N4，ZrO2，HfO2，BST等）作为介电材料。 MIM电容器由一个或两个额外的掩模形成，同时形成电路的其他非电容器逻辑。

9. 发明申请

US20130043560A1 Metal-Insulator-Metal Capacitor and Method of Fabricating 有权
标题翻译：金属绝缘体 - 金属电容器和制造方法
公开(公告)号：US20130043560A1
公开(公告)日：2013-02-21
申请号：US13212922
申请日：2011-08-18
申请人： Kuo-Chyuan Tzeng , Luan C. Tran , Chen-Jong Wang , Kuo-Chi Tu , Hsiang-Fan Lee
发明人： Kuo-Chyuan Tzeng , Luan C. Tran , Chen-Jong Wang , Kuo-Chi Tu , Hsiang-Fan Lee
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L28/86 , H01L23/5223 , H01L28/40 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KÅ˜30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.
摘要翻译： MIM电容器的实施例可以嵌入到具有足够厚度（例如，10K〜30K）的厚IMD层中以获得高电容，其可以在更薄的IMD层之上。可以在三个相邻的金属层之间形成MIM电容器，这两个相邻的金属层具有两个分开三个相邻金属层的厚的IMD层。诸如TaN或TiN的材料用作底部/顶部电极和Cu屏障。厚IMD层上方的金属层可以用作顶部电极连接。厚IMD层下面的金属层可以用作底部电极连接。电容器可以是不同的形状，例如圆柱形或凹形。可以使用多种材料（Si3N4，ZrO2，HfO2，BST等）作为介电材料。 MIM电容器由一个或两个额外的掩模形成，同时形成电路的其他非电容器逻辑。

10. 发明申请

US20080116496A1 Integrating a DRAM with an SRAM having butted contacts and resulting devices 审中-公开
标题翻译：将DRAM与具有对接触点和所产生的器件的SRAM集成
公开(公告)号：US20080116496A1
公开(公告)日：2008-05-22
申请号：US11809642
申请日：2007-06-01
申请人： Kuo-Chyuan Tzeng , Kuo-Chiang Ting , Chen-Jong Wang , Min-Hsiung Chiang , Chih-Yang Pai
发明人： Kuo-Chyuan Tzeng , Kuo-Chiang Ting , Chen-Jong Wang , Min-Hsiung Chiang , Chih-Yang Pai
IPC分类号： H01L27/108
CPC分类号： H01L27/105 , H01L27/10894 , H01L27/11 , H01L27/1116
摘要： A novel SOC structure and method of making the same are provided. An SOC comprises a logic region, an SRRM and a DRAM region. The storage capacitor in a DRAM cell is formed in the first dielectric layer in an MIM (metal-insulator-metal) configuration, having a large vertical surface area. A butted contact, formed in said first dielectric layer, comprises a bottom portion abutting a first and second conductive region in an SRAM cell, and a vertically aligned top portion coupled to a first metal layer. The top portion has a substantially larger depth than that of the bottom portion, while substantially smaller in size. Forming this SOC structure does not require adding complex, error-prone additional processing steps on an existing CMOS manufacturing process, thus having little impact on the overall SOC product yield.
摘要翻译：提供了一种新颖的SOC结构及其制造方法。 SOC包括逻辑区域，SRRM和DRAM区域。金属 - 绝缘体 - 金属）构造中的DRAM单元中的存储电容器形成在第一介电层中，具有大的垂直表面积。形成在所述第一电介质层中的对接触点包括邻接SRAM单元中的第一和第二导电区域的底部以及耦合到第一金属层的垂直对齐的顶部。顶部具有比底部大的深度大得多的深度，而其尺寸基本上更小。形成这种SOC结构不需要在现有的CMOS制造工艺上增加复杂的，容易出错的附加处理步骤，因此对整个SOC产品产量几乎没有影响。

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