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1. 发明授权

US06680239B1 Effective isolation with high aspect ratio shallow trench isolation and oxygen or field implant 失效
标题翻译：有效的隔离与高纵横比浅沟槽隔离和氧或野外植入
公开(公告)号：US06680239B1
公开(公告)日：2004-01-20
申请号：US09624025
申请日：2000-07-24
申请人： Cher Liang Cha , Kok Keng Ong , Alex See , Lap Chan
发明人： Cher Liang Cha , Kok Keng Ong , Alex See , Lap Chan
IPC分类号： H01L2176
CPC分类号： H01L21/76237
摘要： A method for forming shallow trench isolation (STI) with a higher aspect ratio is given. This method allows the formation of narrower and deeper trench isolation regions while avoiding substrate damage due to excessive etching and severe microloading effects. In addition, it yields uniform depth trenches while avoiding problems of etch residue at the bottom of the trench. This method is achieved by using a process where a trench is etched, and an oxide layer grown along the bottom and sidewalls of the trench. Oxygen or field isolation ions are then implanted into the bottom of the trench. A nitride spacer is then formed along the bottom and sidewalls of the trench, followed by an isotropic etch removing the nitride and oxide from the bottom of the trench. An oxide deposition then fills the trench, followed by a planarization step completing the isolation structure.
摘要翻译：给出了一种形成具有较高纵横比的浅沟槽隔离（STI）的方法。该方法允许形成更窄和更深的沟槽隔离区域，同时避免由于过度蚀刻和严重的微负载效应引起的基板损伤。此外，它产生均匀的深度沟槽，同时避免沟槽底部的蚀刻残留问题。该方法通过使用其中蚀刻沟槽的工艺和沿着沟槽的底部和侧壁生长的氧化物层来实现。然后将氧或场隔离离子注入到沟槽的底部。然后沿着沟槽的底部和侧壁形成氮化物间隔物，随后通过各向同性蚀刻从沟槽的底部去除氮化物和氧化物。氧化物沉积然后填充沟槽，随后是完成隔离结构的平坦化步骤。

2. 发明授权

US06303418B1 Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer 有权
标题翻译：制造具有双栅极结构和高介电常数栅极绝缘体层的CMOS器件的方法
公开(公告)号：US06303418B1
公开(公告)日：2001-10-16
申请号：US09607282
申请日：2000-06-30
申请人： Cher Liang Cha , Alex See , Lap Chan
发明人： Cher Liang Cha , Alex See , Lap Chan
IPC分类号： H01L218238
CPC分类号： H01L21/823842
摘要： A method of forming a metal gate structure, on a high k gate insulator layer, for NMOS devices, and simultaneously forming a metal-polysilicon gate structure, on the same high k gate insulator layer, for PMOS devices, has been developed. The method features forming openings in a composite insulator layer, via removal of silicon nitride dummy gate structures that were embedded in a composite insulator layer, with the openings exposing regions of the semiconductor substrate to be used for subsequent NMOS and PMOS channel regions. Deposition of a high k gate insulator layer is followed by deposition of an in situ doped polysilicon layer. After removal of a portion of the in situ doped polysilicon layer located in the NMOS region, a metal layer is deposited on the underlying high k gate insulator layer in the NMOS region, and on the in situ polysilicon layer in the PMOS region. Removal of unwanted regions of metal, and of in situ polysilicon, result in the definition of a metal gate structure, on the high k gate insulator layer, in the NMOS region, and in the definition of a metal—in situ doped polysilicon gate structure, on the high k gate insulator layer, in the PMOS region, with both gate structures embedded in openings in the composite insulator layer, previously formed via removal of the silicon nitride dummy gate structures.
摘要翻译：已经开发了在用于PMOS器件的同一高k栅极绝缘体层上形成用于NMOS器件的高k栅极绝缘体层上并同时形成金属 - 多晶硅栅极结构的金属栅极结构的方法。该方法的特征是在复合绝缘体层中形成开口，通过去除嵌入复合绝缘体层中的氮化硅虚拟栅极结构，其中开口暴露用于随后的NMOS和PMOS沟道区的半导体衬底的区域。沉积高k栅极绝缘体层之后是沉积原位掺杂的多晶硅层。在去除位于NMOS区域中的原位掺杂多晶硅层的一部分之后，金属层沉积在NMOS区域中的下面的高k栅极绝缘体层上以及在PMOS区域中的原位多晶硅层上。去除金属和原位多晶硅的不需要的区域导致在NMOS区域中的高k栅极绝缘体层上以及在金属原位掺杂的多晶硅栅极结构的定义中金属栅极结构的定义在PMOS区域中的高k栅极绝缘体层上，两个栅极结构嵌入在复合绝缘体层中的开口中，预先通过去除氮化硅虚拟栅极结构而形成。

3. 发明授权

US07112866B2 Method to form a cross network of air gaps within IMD layer 有权
标题翻译：在IMD层内形成气隙交叉网络的方法
公开(公告)号：US07112866B2
公开(公告)日：2006-09-26
申请号：US10796893
申请日：2004-03-09
申请人： Lap Chan , Cher Liang Cha , Kheng Chok Tee
发明人： Lap Chan , Cher Liang Cha , Kheng Chok Tee
IPC分类号： H01L29/00 , H01L23/48 , H01L21/331 , H01L21/4765
CPC分类号： H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The invention provides a new multilevel interconnect structure of air gaps in a layer of IMD. A first layer of dielectric is provided over a surface; the surface contains metal points of contact. Trenches are provided in this first layer of dielectric. The trenches are filled with a first layer of nitride or disposable solid and polished. A second layer of dielectric is deposited over the first layer of dielectric. Trenches are formed in the second layer of dielectric, a second layer of nitride or disposable solid is deposited over the second layer of dielectric. The layer of nitride or disposable solid is polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. The thin layer of oxide is masked and etched thereby creating openings in this thin layer of oxide, these openings align with the points of intersect of the trenches in the first layer of dielectric and in the second layer of dielectric. The nitride or removable solid is removed from the trenches. The openings in the thin layer of oxide are closed off leaving a network of trenches that are filled with air in the two layers of dielectric that now function as the Inter Level Dielectric.
摘要翻译：本发明提供了在IMD层中的空气间隙的新的多层互连结构。在表面上提供第一层电介质; 表面含有金属接触点。在第一层电介质中设置沟槽。沟槽填充有第一层氮化物或一次性固体并抛光。第二层介质沉积在第一层电介质上。沟槽形成在第二层电介质中，第二层氮化物或一次性固体沉积在第二层电介质上。抛光氮化物或一次性固体层。在第二电介质层的表面上沉积薄层的氧化物。氧化物的薄层被掩蔽和蚀刻，从而在该薄层氧化物中形成开口，这些开口与第一介电层和第二介质层中的沟槽的交叉点对准。氮化物或可移除的固体从沟槽中去除。氧化物薄层中的开口被封闭，留下在两层电介质中充满空气的沟槽网络，现在这两层电介质用作Inter Level Dielectric。

4. 发明授权

US06252277B1 Embedded polysilicon gate MOSFET 有权
标题翻译：嵌入式多晶硅栅极MOSFET
公开(公告)号：US06252277B1
公开(公告)日：2001-06-26
申请号：US09392392
申请日：1999-09-09
申请人： Lap Chan , Cher Liang Cha , Eng Fong Chor , Gong Hao , Teck Koon Lee
发明人： Lap Chan , Cher Liang Cha , Eng Fong Chor , Gong Hao , Teck Koon Lee
IPC分类号： H01L2972
CPC分类号： H01L29/66621 , H01L29/665 , H01L29/66628 , H01L29/7834
摘要： Formation of a MOSFET with a polysilicon gate electrode embedded within a silicon trench is described. The MOSFET retains all the features of conventional MOSFETs with photolithographically patterned polysilicon gate electrodes, including robust LDD (lightly doped drain) regions formed in along the walls of the trench. Because the gate dielectric is never exposed to plasma etching or aqueous chemical etching, gate dielectric films of under 100 Angstroms may be formed without defects. The problems of over etching, and substrate spiking which are encountered in the manufacture of photolithographically patterned polysilicon gate electrodes do not occur. The entire process utilizes only two photolithographic steps. The first step defines the silicon active area by patterning a field isolation and the second defines a trench within the active area wherein the device is formed. The new process, uses the same total number of photolithographic steps to form the MOSFET device elements as a conventional process but is far more protective of the thin gate oxide.
摘要翻译：描述了形成具有嵌入在硅沟槽内的多晶硅栅电极的MOSFET。 MOSFET保留了具有光刻图案化多晶硅栅电极的常规MOSFET的所有特征，包括沿沟槽壁形成的鲁棒LDD（轻掺杂漏极）区域。因为栅极电介质永远不会暴露于等离子体蚀刻或水性化学蚀刻，所以可以形成低于100埃的栅介质膜而没有缺陷。在光刻图案化多晶硅栅电极的制造中遇到的过蚀刻和衬底尖峰的问题不会发生。整个过程仅使用两个光刻步骤。第一步骤通过图案化场隔离来定义硅有源面积，第二步限定在形成器件的有源区域内的沟槽。新工艺使用相同的光刻步骤总数来形成MOSFET器件元件作为常规工艺，但对薄栅极氧化物的保护更为广泛。

5. 发明授权

US06531750B2 Shallow junction transistors which eliminating shorts due to junction spiking 失效
标题翻译：浅结结晶体管，消除由于接头尖峰引起的短路
公开(公告)号：US06531750B2
公开(公告)日：2003-03-11
申请号：US09943306
申请日：2001-08-31
申请人： Lap Chan , Cher Liang Cha , Ravishankar Sundaresan
发明人： Lap Chan , Cher Liang Cha , Ravishankar Sundaresan
IPC分类号： H01L2976
CPC分类号： H01L29/6659 , H01L21/28044 , H01L29/41775 , H01L29/41783 , H01L29/456 , H01L29/4916 , H01L29/4941 , H01L29/665 , H01L29/66545
摘要： A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions. The second electrode layer is etched through to form separate conductive connections. An intermetal dielectric layer is deposited. The intermetal dielectric layer is etched through to form contact openings. A metal layer is deposited and etched through to form separate metal interconnects. A passivation layer is deposited, and the integrated circuit is completed.
摘要翻译：实现了形成浅结MOSFET的方法。栅极氧化层形成在衬底上。沉积多晶硅或金属的第一电极层。沉积氮化硅层。氮化硅层和第一电极层被蚀刻通过以形成临时MOSFET栅极。将离子注入到衬底中以形成轻掺杂的结。沉积间隔层。间隔层和栅极氧化物层被各向异性地蚀刻以形成侧壁间隔物。将离子注入到衬底中以形成重掺杂的结。蚀刻掉氮化硅层。多晶硅或金属的第二电极层沉积在衬底，侧壁间隔物和第一多晶硅层上。将第二电极层抛光到侧壁间隔物的顶表面以完成MOSFET并形成永久栅极和与源极和漏极结的导电连接。蚀刻第二电极层以形成分开的导电连接。沉积金属间电介质层。金属间电介质层被蚀刻穿过以形成接触开口。金属层被沉积并蚀刻通过以形成单独的金属互连。沉积钝化层，并且集成电路完成。

6. 发明授权

US06297109B1 Method to form shallow junction transistors while eliminating shorts due to junction spiking 失效
标题翻译：形成浅结晶体管的方法，同时消除由于接头尖峰引起的短路
公开(公告)号：US06297109B1
公开(公告)日：2001-10-02
申请号：US09377543
申请日：1999-08-19
申请人： Lap Chan , Cher Liang Cha , Ravishankar Sundaresan
发明人： Lap Chan , Cher Liang Cha , Ravishankar Sundaresan
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/28044 , H01L29/41775 , H01L29/41783 , H01L29/456 , H01L29/4916 , H01L29/4941 , H01L29/665 , H01L29/66545
摘要： A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions. The second electrode layer is etched through to form separate conductive connections. An intermetal dielectric layer is deposited. The intermetal dielectric layer is etched through to form contact openings. A metal layer is deposited and etched through to form separate metal interconnects. A passivation layer is deposited, and the integrated circuit is completed.
摘要翻译：实现了形成浅结MOSFET的方法。栅极氧化层形成在衬底上。沉积多晶硅或金属的第一电极层。沉积氮化硅层。氮化硅层和第一电极层被蚀刻通过以形成临时MOSFET栅极。将离子注入到衬底中以形成轻掺杂的结。沉积间隔层。间隔层和栅极氧化物层被各向异性地蚀刻以形成侧壁间隔物。将离子注入到衬底中以形成重掺杂的结。蚀刻掉氮化硅层。多晶硅或金属的第二电极层沉积在衬底，侧壁间隔物和第一多晶硅层上。将第二电极层抛光到侧壁间隔物的顶表面以完成MOSFET并形成永久栅极和与源极和漏极结的导电连接。蚀刻第二电极层以形成分开的导电连接。沉积金属间电介质层。金属间电介质层被蚀刻穿过以形成接触开口。金属层被沉积并蚀刻通过以形成单独的金属互连。沉积钝化层，并且集成电路完成。

7. 发明授权

US07573081B2 Method to fabricate horizontal air columns underneath metal inductor 有权
标题翻译：在金属电感器下制造水平空气柱的方法
公开(公告)号：US07573081B2
公开(公告)日：2009-08-11
申请号：US11519103
申请日：2006-09-11
申请人： Lap Chan , Kok Wai Johnny Chew , Cher Liang Cha , Chee Tee Chua
发明人： Lap Chan , Kok Wai Johnny Chew , Cher Liang Cha , Chee Tee Chua
IPC分类号： H01L29/78
CPC分类号： H01L21/76834 , H01F3/14 , H01F17/0006 , H01F27/34 , H01F41/041 , H01F41/045 , H01L21/764 , H01L21/7682 , H01L23/5227 , H01L23/53295 , H01L27/08 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.
摘要翻译：提供了一种在硅衬底的表面上形成电感器的新方法。本发明提供金属电感器下面的氧化物鳍片的覆盖层。氧化物鳍片为上覆的金属电感器提供了稳定的支持，同时也允许水平空气柱同时存在于电感器下面。通过重复施用所使用的掩模，可以在本发明的基础上产生空间上插入在所产生的氧化物翅片的覆盖层之间的空腔的覆盖层。衬底表面上的空穴的存在显着降低了与衬底相关联的电感器的寄生电容和串联电阻。

8. 发明授权

US07105420B1 Method to fabricate horizontal air columns underneath metal inductor 有权
公开(公告)号：US07105420B1
公开(公告)日：2006-09-12
申请号：US09413177
申请日：1999-10-07
申请人： Lap Chan , Kok Wai Johnny Chew , Cher Liang Cha , Chee Tee Chua
发明人： Lap Chan , Kok Wai Johnny Chew , Cher Liang Cha , Chee Tee Chua
IPC分类号： H01L21/76
CPC分类号： H01L21/76834 , H01F3/14 , H01F17/0006 , H01F27/34 , H01F41/041 , H01F41/045 , H01L21/764 , H01L21/7682 , H01L23/5227 , H01L23/53295 , H01L27/08 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.

9. 发明授权

US06326272B1 Method for forming self-aligned elevated transistor 失效
标题翻译：用于形成自对准高架晶体管的方法
公开(公告)号：US06326272B1
公开(公告)日：2001-12-04
申请号：US09442496
申请日：1999-11-18
申请人： Lap Chan , Cher Liang Cha
发明人： Lap Chan , Cher Liang Cha
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L21/28123 , H01L29/0653 , H01L29/665 , H01L29/66553 , H01L29/66651
摘要： A method of forming a self-aligned elevated transistor using selective epitaxial growth is described. An oxide layer is provided overlying a semiconductor substrate. The oxide layer is etched through to the semiconductor substrate to form a trench having a lower portion contacting the substrate and an upper portion having a width larger than the width of the lower portion. A silicon layer is grown within the trench using selective epitaxial growth wherein the silicon layer fills the lower portion and partially fills the upper portion. Nitride spacers are formed on the sidewalls of the trench. A polysilicon layer is deposited overlying the oxide layer and within the trench and etched back to form a gate electrode within the trench between the nitride spacers. The nitride spacers are etched away where they are not covered by the gate electrode leaving thin nitride spacers on sidewalls of the gate electrode. Ions are implanted into the silicon layer exposed at the edges of the trench whereby source and drain pockets are formed within the silicon layer wherein the junction depth is determined by the thickness of the silicon layer. A dielectric layer is deposited overlying the oxide layer and the gate electrode and source/drain pockets within the trench to complete formation of the self-aligned elevated transistor in the fabrication of an integrated circuit.
摘要翻译：描述了使用选择性外延生长形成自对准升高的晶体管的方法。设置覆盖在半导体衬底上的氧化物层。氧化层被蚀刻到半导体衬底上以形成具有与衬底接触的下部的沟槽和具有大于下部宽度的宽度的上部的沟槽。使用选择性外延生长在沟槽内生长硅层，其中硅层填充下部并部分填充上部。氮化物间隔物形成在沟槽的侧壁上。沉积覆盖氧化物层并在沟槽内的多晶硅层被回蚀刻以在氮化物间隔物之间的沟槽内形成栅电极。蚀刻氮化物间隔物，在那里它们不被栅极电极覆盖，从而在栅电极的侧壁上留下薄的氮化物间隔物。将离子注入暴露在沟槽边缘处的硅层中，从而在硅层内形成源极和漏极穴，其中结深度由硅层的厚度确定。沉积覆盖在沟槽内的氧化物层和栅电极和源极/漏极腔的电介质层，以在集成电路的制造中完成自对准升高的晶体管的形成。

10. 发明授权

US6051467A Method to fabricate a large planar area ONO interpoly dielectric in flash device 失效
标题翻译：在闪光装置中制造大平面区域ONO内部电介质的方法
公开(公告)号：US6051467A
公开(公告)日：2000-04-18
申请号：US53855
申请日：1998-04-02
申请人： Lap Chan , Cher Liang Cha
发明人： Lap Chan , Cher Liang Cha
IPC分类号： H01L21/28 , H01L29/423 , H01L21/8247
CPC分类号： H01L29/42324 , H01L21/28273
摘要： A new method of fabricating a stacked gate Flash EEPROM device having an improved interpoly oxide layer is described. A gate oxide layer is provided on the surface of a semiconductor substrate. A first polysilicon layer is deposited overlying the gate oxide layer. The first polysilicon layer is etched away where it is not covered by a mask to form a floating gate. Source and drain regions associated with the floating gate are formed within the substrate. An oxide layer is deposited overlying the floating gate and the substrate. The oxide layer is polished away until the top of the oxide layer is even with the top of the floating gate. A second polysilicon layer is deposited overlying the oxide layer and the first polysilicon layer of the floating gate wherein the second polysilicon layer has a smooth surface. An interpoly dielectric layer is deposited overlying the second polysilicon layer. A third polysilicon layer is deposited overlying the interpoly dielectric layer. The third polysilicon layer and the interpoly dielectric layer are etched away where they are not covered by a mask to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate. Contact openings are formed through the insulating layer to the underlying control gate and to the underlying source and drain regions. The contact openings are filled with a conducting layer to complete the fabrication of the Flash EEPROM device.
摘要翻译：描述了一种制造具有改进的叠层氧化物层的堆叠栅极快闪EEPROM器件的新方法。在半导体衬底的表面上设置栅氧化层。沉积在栅极氧化物层上的第一多晶硅层。第一多晶硅层被蚀刻掉，其未被掩模覆盖以形成浮动栅极。与浮栅相关联的源区和漏区形成在衬底内。沉积在浮动栅极和衬底上的氧化物层。将氧化物层抛光直到氧化物层的顶部与浮动栅极的顶部均匀。第二多晶硅层沉积在覆盖氧化物层和浮置栅极的第一多晶硅层上，其中第二多晶硅层具有光滑表面。沉积在第二多晶硅层上的多层介电层。第三多晶硅层沉积在层间介电层上。第三多晶硅层和多晶硅间介电层被蚀刻掉，其中它们不被掩模覆盖以形成覆盖浮栅的控制栅极。绝缘层沉积在氧化层和控制栅上。通过绝缘层到底层控制栅极和底层的源极和漏极区域形成接触开口。接触开口填充有导电层以完成闪速EEPROM装置的制造。

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