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1. 发明申请

US20130256834A1 BACK-SIDE MOM/MIM DEVICES 有权
标题翻译：背面MOM / MIM设备
公开(公告)号：US20130256834A1
公开(公告)日：2013-10-03
申请号：US13430778
申请日：2012-03-27
申请人： Juan Boon TAN , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah , Shunqiang Gong
发明人： Juan Boon TAN , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah , Shunqiang Gong
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L23/5223 , H01L23/481 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Back-side MOM/MIM structures are integrated on a device with front-side circuitry. Embodiments include forming a substrate having a front side and a back side that is opposite the front side, the substrate including circuitry on the front side of the substrate; and forming a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or a combination thereof on the back side of the substrate. Other embodiments include forming a through-silicon via (TSV), in the substrate, connecting the MOM capacitor, the MIM capacitor, or a combination thereof to the circuitry on the front side of the substrate.
摘要翻译：背面MOM / MIM结构集成在具有前端电路的设备上。实施例包括形成具有与前侧相对的前侧和后侧的基板，所述基板在基板的正面上包括电路; 以及在衬底的背面上形成金属 - 氧化物 - 金属（MOM）电容器，金属 - 绝缘体 - 金属（MIM）电容器或其组合。其他实施例包括在衬底中形成穿硅通孔（TSV），将MOM电容器，MIM电容器或其组合连接到衬底前侧上的电路。

2. 发明授权

US06558994B2 Dual silicon-on-insulator device wafer die 失效
公开(公告)号：US06558994B2
公开(公告)日：2003-05-06
申请号：US09841564
申请日：2001-03-01
申请人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
发明人： Randall Cher Liang Cha , Yeow Kheng Lim , Alex See , Tae Jong Lee , Wang Ling Goh
IPC分类号： H01L2100
CPC分类号： H01L21/76264 , H01L21/76278 , H01L21/76281 , H01L21/76283 , H01L2924/0002 , Y10S438/967 , H01L2924/00
摘要： A silicon-on-insulator semiconductor device and manufacturing method therefor is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on the semiconductor wafer forms a partially depleted silicon-on-insulator device.

3. 发明授权

US06319767B1 Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique 有权
标题翻译：用于通过等离子体灰化和硬掩蔽技术消除MIM电容器底金属图案化期间的顶部金属角成形的方法
公开(公告)号：US06319767B1
公开(公告)日：2001-11-20
申请号：US09798639
申请日：2001-03-05
申请人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
发明人： Randall Cher Liang Cha , Tae Jong Lee , Alex See , Lap Chan , Yeow Kheng Lim
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/31122 , H01L21/31144 , H01L21/32136 , H01L21/32139
摘要： A method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is described. An insulating layer is provided overlying a semiconductor substrate. A composite metal stack is formed comprising a first metal layer overlying the insulating layer, a capacitor dielectric layer overlying the first metal layer, a second metal layer overlying the capacitor dielectric layer, and a hard mask layer overlying the second metal layer. A first photoresist mask is formed overlying the hard mask layer. The composite metal stack is patterned using the first photoresist mask as an etching mask whereby the patterned first metal layer forms a bottom electrode of the capacitor. A portion of the first photoresist mask is removed by plasma ashing to form a second photoresist mask narrower than the first photoresist mask. The hard mask layer is patterned using the second photoresist mask as an etching mask. The second metal layer is patterned using the hard mask layer as an etching mask whereby the second metal layer forms a top electrode of the capacitor to complete fabrication of a metal-insulator-metal capacitor.
摘要翻译：描述了一种用于制造金属 - 绝缘体 - 金属电容器的方法，其中消除了图案化期间的顶部金属角成形。绝缘层设置在半导体衬底上。形成复合金属堆叠，其包括覆盖绝缘层的第一金属层，覆盖第一金属层的电容器电介质层，覆盖电容器电介质层的第二金属层和覆盖第二金属层的硬掩模层。第一光致抗蚀剂掩模形成在硬掩模层上。使用第一光致抗蚀剂掩模将复合金属堆叠图案化为蚀刻掩模，由此图案化的第一金属层形成电容器的底部电极。通过等离子体灰化除去第一光致抗蚀剂掩模的一部分，以形成比第一光致抗蚀剂掩模窄的第二光刻胶掩模。使用第二光致抗蚀剂掩模将硬掩模层图案化为蚀刻掩模。使用硬掩模层作为蚀刻掩模对第二金属层进行构图，由此第二金属层形成电容器的顶部电极，以完成金属 - 绝缘体 - 金属电容器的制造。

4. 发明授权

US09318378B2 Slot designs in wide metal lines 有权
公开(公告)号：US09318378B2
公开(公告)日：2016-04-19
申请号：US10923123
申请日：2004-08-21
申请人： Yeow Kheng Lim , Alex See , Tae Jong Lee , David Vigar , Liang Choo Hsia , Kin Leong Pey
发明人： Yeow Kheng Lim , Alex See , Tae Jong Lee , David Vigar , Liang Choo Hsia , Kin Leong Pey
IPC分类号： H01L21/76 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532
CPC分类号： H01L23/528 , H01L21/0276 , H01L21/288 , H01L21/3212 , H01L21/76802 , H01L21/76808 , H01L21/76816 , H01L21/7684 , H01L21/76843 , H01L21/7685 , H01L21/76879 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

5. 发明授权

US08860185B2 Crack-arresting structure for through-silicon vias 有权
标题翻译：通硅通孔的破裂结构
公开(公告)号：US08860185B2
公开(公告)日：2014-10-14
申请号：US13357960
申请日：2012-01-25
申请人： Shaoning Yuan , Yue Kang Lu , Yeow Kheng Lim , Juan Boon Tan
发明人： Shaoning Yuan , Yue Kang Lu , Yeow Kheng Lim , Juan Boon Tan
IPC分类号： H01L23/544
CPC分类号： H01L23/585 , H01L23/481 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05572 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/014
摘要： The subject matter disclosed herein relates to structures formed on semiconductor chips that are used for at least partially addressing the thermally induced stresses and metallization system cracking problems in a semiconductor chip that may be caused by the presence of through-silicon vias (TSV's), and which may be due primarily to the significant differences in thermal expansion between the materials of the TSV's and the semiconductor-based materials that generally make up the remainder of the semiconductor chip. One device disclosed herein includes a substrate and a crack-arresting structure positioned above the substrate, the crack-arresting structure comprising a plurality of crack-arresting elements and having a perimeter when viewed from above. The device also includes a conductive structure positioned at least partially within the perimeter of the crack-arresting structure, and a conductive element extending through an opening in the crack-arresting structure, wherein the conductive element is conductively coupled to the conductive structure.
摘要翻译：本文公开的主题涉及形成在半导体芯片上的结构，其用于至少部分地解决半导体芯片中可能由于存在穿硅通孔（TSV）而导致的热诱导应力和金属化系统开裂问题，以及这可能主要是由于TSV的材料与通常构成半导体芯片的其余部分的半导体材料之间的热膨胀的显着差异。本文公开的一种装置包括基底和位于基底上方的裂缝阻止结构，所述裂缝阻止结构包括多个裂缝阻止元件，并且当从上方观察时具有周边。该装置还包括至少部分地位于裂缝阻止结构的周边内的导电结构，以及延伸穿过裂缝阻止结构中的开口的导电元件，其中导电元件与导电结构导电耦合。

6. 发明授权

US08766454B2 Integrated circuit with self-aligned line and via 有权
标题翻译：具有自对准线和通孔的集成电路
公开(公告)号：US08766454B2
公开(公告)日：2014-07-01
申请号：US11466018
申请日：2006-08-21
申请人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh
发明人： Yeow Kheng Lim , Randall Cher Liang Cha , Alex See , Wang Ling Goh
IPC分类号： H01L23/48 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.
摘要翻译：提供一种集成电路，其具有形成在其上的第一电介质层的基极。在第一电介质层上形成第二电介质层。第三电介质层形成在第二电介质层上的间隔开的条带中。第一沟槽开口通过第三和第二电介质层形成在第三介电层间隔开的条之间。第二沟槽开口与通过第一介电层的第一沟槽开口连续地形成在第三介电层的间隔开的条之间。沟槽开口中的导体金属形成自对准沟槽互连。

7. 发明授权

US06380084B1 Method to form high performance copper damascene interconnects by de-coupling via and metal line filling 有权
标题翻译：通过去耦合通孔和金属线填充形成高性能铜镶嵌互连的方法
公开(公告)号：US06380084B1
公开(公告)日：2002-04-30
申请号：US09678621
申请日：2000-10-02
申请人： Yeow Kheng Lim , Alex See , Cher Liang Cha , Subhash Gupta , Wang Ling Goh , Man Siu Tse
发明人： Yeow Kheng Lim , Alex See , Cher Liang Cha , Subhash Gupta , Wang Ling Goh , Man Siu Tse
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/32051 , H01L21/76802 , H01L21/76849 , H01L21/7685 , H01L21/76877 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method to form robust dual damascene interconnects by decoupling via and connective line trench filling has been achieved. A first dielectric layer is deposited overlying a silicon nitride layer. A shielding layer is deposited. The shielding layer, the first dielectric layer, and the silicon nitride layer are patterned to form via trenches. A first barrier layer is deposited to line the trenches. The via trenches are filled with a first copper layer by a single deposition or by depositing a seed layer and then electroless or electrochemical plating. The first copper layer is polished down to complete the vias. A second barrier layer is deposited. The second barrier layer is patterned to form via caps. A second dielectric layer is deposited. A capping layer is deposited. The capping layer and the second dielectric layer are patterned to form connective line trenches that expose a part of the via caps. A third barrier layer is deposited to line the connective line trenches. The third barrier layer and the via caps are etched to form trench barrier sidewall spacers and to expose the vias. The connective line trenches are filled with a second copper layer by a single deposition, by a first deposition of a seed layer followed by plating, or by plating using the via as the seed layer. The second copper layer is polished down.
摘要翻译：已经实现了通过解耦通孔和连接线沟槽填充形成鲁棒的双镶嵌互连的方法。沉积在氮化硅层上的第一介电层。屏蔽层被沉积。将屏蔽层，第一介电层和氮化硅层图案化以形成通孔沟槽。沉积第一势垒层以对沟槽进行排列。通过单个沉积或通过沉积种子层然后进行无电镀或电化学电镀，将通孔沟槽填充有第一铜层。第一个铜层被抛光以完成通孔。沉积第二阻挡层。图案化第二阻挡层以形成通孔。沉积第二介电层。沉积覆盖层。图案化覆盖层和第二介电层以形成连接线沟槽，其暴露通孔盖的一部分。沉积第三阻挡层以对连接线沟槽进行排列。蚀刻第三阻挡层和通孔盖以形成沟槽阻挡侧壁间隔件并露出通孔。连接线沟槽通过单次沉积，通过第一次沉积种子层，然后电镀，或通过使用通孔作为种子层进行电镀，填充第二铜层。第二个铜层被抛光。

8. 发明授权

US06355563B1 Versatile copper-wiring layout design with low-k dielectric integration 失效
标题翻译：多功能铜线布局设计，低k电介质集成
公开(公告)号：US06355563B1
公开(公告)日：2002-03-12
申请号：US09798652
申请日：2001-03-05
申请人： Randall Cher Liang Cha , Alex See , Yeow Kheng Lim , Tae Jong Lee , Lap Chan
发明人： Randall Cher Liang Cha , Alex See , Yeow Kheng Lim , Tae Jong Lee , Lap Chan
IPC分类号： H01L2144
CPC分类号： H01L21/76802 , H01L21/76825 , H01L21/76831 , H01L21/76832
摘要： A method to integrate low dielectric constant dielectric materials with copper metallization is described. A metal line is provided overlying a semiconductor substrate and having a nitride capping layer thereover. A polysilicon layer is deposited over the nitride layer and patterned to form dummy vias. A dielectric liner layer is conformally deposited overlying the nitride layer and dummy vias. A dielectric layer having a low dielectric constant is spun-on overlying the liner layer and covering the dummy vias. The dielectric layer is polished down whereby the dummy vias are exposed. Thereafter, the dielectric layer is cured whereby a cross-linked surface layer is formed. The dummy vias are removed thereby exposing a portion of the nitride layer within the via openings. The exposed nitride layer is removed. The via openings are filled with a copper layer which is planarized to complete copper metallization in the fabrication of an integrated circuit device.
摘要翻译：描述了一种将低介电常数电介质材料与铜金属化相结合的方法。金属线设置在半导体衬底上并且在其上具有氮化物覆盖层。多晶硅层沉积在氮化物层上并被图案化以形成虚拟通孔。电介质衬垫层共形沉积在氮化物层和虚拟通孔之上。将具有低介电常数的介电层旋涂在衬层上并覆盖虚拟通孔。抛光电介质层，从而暴露虚拟通孔。此后，电介质层被固化，由此形成交联表面层。去除虚设通孔，从而将通孔的一部分氮化物层露出。去除暴露的氮化物层。通孔开口填充有铜层，该铜层在集成电路器件的制造中被平坦化以完成铜金属化。

9. 发明申请

US20140035155A1 DEVICE WITH INTEGRATED POWER SUPPLY 有权
标题翻译：具有集成电源的设备
公开(公告)号：US20140035155A1
公开(公告)日：2014-02-06
申请号：US13565748
申请日：2012-08-02
申请人： Juan Boon TAN , Yeow Kheng LIM , Soh Yun SIAH , Wei LIU , Shunqiang GONG
发明人： Juan Boon TAN , Yeow Kheng LIM , Soh Yun SIAH , Wei LIU , Shunqiang GONG
IPC分类号： H01L23/48 , H01L21/50 , H01L21/768
CPC分类号： H01L23/49827 , H01L23/147 , H01L23/481 , H01L23/58 , H01L2224/16225
摘要： Semiconductor devices and methods for forming a semiconductor device are disclosed. The semiconductor device includes a die. The die includes a die substrate having first and second major surfaces. The semiconductor device includes a power module disposed below the second major surface of the die substrate. The power module is electrically coupled to the die through through silicon via (TSV) contacts.
摘要翻译：公开了用于形成半导体器件的半导体器件和方法。该半导体器件包括一个管芯。模具包括具有第一和第二主表面的模具基板。半导体器件包括设置在管芯衬底的第二主表面下方的功率模块。电源模块通过硅通孔（TSV）触点电连接到管芯。

10. 发明申请

US20130277810A1 METHOD FOR FORMING HEAT SINK WITH THROUGH SILICON VIAS 审中-公开
标题翻译：通过硅酮形成热沉的方法
公开(公告)号：US20130277810A1
公开(公告)日：2013-10-24
申请号：US13453762
申请日：2012-04-23
申请人： Juan Boon Tan , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah
发明人： Juan Boon Tan , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah
IPC分类号： H01L29/02 , H01L21/768
CPC分类号： H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices are formed with through silicon vias extending into the semiconductor substrate from a backside surface for improved heat dissipation. Embodiments include forming a cavity in a backside surface of a substrate, the substrate including a gate stack on a frontside surface, and filling the cavity with a thermally conductive material.
摘要翻译：半导体器件通过从后侧表面延伸到半导体衬底中的硅通孔形成，以改善散热。实施例包括在衬底的背面形成空腔，衬底包括在前表面上的栅叠层，并用导热材料填充空腔。

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