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1. 发明授权

US06362071B1 Method for forming a semiconductor device with an opening in a dielectric layer 有权
标题翻译：用于形成在电介质层中具有开口的半导体器件的方法
公开(公告)号：US06362071B1
公开(公告)日：2002-03-26
申请号：US09542706
申请日：2000-04-05
申请人： Bich-Yen Nguyen , William J. Taylor, Jr. , Philip J. Tobin , David L. O'Meara , Percy V. Gilbert , Yeong-Jyh T. Lii , Victor S. Wang
发明人： Bich-Yen Nguyen , William J. Taylor, Jr. , Philip J. Tobin , David L. O'Meara , Percy V. Gilbert , Yeong-Jyh T. Lii , Victor S. Wang
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/823481
摘要： In accordance with one embodiment of the present invention, a method is disclosed for forming a semiconductor device having an isolation region (601). A dielectric layer (108) is deposited and etched to form isolation regions (102, 605) having top portions that are narrower than their bottom portions, thereby a tapered isolation region is formed. Active regions (601, 603) are formed using an epitaxial process in the regions between the isolation regions. The resulting active regions (601, 603) have a greater amount of surface area near a top portion, than near a bottom portion. Transistors (721, 723) having opposite polarities are formed within the active areas.
摘要翻译：根据本发明的一个实施例，公开了一种用于形成具有隔离区域（601）的半导体器件的方法。沉积和蚀刻电介质层（108）以形成具有比其底部部分更窄的顶部部分的隔离区域（102,605），从而形成锥形隔离区域。在隔离区域之间的区域中使用外延工艺形成有源区（601,603）。所得活性区域（601,603）在顶部附近具有比在底部附近更大的表面积。在有源区域内形成具有相反极性的晶体管（721,723）。

2. 发明授权

US06891229B2 Inverted isolation formed with spacers 有权
标题翻译：与隔离件形成反向隔离
公开(公告)号：US06891229B2
公开(公告)日：2005-05-10
申请号：US10426296
申请日：2003-04-30
申请人： Andrea Franke , Jonathan Cobb , John M. Grant , Al T. Koh , Yeong-Jyh T. Lii , Bich-Yen Nguyen , Anna M. Phillips
发明人： Andrea Franke , Jonathan Cobb , John M. Grant , Al T. Koh , Yeong-Jyh T. Lii , Bich-Yen Nguyen , Anna M. Phillips
IPC分类号： H01L21/762 , H01L27/01 , H01L29/00
CPC分类号： H01L21/762
摘要： A method of forming a semiconductor device so as to provide the device inverted isolation trenches with convex sidewalls. Initially, a plurality of composite isolation posts (50, 51) are formed on a substrate (40) through successive deposition, lithography, and etching steps. The posts comprise a bottom layer (501, 502) of silicon dioxide and an overlying etch-stop layer of silicon nitride (502, 512). An insulating material (60) is then deposited over the isolation posts and areas of the substrate. Isolation structures (70,71) are established by etching the insulating material to form convex sidewall spacers (701,702, 711, 712) at the vertical walls of the isolation posts. Active areas (80) between spacers are filled with semiconductor material. In an embodiment, a strained cap layer (101) may be imposed on the active areas. The strained cap layer has a lattice constant that is different from the lattice constant of the semiconductor material.
摘要翻译：一种形成半导体器件以便提供具有凸形侧壁的器件反向隔离沟槽的方法。最初，通过连续沉积，光刻和蚀刻步骤，在基板（40）上形成多个复合隔离柱（50,51）。柱包括二氧化硅的底层（501,502）和上覆的氮化硅蚀刻停止层（502,512）。然后将绝缘材料（60）沉积在衬底的隔离柱和区域上。通过蚀刻绝缘材料以在隔离柱的垂直壁处形成凸形侧壁间隔件（701,702,711,712）来建立隔离结构（70,71）。间隔物之间的有源区（80）填充有半导体材料。在一个实施例中，应变盖层（101）可以施加在活动区域上。应变盖层具有与半导体材料的晶格常数不同的晶格常数。

3. 发明授权

US06838354B2 Method for forming a passivation layer for air gap formation 有权
标题翻译：形成气隙形成钝化层的方法
公开(公告)号：US06838354B2
公开(公告)日：2005-01-04
申请号：US10327403
申请日：2002-12-20
申请人： Cindy K. Goldberg , Stanley Michael Filipiak , John C. Flake , Yeong-Jyh T. Lii , Bradley P. Smith , Yuri E. Solomentsev , Terry G. Sparks , Kirk J. Strozewski , Kathleen C. Yu
发明人： Cindy K. Goldberg , Stanley Michael Filipiak , John C. Flake , Yeong-Jyh T. Lii , Bradley P. Smith , Yuri E. Solomentsev , Terry G. Sparks , Kirk J. Strozewski , Kathleen C. Yu
IPC分类号： H01L21/288 , H01L21/768 , H01L21/76
CPC分类号： H01L21/76844 , H01L21/288 , H01L21/7682 , H01L21/76849 , H01L21/76874
摘要： Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.

4. 发明授权

US06774053B1 Method and structure for low-k dielectric constant applications 有权
标题翻译：低k介电常数应用的方法和结构
公开(公告)号：US06774053B1
公开(公告)日：2004-08-10
申请号：US10384350
申请日：2003-03-07
申请人： Errol Todd Ryan , Cindy K. Goldberg , Yuri Solomentsev , Yeong-Jyh T. Lii
发明人： Errol Todd Ryan , Cindy K. Goldberg , Yuri Solomentsev , Yeong-Jyh T. Lii
IPC分类号： H01L2131
CPC分类号： H01L21/76835 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L21/76829 , H01L21/7684
摘要： The present invention provides a low-k dielectric constant structure and method of forming the same on a substrate 10 that features having a dielectric layer 20 with differing regions of density 12 and 18. To that end, the method includes depositing, upon the substrate, a dielectric layer having first and second density regions. The density associated with the second density region being greater than the density associated with the first density region, and the first density region being disposed between the substrate and the second density region.
摘要翻译：本发明提供了一种低k介电常数结构及其在衬底10上形成的方法，其特征在于具有不同密度区域12和18的电介质层20.为此，该方法包括在衬底上沉积，具有第一和第二密度区域的电介质层。与第二密度区域相关联的密度大于与第一密度区域相关联的密度，并且第一密度区域设置在衬底和第二密度区域之间。

5. 发明授权

US06369430B1 Method of preventing two neighboring contacts from a short-circuit caused by a void between them and device having the same 失效
标题翻译：防止两个相邻触点之间的空隙引起的短路的装置和具有该触点的装置的方法
公开(公告)号：US06369430B1
公开(公告)日：2002-04-09
申请号：US09823310
申请日：2001-04-02
申请人： Olubunmi O. Adetutu , Yeong-Jyh T. Lii , Paul A. Grudowski
发明人： Olubunmi O. Adetutu , Yeong-Jyh T. Lii , Paul A. Grudowski
IPC分类号： H01L2976
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/7682 , H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： Insulating layers between transistors that are very close together may have voids. When contacts are formed in these areas between these close transistors, the contact hole is formed at the void location. These voids may extend between the contact locations that are close together so that the deposition of the conductive material into these contact holes may extend sufficiently into the void to short two such contacts. This is prevented by placing a liner in the contact hole, which constricts the void size in the contact hole, prior to depositing the conductive material. This restricts ingress of conductive material into the void. This prevents the void from being an unwanted conduction path between two contacts that are in close proximity. The bottoms of the contact holes are etched to remove the liner prior to depositing the conductive material.
摘要翻译：非常靠近在一起的晶体管之间的绝缘层可能具有空隙。当在这些紧密晶体管之间的这些区域中形成接触时，在空隙位置处形成接触孔。这些空隙可以在靠近在一起的接触位置之间延伸，使得导电材料沉积到这些接触孔中可以充分地延伸到空隙中以短两个这样的接触。在沉积导电材料之前，通过将衬垫放置在接触孔中来限制接触孔中的空隙尺寸来防止这种情况。这限制了导电材料进入空隙。这样可以防止这两个触点之间的不必要的导电路径的空隙处于非常接近的位置。在沉积导电材料之前蚀刻接触孔的底部以去除衬垫。

6. 发明授权

US5378312A Process for fabricating a semiconductor structure having sidewalls 失效
标题翻译：制造具有侧壁的半导体结构的工艺
公开(公告)号：US5378312A
公开(公告)日：1995-01-03
申请号：US164223
申请日：1993-12-07
申请人： George G. Gifford , Yeong-Jyh T. Lii , Jin J. Wu
发明人： George G. Gifford , Yeong-Jyh T. Lii , Jin J. Wu
IPC分类号： B08B7/00 , H01L21/02 , H01L21/311 , H01L21/3213 , H01L21/00
CPC分类号： H01L21/02071 , B08B7/0092 , H01L21/31116 , Y10S438/963
摘要： A method of fabricating a semiconductor structure includes the steps of providing a semiconductor substrate having a material disposed thereon, masking the material with a mask having an appropriate pattern for forming a semiconductor structure, etching unmasked portions of the material so as to form the semiconductor structure, wherein the etching produces a film which attaches onto the semiconductor structure and/or on the semiconductor substrate, and removing the film from the semiconductor structure according to the steps of producing a cryogenic jet stream having cryogenic particles therein, and directing the cryogenic jet stream at the film such that the crogenic jet stream impinges on and causes the film to decrease in temperature so that a high temperature gradient develops between the film and the semiconductor structure, the film detaching from the semiconductor structure and fracturing due to contraction caused by the decrease in temperature and high temperature gradient.
摘要翻译：一种制造半导体结构的方法包括以下步骤：提供具有设置在其上的材料的半导体衬底，用具有用于形成半导体结构的适当图案的掩模掩蔽该材料，蚀刻材料的未屏蔽部分以形成半导体结构其中所述蚀刻产生附着到所述半导体结构和/或所述半导体衬底上的膜，并且根据在其中制备其中具有低温颗粒的低温喷射流的步骤从所述半导体结构去除所述膜，以及引导所述低温射流在膜上使得致动喷流影响并导致膜的温度降低，使得在膜和半导体结构之间产生高温梯度，膜与半导体结构分离并由于减少引起的收缩而断裂在温度和高温梯度下。

7. 发明授权

US07176574B2 Semiconductor device having a multiple thickness interconnect 有权
标题翻译：具有多重厚度互连的半导体器件
公开(公告)号：US07176574B2
公开(公告)日：2007-02-13
申请号：US10946675
申请日：2004-09-22
申请人： Kathleen C. Yu , Kirk J. Strozewski , Janos Farkas , Hector Sanchez , Yeong-Jyh T. Lii
发明人： Kathleen C. Yu , Kirk J. Strozewski , Janos Farkas , Hector Sanchez , Yeong-Jyh T. Lii
IPC分类号： H01L23/52
CPC分类号： H01L23/5283 , H01L21/76807 , H01L21/76816 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.
摘要翻译：导线的厚度变化，有助于克服RC延迟和噪声耦合。通过改变线路厚度，如果需要在导体之间保持规定的最小间距，同时保持预定的期望的RC参数和导线的噪声特性，则避免导体宽度的变化。通过将介电层蚀刻成不同的厚度来实现导体深度变化。电介质层上的不同厚度的导电填充导致厚度变化的导线。在特定金属水平可用的不同的导线厚度可以另外用于除信号或电源导线之外的半导体结构，例如器件的触点，通孔或电极。为了满足期望的设计标准，确定互连厚度如何变化所需的厚度分析可以是自动化的并且作为CAD工具提供。

8. 发明授权

US06815820B2 Method for forming a semiconductor interconnect with multiple thickness 有权
标题翻译：用于形成具有多个厚度的半导体互连的方法
公开(公告)号：US06815820B2
公开(公告)日：2004-11-09
申请号：US10141714
申请日：2002-05-09
申请人： Kathleen C. Yu , Kirk J. Strozewski , Janos Farkas , Hector Sanchez , Yeong-Jyh T. Lii
发明人： Kathleen C. Yu , Kirk J. Strozewski , Janos Farkas , Hector Sanchez , Yeong-Jyh T. Lii
IPC分类号： H01L2348
CPC分类号： H01L23/5283 , H01L21/76807 , H01L21/76816 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.

9. 发明授权

US06689676B1 Method for forming a semiconductor device structure in a semiconductor layer 有权
标题翻译：在半导体层中形成半导体器件结构的方法
公开(公告)号：US06689676B1
公开(公告)日：2004-02-10
申请号：US10206475
申请日：2002-07-26
申请人： Daniel Thanh-Khac Pham , Al T. Koh , Yeong-Jyh T. Lii , Robert F. Steimle , Anne Vandooren , Ricardo Garcia , Kimberly G. Reid , Marc Rossow , James P. Geren
发明人： Daniel Thanh-Khac Pham , Al T. Koh , Yeong-Jyh T. Lii , Robert F. Steimle , Anne Vandooren , Ricardo Garcia , Kimberly G. Reid , Marc Rossow , James P. Geren
IPC分类号： H01L213205
CPC分类号： H01L29/517 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/4933 , H01L29/51
摘要： A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.
摘要翻译：用于提供具有至少两种不同功函数的晶体管栅极的方法利用两种不同金属在不同时间的硅化，一个栅极的硅化，另一个的硅化，或使用具有两个不同掺杂硅结构的单一金属的硅化。因此，避免了与同时进行两种不同金属的硅化相关的问题。如果两种金属具有明显不同的硅化物温度，则由于必须也经历用其它金属进行硅化所需的较高温度，具有较低温度硅化的温度可能会显着降低性能。

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