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1. 发明授权

US07091128B2 Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs 失效
标题翻译：避免氧化物底切在薄间隔FET预硅化物清洗过程中的方法
公开(公告)号：US07091128B2
公开(公告)日：2006-08-15
申请号：US11266855
申请日：2005-11-04
申请人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A. Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
发明人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A. Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L21/302
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.
摘要翻译：描述了在预硅化物清洁步骤期间以避免电介质层底切的方式形成CMOS器件的方法。在形成包括半导体衬底表面上的栅极堆叠的CMOS器件的情况下，图案化栅极堆叠包括在具有垂直侧壁的导体下方的栅极电介质，在衬底表面之上和之上形成介电层。在每个垂直侧壁处形成覆盖在电介质层上的各种氮化物间隔元件。使用蚀刻工艺去除衬底表面上的电介质层，使得保留每个间隔物下面的介电层的一部分。然后，在整个样品（栅极堆叠，每个栅极侧壁和衬底表面处的间隔元件）上沉积氮化物层，然后通过蚀刻工艺去除，使得仅一部分所述氮化物膜（“插塞”）遗迹。插头密封并封装每个所述间隔件下面的电介质层，从而防止在随后的硅化物前处理过程中电介质材料被切削。通过防止底切，本发明还防止蚀刻停止膜（在接触形成之前沉积）与栅极氧化物接触。因此，能够实现提高晶体管驱动电流所需的薄间隔晶体管几何形状的集成。

2. 发明授权

US5349224A Integrable MOS and IGBT devices having trench gate structure 失效
标题翻译：具有沟槽栅极结构的可集成MOS和IGBT器件
公开(公告)号：US5349224A
公开(公告)日：1994-09-20
申请号：US85845
申请日：1993-06-30
申请人： Percy V. Gilbert , Gerold W. Neudeck
发明人： Percy V. Gilbert , Gerold W. Neudeck
IPC分类号： H01L21/28 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/423 , H01L29/739 , H01L29/78 , H01L27/02
CPC分类号： H01L29/7825 , H01L21/2815 , H01L29/66325 , H01L29/66348 , H01L29/7398 , H01L29/0696 , H01L29/4232 , H01L29/42376
摘要： A power semiconductor device which is integrable in an integrated circuit includes a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween, second and third doped regions of a second conductivity type formed in the first doped region, the second and third doped regions being spaced apart and abutting the first surface, and fourth and fifth doped regions of the first conductivity type respectively formed in the second and third doped regions and abutting the first surface. Sixth and seventh doped regions extend from the first surface into the first region, the sixth region being adjacent to the second and fourth regions and spaced therefrom by an electrically insulative layer, the seventh region being adjacent to the third and fifth regions and spaced therefrom by an insulative layer. The first doped region extends toward the first surface between the sixth and seventh regions and separated therefrom by an electrically insulative layer of variable thickness suitable for voltage blocking. An eighth doped region in the first doped region between the sixth and seventh regions abuts the first surface and forms the drain of a MOSFET or the anode of an IGBT. In fabricating the device, reactive ion etching is used to from a trench in which the sixth and seventh regions are formed. The trench is filled by epitaxially grown semiconductor material in which the eighth doped region is formed. The fourth and fifth doped regions form the source of a MOSFET or a cathode of an IGBT. All ohmic contacts to the device can be made on the first surface.
摘要翻译：可集成在集成电路中的功率半导体器件包括具有第一和第二主要相对表面的半导体本体，其间具有第一导电类型的第一掺杂区域，第二导电类型的第二和第三掺杂区域形成在第一掺杂区域中第二和第三掺杂区域间隔开并邻接第一表面以及分别形成在第二和第三掺杂区域中并邻接第一表面的第一导电类型的第四和第五掺杂区域。第六和第七掺杂区域从第一表面延伸到第一区域，第六区域与第二和第四区域相邻并且由电绝缘层隔开，第七区域与第三和第五区域相邻并且与第三区域和第五区域间隔开绝缘层。第一掺杂区域朝向第六和第七区域之间的第一表面延伸，并且通过适于电压阻挡的可变厚度的电绝缘层与之分离。在第六和第七区域之间的第一掺杂区域中的第八掺杂区域邻接第一表面并形成MOSFET的漏极或IGBT的阳极。在制造该器件时，从其中形成第六和第七区域的沟槽使用反应离子蚀刻。通过外延生长的半导体材料填充沟槽，其中形成第八掺杂区域。第四和第五掺杂区域形成MOSFET的MOSFET或阴极的源极。所有欧姆接触器件可以在第一个表面上进行。

3. 发明授权

US06806584B2 Semiconductor device structure including multiple fets having different spacer widths 有权
标题翻译：半导体器件结构包括具有不同间隔物宽度的多个翅片
公开(公告)号：US06806584B2
公开(公告)日：2004-10-19
申请号：US10277907
申请日：2002-10-21
申请人： Ka Hing Fung , Percy V. Gilbert
发明人： Ka Hing Fung , Percy V. Gilbert
IPC分类号： H01L27088
CPC分类号： H01L21/823864 , Y10S257/90
摘要： A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a spacer having a second width, the first width being different than said second width. Preferably, the first width is narrower than the second width.
摘要翻译：半导体器件结构包括形成在同一衬底上的至少两个场效应晶体管，所述第一场效应晶体管包括具有第一宽度的间隔物，所述第二场效应晶体管包括具有第二宽度的间隔物，所述第一宽度不同于所述第二宽度宽度。优选地，第一宽度比第二宽度窄。

4. 发明授权

US5773326A Method of making an SOI integrated circuit with ESD protection 失效
标题翻译：制造具有ESD保护的SOI集成电路的方法
公开(公告)号：US5773326A
公开(公告)日：1998-06-30
申请号：US710702
申请日：1996-09-19
申请人： Percy V. Gilbert , Paul G. Y. Tsui , Stephen G. Jamison , James W. Miller
发明人： Percy V. Gilbert , Paul G. Y. Tsui , Stephen G. Jamison , James W. Miller
IPC分类号： H01L21/84 , H01L27/02 , H01L27/12 , H01L21/786
CPC分类号： H01L27/0251 , H01L21/84 , H01L27/1203 , Y10S438/981
摘要： An SOI structure (20) includes a semiconductor layer (15) formed on an insulating substrate (12). The semiconductor layer (15) is partitioned into an ESD protection portion (32) and a circuitry portion (34). A portion of the semiconductor layer (15) in the ESD protection portion (32) and a different portion of the semiconductor layer (15) in the circuitry portion (34) are differentially thinned. A device (60) which implements the desired circuit functions of the SOI structure (20) is fabricated in the circuitry portion (34). An ESD protection device (40) is fabricated in the ESD protection portion (32). The thick semiconductor layer (15) in the ESD protection portion (32) serves to distribute the ESD current and heat over a large area, thereby improving the ability of the SOI structure (20) to withstand an ESD event.
摘要翻译： SOI结构（20）包括形成在绝缘基板（12）上的半导体层（15）。半导体层（15）被分隔成ESD保护部分（32）和电路部分（34）。 ESD保护部分（32）中的半导体层（15）的一部分和电路部分（34）中的半导体层（15）的不同部分被差异地变薄。在电路部分（34）中制造实现SOI结构（20）的所需电路功能的器件（60）。在ESD保护部分（32）中制造ESD保护装置（40）。 ESD保护部分（32）中的厚半导体层（15）用于在大面积上分布ESD电流和热量，从而提高SOI结构（20）承受ESD事件的能力。

5. 发明授权

US06991979B2 Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs 有权
公开(公告)号：US06991979B2
公开(公告)日：2006-01-31
申请号：US10605311
申请日：2003-09-22
申请人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
发明人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L21/8238
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.

6. 发明授权

US06362071B1 Method for forming a semiconductor device with an opening in a dielectric layer 有权
标题翻译：用于形成在电介质层中具有开口的半导体器件的方法
公开(公告)号：US06362071B1
公开(公告)日：2002-03-26
申请号：US09542706
申请日：2000-04-05
申请人： Bich-Yen Nguyen , William J. Taylor, Jr. , Philip J. Tobin , David L. O'Meara , Percy V. Gilbert , Yeong-Jyh T. Lii , Victor S. Wang
发明人： Bich-Yen Nguyen , William J. Taylor, Jr. , Philip J. Tobin , David L. O'Meara , Percy V. Gilbert , Yeong-Jyh T. Lii , Victor S. Wang
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/823481
摘要： In accordance with one embodiment of the present invention, a method is disclosed for forming a semiconductor device having an isolation region (601). A dielectric layer (108) is deposited and etched to form isolation regions (102, 605) having top portions that are narrower than their bottom portions, thereby a tapered isolation region is formed. Active regions (601, 603) are formed using an epitaxial process in the regions between the isolation regions. The resulting active regions (601, 603) have a greater amount of surface area near a top portion, than near a bottom portion. Transistors (721, 723) having opposite polarities are formed within the active areas.
摘要翻译：根据本发明的一个实施例，公开了一种用于形成具有隔离区域（601）的半导体器件的方法。沉积和蚀刻电介质层（108）以形成具有比其底部部分更窄的顶部部分的隔离区域（102,605），从而形成锥形隔离区域。在隔离区域之间的区域中使用外延工艺形成有源区（601,603）。所得活性区域（601,603）在顶部附近具有比在底部附近更大的表面积。在有源区域内形成具有相反极性的晶体管（721,723）。

7. 发明授权

US5885856A Integrated circuit having a dummy structure and method of making 失效
标题翻译：具有虚拟结构的集成电路及其制造方法
公开(公告)号：US5885856A
公开(公告)日：1999-03-23
申请号：US704481
申请日：1996-08-21
申请人： Percy V. Gilbert , Subramoney Iyer , Bradley P. Smith , Matthew A. Thompson , Kevin Kemp , Rajive Dhar
发明人： Percy V. Gilbert , Subramoney Iyer , Bradley P. Smith , Matthew A. Thompson , Kevin Kemp , Rajive Dhar
IPC分类号： H01L21/76 , H01L21/304 , H01L21/3105 , H01L21/762 , H01L21/768 , H01L21/70
CPC分类号： H01L21/31053 , H01L21/76229 , H01L21/76819
摘要： A pattern of dummy structures (20) is added to the layout pattern of an integrated circuit (10) to equilibrate the polishing rate across the surface of a semiconductor substrate (11). The location of each dummy structure (20) is predetermined so that it does not intersect a well boundary (17) or an active region (21,27), and does not fall under a conductive material such as a layer of polysilicon (22,28) or an interconnect structure (23,29).
摘要翻译：在集成电路（10）的布局图案中添加了虚拟结构（20）的图案，以平衡半导体衬底（11）的表面上的抛光速率。每个虚拟结构（20）的位置是预定的，使得其不与阱边界（17）或有源区（21,27）相交，并且不会落在导电材料（例如多晶硅层22） 28）或互连结构（23,29）。

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