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1. 发明授权

US06362071B1 Method for forming a semiconductor device with an opening in a dielectric layer 有权
标题翻译：用于形成在电介质层中具有开口的半导体器件的方法
公开(公告)号：US06362071B1
公开(公告)日：2002-03-26
申请号：US09542706
申请日：2000-04-05
申请人： Bich-Yen Nguyen , William J. Taylor, Jr. , Philip J. Tobin , David L. O'Meara , Percy V. Gilbert , Yeong-Jyh T. Lii , Victor S. Wang
发明人： Bich-Yen Nguyen , William J. Taylor, Jr. , Philip J. Tobin , David L. O'Meara , Percy V. Gilbert , Yeong-Jyh T. Lii , Victor S. Wang
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/823481
摘要： In accordance with one embodiment of the present invention, a method is disclosed for forming a semiconductor device having an isolation region (601). A dielectric layer (108) is deposited and etched to form isolation regions (102, 605) having top portions that are narrower than their bottom portions, thereby a tapered isolation region is formed. Active regions (601, 603) are formed using an epitaxial process in the regions between the isolation regions. The resulting active regions (601, 603) have a greater amount of surface area near a top portion, than near a bottom portion. Transistors (721, 723) having opposite polarities are formed within the active areas.
摘要翻译：根据本发明的一个实施例，公开了一种用于形成具有隔离区域（601）的半导体器件的方法。沉积和蚀刻电介质层（108）以形成具有比其底部部分更窄的顶部部分的隔离区域（102,605），从而形成锥形隔离区域。在隔离区域之间的区域中使用外延工艺形成有源区（601,603）。所得活性区域（601,603）在顶部附近具有比在底部附近更大的表面积。在有源区域内形成具有相反极性的晶体管（721,723）。

2. 发明授权

US06423632B1 Semiconductor device and a process for forming the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06423632B1
公开(公告)日：2002-07-23
申请号：US09621804
申请日：2000-07-21
申请人： Srikanth B. Samavedam , Philip J. Tobin , William J. Taylor, Jr.
发明人： Srikanth B. Samavedam , Philip J. Tobin , William J. Taylor, Jr.
IPC分类号： H01L2144
CPC分类号： H01L29/49 , H01L21/2807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a process for forming the device includes a conductor that overlies an insulating layer. In one embodiment, the conductor includes a first conductive portion, a second conductive portion, and a third conductive portion. The second conductive portion lies between the first and third conductive portions. The first conductive portion includes a first element, and the third conductive portion includes a metal and silicon without a significant amount of the first element. In another embodiment, the conductor is a gate electrode or a capacitor electrode. The conductor includes a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion. The second conductive portion lies between the first and third conductive portions and has a different composition compared to the first, third, and fourth conductive portion. The third conductive portion lies between the second and fourth conductive portions and has a different composition compared to the first and fourth conductive portions.
摘要翻译：半导体器件和用于形成器件的工艺包括覆盖在绝缘层上的导体。在一个实施例中，导体包括第一导电部分，第二导电部分和第三导电部分。第二导电部分位于第一和第三导电部分之间。第一导电部分包括第一元件，并且第三导电部分包括没有大量第一元件的金属和硅。在另一个实施例中，导体是栅电极或电容器电极。导体包括第一导电部分，第二导电部分，第三导电部分和第四导电部分。第二导电部分位于第一和第三导电部分之间，并且与第一，第三和第四导电部分相比具有不同的组成。第三导电部分位于第二和第四导电部分之间，并且与第一和第四导电部分相比具有不同的组成。

3. 发明授权

US07910442B2 Process for making a semiconductor device using partial etching 有权
标题翻译：使用局部蚀刻制造半导体器件的工艺
公开(公告)号：US07910442B2
公开(公告)日：2011-03-22
申请号：US11782319
申请日：2007-07-24
申请人： William J. Taylor, Jr. , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer
发明人： William J. Taylor, Jr. , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842 , H01L21/82345 , H01L21/84
摘要： A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device.
摘要翻译：提供了一种包括部分蚀刻第一层的第一部分的方法，其中第一层是导电层。该方法还包括去除第二层的至少一部分。该方法还包括完成导电层的所述第一部分的蚀刻，使得导电层的所述第一部分被去除。该方法还包括完成半导体器件的形成。

4. 发明授权

US07365410B2 Semiconductor structure having a metallic buffer layer and method for forming 有权
标题翻译：具有金属缓冲层的半导体结构和形成方法
公开(公告)号：US07365410B2
公开(公告)日：2008-04-29
申请号：US10977727
申请日：2004-10-29
申请人： Alexander A. Demkov , William J. Taylor, Jr.
发明人： Alexander A. Demkov , William J. Taylor, Jr.
IPC分类号： H01L29/12 , H01L29/16 , H01L29/161
CPC分类号： H01L21/823412 , H01L21/02381 , H01L21/02491 , H01L21/02532 , H01L21/02667 , H01L29/7833
摘要： A method for forming a semiconductor structure including providing a semiconductor substrate, forming a metallic buffer layer over the semiconductor substrate, forming an amorphous semiconductor layer over the metallic buffer layer, and recrystallizing the amorphous semiconductor layer to form a crystalline semiconductor layer. A semiconductor structure includes a semiconductor substrate, a buffer layer comprising at least one of silicide and germanide formed over the semiconductor substrate, and a crystalline semiconductor layer formed over the metallic buffer layer.
摘要翻译：一种用于形成半导体结构的方法，包括：提供半导体衬底，在所述半导体衬底上形成金属缓冲层，在所述金属缓冲层上形成非晶半导体层，以及使所述非晶半导体层再结晶以形成晶体半导体层。半导体结构包括半导体衬底，包括形成在半导体衬底上的硅化物和锗化物中的至少一种的缓冲层以及形成在金属缓冲层上的晶体半导体层。

5. 发明授权

US06849487B2 Method for forming an electronic structure using etch 失效
标题翻译：使用蚀刻形成电子结构的方法
公开(公告)号：US06849487B2
公开(公告)日：2005-02-01
申请号：US10445791
申请日：2003-05-27
申请人： William J. Taylor, Jr. , Olubunmi O. Adetutu , Steven G. H. Anderson
发明人： William J. Taylor, Jr. , Olubunmi O. Adetutu , Steven G. H. Anderson
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L29/51 , H01L29/786
CPC分类号： H01L29/785 , B82Y10/00 , H01L21/28035 , H01L21/28123 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28273 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66795 , Y10S438/947
摘要： A method of forming a conductive structure having a length that is less than the length define by photolithographic patterning. A silicon layer (12) is formed in a MeOx dielectric layer (11) is photolithographically patterned to a predetermined first length. A metal layer (31) is formed conformally to at least the sidewalls of the silicon layer and then is reacted with the silicon to form a metal silicide (41). In particular, metal silicide abutments (411,412) are formed contiguous to sidewalls (421,422) of a reduced conductor (42). The remaining metal layer and the metal silicide are etched away, resulting in a conductor having predetermined second length that is less than the predetermined first length.
摘要翻译：通过光刻图案形成具有小于长度的长度的导电结构的方法。在MeOx电介质层（11）中形成的硅层（12）被光刻地图案化到预定的第一长度。金属层（31）至少与硅层的侧壁共形形成，然后与硅反应形成金属硅化物（41）。特别地，与还原导体（42）的侧壁（421,422）邻接地形成金属硅化物接合部（411,412）。蚀刻剩余的金属层和金属硅化物，导致具有小于预定第一长度的预定第二长度的导体。

6. 发明授权

US06573160B2 Method of recrystallizing an amorphous region of a semiconductor 有权
标题翻译：重结晶半导体的非晶区域的方法
公开(公告)号：US06573160B2
公开(公告)日：2003-06-03
申请号：US09578404
申请日：2000-05-26
申请人： William J. Taylor, Jr. , Marius Orlowski , David C. Gilmer , Prasad V. Alluri , Christopher C. Hobbs , Michael J. Rendon , Iuval R. Clejan
发明人： William J. Taylor, Jr. , Marius Orlowski , David C. Gilmer , Prasad V. Alluri , Christopher C. Hobbs , Michael J. Rendon , Iuval R. Clejan
IPC分类号： H01L2120
CPC分类号： H01L21/02667 , H01L21/02381 , H01L21/2022 , H01L21/823807 , H01L21/823857 , H01L29/517 , H01L29/6659
摘要： Techniques for forming gate dielectric layers (702) overlying amorphous substrate materials are presented. In addition, techniques for low temperature processing operations that allow for the use of amorphous silicon in doping operations are presented. The amorphous silicon regions (604, 606) are formed prior to formation of structures included in the gate structure (804) of the semiconductor device, where the gate structures (804) are preferably formed using low temperature operations that allow the amorphous silicon regions (604, 606) to remain in an amorphous state. Source/drain regions (1004, 1006) are formed in the amorphous silicon regions (604, 606), and then the substrate is annealed to recrystallize the amorphous regions.
摘要翻译：提出了用于形成覆盖非晶衬底材料的栅介质层（702）的技术。此外，提出了允许在掺杂操作中使用非晶硅的低温处理操作的技术。在形成包括在半导体器件的栅极结构（804）中的结构之前形成非晶硅区域（604,606），其中栅极结构（804）优选地使用允许非晶硅区域（ 604,606）保持在非晶状态。源极/漏极区（1004,1006）形成在非晶硅区（604,606）中，然后将衬底退火以使非晶区重结晶。

7. 发明授权

US06475841B1 Transistor with shaped gate electrode and method therefor 失效
标题翻译：具有形状栅电极的晶体管及其方法
公开(公告)号：US06475841B1
公开(公告)日：2002-11-05
申请号：US09584963
申请日：2000-06-02
申请人： William J. Taylor, Jr. , Srikanth B. Samavedam , Nigel Cave
发明人： William J. Taylor, Jr. , Srikanth B. Samavedam , Nigel Cave
IPC分类号： H01L21311
CPC分类号： H01L29/4916 , H01L21/26586 , H01L21/28114 , H01L21/823437 , H01L21/823456 , H01L21/823828 , H01L21/823842 , H01L21/82385 , H01L29/42376
摘要： A transistor structure includes a retrograde gate structure (112) that is narrower at the end that interfaces with the gate dielectric (120) than it is at the opposite end and method for manufacture of such a structure. The retrograde gate structure (112) is formed by depositing a layer of gate material (104) that has varying composition in the vertical direction. The differentiation in composition causes varying lateral etch rate characteristics along the vertical direction of the gate structure (112) such that increased etching of the gate material (104) occurs near the interface with the gate dielectric layer (102).
摘要翻译：晶体管结构包括在与栅极电介质（120）接合的端部处比在相反端更窄的逆向栅极结构（112）和用于制造这种结构的方法。逆行栅极结构（112）通过在垂直方向上沉积具有不同组成的栅极材料层（104）而形成。组成的区别导致沿着栅极结构（112）的垂直方向的不同的横向蚀刻速率特性，使得栅极材料（104）的增加的蚀刻发生在与栅极介电层（102）的界面附近。

8. 发明授权

US4719700A Knife opening mechanism 失效
标题翻译：刀打开机制
公开(公告)号：US4719700A
公开(公告)日：1988-01-19
申请号：US878791
申请日：1986-06-26
申请人： William J. Taylor, Jr.
发明人： William J. Taylor, Jr.
IPC分类号： B26B1/04 , B26B3/06
CPC分类号： B26B1/048
摘要： A knife of the type having a casing and a blade pivotably mounted thereto has an actuator button slidably mounted to the casing. The blade has a concentric wheel associated therewith. One end of a non-extensible linkage is connected to the actuator, and the opposite end of the non-extensible linkage is wrapped around a portion of the wheel. When the user exerts a force to slide the actuator, the user-exerted force is transmitted by the non-extensible linkage to rotate the wheel, thereby pivoting the blade from its closed position to its open position.
摘要翻译：具有壳体的刀片和可枢转地安装在其上的刀片具有可滑动地安装到壳体的致动器按钮。刀片具有与其相关联的同心轮。不可延伸的连杆的一端连接到致动器，并且不可延伸的连杆的相对端缠绕在车轮的一部分上。当用户施加力以使致动器滑动时，用户施加的力由不可伸展的联动装置传递以旋转车轮，从而将刀片从其关闭位置枢转到其打开位置。

9. 发明授权

US07544595B2 Forming a semiconductor device having a metal electrode and structure thereof 有权
标题翻译：形成具有金属电极的半导体器件及其结构
公开(公告)号：US07544595B2
公开(公告)日：2009-06-09
申请号：US11619861
申请日：2007-01-04
申请人： William J. Taylor, Jr.
发明人： William J. Taylor, Jr.
IPC分类号： H01L21/3205
CPC分类号： H01L29/66545 , H01L21/28026 , H01L29/49 , H01L29/665 , H01L29/6659
摘要： A method for forming a semiconductor device includes forming a gate dielectric over a substrate, forming a metal electrode over the gate dielectric, forming a first sacrificial layer which includes polysilicon or a metal over the metal electrode, removing the first sacrificial layer, and forming a gate electrode contact over and coupled to the metal electrode.
摘要翻译：一种用于形成半导体器件的方法包括在衬底上形成栅极电介质，在栅极电介质上形成金属电极，在金属电极上形成包括多晶硅或金属的第一牺牲层，去除第一牺牲层，并形成栅电极接触并耦合到金属电极。

10. 发明授权

US06514808B1 Transistor having a high K dielectric and short gate length and method therefor 失效
标题翻译：具有高K电介质和短栅极长度的晶体管及其方法
公开(公告)号：US06514808B1
公开(公告)日：2003-02-04
申请号：US09997358
申请日：2001-11-30
申请人： Srikanth B. Samavedam , Christopher C. Hobbs , William J. Taylor, Jr.
发明人： Srikanth B. Samavedam , Christopher C. Hobbs , William J. Taylor, Jr.
IPC分类号： H01L21336
CPC分类号： H01L21/28176 , H01L21/28123 , H01L21/28194 , H01L21/31122 , H01L21/31604 , H01L21/31608 , H01L21/31616 , H01L21/31637 , H01L21/31645 , H01L21/32135 , H01L29/512 , H01L29/517
摘要： A transistor device (19) utilizes a high K dielectric (24) between a gate electrode (16) and a substrate (12). The high K dielectric (24) is etched under the gate electrode (16) so that there is an area between the gate electrode (16) and the substrate (12) that is void of high K dielectric (24). The source/drains extensions (28 and 30) are minimized to extend substantially in alignment with the edge of gate dielectric (24) to reduce overlap with the gate dielectric (24). This results in reduced capacitance between the gate and the source/drain extensions. The void areas (20 and 22) between the gate and the substrate (12) may remain void or may be filled with a low K dielectric, or at least a dielectric that is not high K.
摘要翻译：晶体管器件（19）利用栅电极（16）和衬底（12）之间的高K电介质（24）。在栅电极（16）下蚀刻高K电介质（24），使得在栅极电极（16）和基板（12）之间存在无K电介质（24）的区域。源极/漏极延伸部（28和30）被最小化以基本上与栅极电介质（24）的边缘对准以减小与栅极电介质（24）的重叠。这导致栅极和源极/漏极延伸部之间的电容降低。栅极和衬底（12）之间的空隙区域（20和22）可以保持空隙，或者可以填充低K电介质，或者至少是不高K的电介质。

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