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1. 发明申请

US20110027999A1 ETCH METHOD IN THE MANUFACTURE OF AN INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路制造中的ETCH方法
公开(公告)号：US20110027999A1
公开(公告)日：2011-02-03
申请号：US12377348
申请日：2006-08-16
申请人： Terry G. Sparks , Rauf Shahid
发明人： Terry G. Sparks , Rauf Shahid
IPC分类号： H01L21/465
CPC分类号： H01L21/3065 , C23F4/00 , H01L21/31116 , H01L21/32136
摘要： The present invention provides a method for etching a substrate in the manufacture of a semiconductor device, the method comprising contacting a surface of the substrate with ions extracted from a plasma formed from a gas comprising one or more of an oxygen-containing species, a nitrogen-containing species and an inert gas, and separately contacting the surface of the substrate with a plasma formed from a gas comprising a fluorine-containing species.
摘要翻译：本发明提供一种在半导体器件的制造中蚀刻衬底的方法，所述方法包括使衬底的表面与从包含一种或多种含氧物质，氮气的气体形成的等离子体提取的离子接触和惰性气体，并且分别使基板的表面与由包含含氟物质的气体形成的等离子体接触。

2. 发明申请

US20100227471A1 Pseudo Hybrid Structure for Low K Interconnect Integration 有权
标题翻译：用于低K互连集成的伪混合结构
公开(公告)号：US20100227471A1
公开(公告)日：2010-09-09
申请号：US12399372
申请日：2009-03-06
申请人： Pak K. Leung , Terry G. Sparks , David V. Horak , Steven M. Gates
发明人： Pak K. Leung , Terry G. Sparks , David V. Horak , Steven M. Gates
IPC分类号： H01L21/4763 , H01R43/00
CPC分类号： H01L21/76828 , H01L21/76808 , H01L21/76814 , H01L21/76825 , H01L21/76835 , H01L2221/1036 , Y10T29/49224
摘要： A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.
摘要翻译：描述了通过沉积和固化超低介电常数（ULK）材料的第一通孔层（43）来制造超低k互连结构的方法和装置，沉积相同ULK材料的第二未固化沟槽层（51）通过使用来自未固化沟槽层（51）和下面的固化通孔层（43）之间的化学差异的沟槽蚀刻终点信号的双镶嵌蚀刻工艺来选择性地蚀刻通孔开口（62）和沟槽开口（72）然后在通过用互连材料填充沟槽开口（72）和通孔开口（62）形成互连结构（91）之前固化第二沟槽层（83），使得不存在附加的界面或更高的介电常数材料留下。

3. 发明授权

US07544605B2 Method of making a contact on a backside of a die 有权
标题翻译：在模具的背面进行接触的方法
公开(公告)号：US07544605B2
公开(公告)日：2009-06-09
申请号：US11562161
申请日：2006-11-21
申请人： Terry G. Sparks , Shahid Rauf
发明人： Terry G. Sparks , Shahid Rauf
IPC分类号： H01L21/20
CPC分类号： H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05572 , H01L2224/13025 , H01L2224/13111 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： A method of forming a semiconductor device includes forming active circuitry over a semiconductor substrate, wherein the semiconductor substrate has a first major surface and a second major surface and the first active circuitry is formed over the first major surface of the semiconductor substrate. A via is formed within the first semiconductor substrate, wherein the via extends from the first active circuitry to the second major surface of the first semiconductor substrate. A dielectric layer is formed over the second major surface and adjacent the first via. The dielectric layer may include nitrogen and silicon and may be formed by a low pressure, low temperature, or both plasma process.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成有源电路，其中半导体衬底具有第一主表面和第二主表面，并且第一有源电路形成在半导体衬底的第一主表面上。通孔形成在第一半导体衬底内，其中通孔从第一有源电路延伸到第一半导体衬底的第二主表面。介电层形成在第二主表面上并与第一通孔相邻。电介质层可以包括氮和硅，并且可以通过低压，低温或两种等离子体工艺形成。

4. 发明授权

US06838354B2 Method for forming a passivation layer for air gap formation 有权
标题翻译：形成气隙形成钝化层的方法
公开(公告)号：US06838354B2
公开(公告)日：2005-01-04
申请号：US10327403
申请日：2002-12-20
申请人： Cindy K. Goldberg , Stanley Michael Filipiak , John C. Flake , Yeong-Jyh T. Lii , Bradley P. Smith , Yuri E. Solomentsev , Terry G. Sparks , Kirk J. Strozewski , Kathleen C. Yu
发明人： Cindy K. Goldberg , Stanley Michael Filipiak , John C. Flake , Yeong-Jyh T. Lii , Bradley P. Smith , Yuri E. Solomentsev , Terry G. Sparks , Kirk J. Strozewski , Kathleen C. Yu
IPC分类号： H01L21/288 , H01L21/768 , H01L21/76
CPC分类号： H01L21/76844 , H01L21/288 , H01L21/7682 , H01L21/76849 , H01L21/76874
摘要： Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.

5. 发明申请

US20090325106A1 Method for Implant Imaging with Spin-on Hard Masks 审中-公开
标题翻译：用旋转硬面膜进行种植体成像的方法
公开(公告)号：US20090325106A1
公开(公告)日：2009-12-31
申请号：US12147889
申请日：2008-06-27
申请人： Willard E. Conley , Terry G. Sparks , William J. Taylor, JR.
发明人： Willard E. Conley , Terry G. Sparks , William J. Taylor, JR.
IPC分类号： H01L21/02
CPC分类号： H01L21/0332 , H01L21/2652 , H01L29/78
摘要： A semiconductor fabrication method that includes forming a patterned mask (62, 72) by spin coating a developable hard mask layer (32) and a resist layer (42) over a semiconductor substrate (4). Subsequently, the resist layer (42) is exposed and developed to form a patterned resist layer (62), where the development step also removes the underlying hard mask layer (32), thereby forming a patterned mask (62, 72) which defines a void or printed feature to expose a region (97) over the semiconductor substrate which may be implanted, etched or otherwise processed.
摘要翻译：一种半导体制造方法，包括通过在半导体衬底（4）上旋涂可显影硬掩模层（32）和抗蚀剂层（42）来形成图案化掩模（62,72）。随后，曝光和显影抗蚀剂层（42）以形成图案化的抗蚀剂层（62），其中显影步骤还去除下面的硬掩模层（32），由此形成图案化掩模（62,72），其限定了空隙或印刷特征以暴露可以被植入，蚀刻或以其他方式处理的半导体衬底上的区域（97）。

6. 发明授权

US06245686B1 Process for forming a semiconductor device and a process for operating an apparatus 有权
标题翻译：用于形成半导体器件的工艺和用于操作器件的工艺
公开(公告)号：US06245686B1
公开(公告)日：2001-06-12
申请号：US09586828
申请日：2000-06-05
申请人： Jeffrey D. Rose , Michael J. Hartig , David G. Farber , Danny R. Babbitt , Jason A. Rivers , Ai Koh , Terry G. Sparks
发明人： Jeffrey D. Rose , Michael J. Hartig , David G. Farber , Danny R. Babbitt , Jason A. Rivers , Ai Koh , Terry G. Sparks
IPC分类号： H01L21302
CPC分类号： H01J37/321 , H01L21/31116
摘要： A process for forming a semiconductor device includes placing a substrate (104) into an apparatus (300), creating a plasma, and processing the substrate (104). The apparatus (300) includes an electromagnetic source (120), a bulk material (302), and a first barrier layer (304). The bulk material (302) is between the electromagnetic source (120) and an interior (126) of the apparatus (300). The first barrier layer (304) is between the bulk material (302) and the interior (126). A process for operating an apparatus (300) includes forming a polymer layer along an inorganic layer (302, 306or 702), wherein the polymer layer is formed within the apparatus (300); removing the polymer layer to expose the inorganic layer (302, 306, or 702); and etching at least a portion of the exposed inorganic layer (302, 306, or 702). Typically, the inorganic layer (203, 306, or 702) is semiconductive or resistive.
摘要翻译：一种用于形成半导体器件的工艺包括将衬底（104）放入设备（300）中，产生等离子体，以及处理衬底（104）。装置（300）包括电磁源（120），散装材料（302）和第一阻挡层（304）。散装材料（302）位于电磁源（120）和装置（300）的内部（126）之间。第一阻挡层（304）在散装材料（302）和内部（126）之间。用于操作设备（300）的方法包括沿着无机层（302,306或702）形成聚合物层，其中聚合物层形成在设备（300）内; 除去聚合物层以暴露无机层（302,306或702）; 并蚀刻所述暴露的无机层（302,306或702）的至少一部分。通常，无机层（203,306或702）是半导体或电阻的。

7. 发明授权

US07955968B2 Pseudo hybrid structure for low K interconnect integration 有权
标题翻译：用于低K互连集成的伪混合结构
公开(公告)号：US07955968B2
公开(公告)日：2011-06-07
申请号：US12399372
申请日：2009-03-06
申请人： Pak K. Leung , Terry G. Sparks , David V. Horak , Stephen M. Gates
发明人： Pak K. Leung , Terry G. Sparks , David V. Horak , Stephen M. Gates
IPC分类号： H01L21/4763
CPC分类号： H01L21/76828 , H01L21/76808 , H01L21/76814 , H01L21/76825 , H01L21/76835 , H01L2221/1036 , Y10T29/49224
摘要： A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.
摘要翻译：描述了通过沉积和固化超低介电常数（ULK）材料的第一通孔层（43）来制造超低k互连结构的方法和装置，沉积相同ULK材料的第二未固化沟槽层（51）通过使用来自未固化沟槽层（51）和下面的固化通孔层（43）之间的化学差异的沟槽蚀刻终点信号的双镶嵌蚀刻工艺来选择性地蚀刻通孔开口（62）和沟槽开口（72）然后在通过用互连材料填充沟槽开口（72）和通孔开口（62）形成互连结构（91）之前固化第二沟槽层（83），使得不存在附加的界面或更高的介电常数材料留下。

8. 发明申请

US20080119046A1 METHOD OF MAKING A CONTACT ON A BACKSIDE OF A DIE 有权
标题翻译：在DIE背面制作接触的方法
公开(公告)号：US20080119046A1
公开(公告)日：2008-05-22
申请号：US11562161
申请日：2006-11-21
申请人： Terry G. Sparks , Shahid Rauf
发明人： Terry G. Sparks , Shahid Rauf
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05572 , H01L2224/13025 , H01L2224/13111 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： A method of forming a semiconductor device includes forming active circuitry over a semiconductor substrate, wherein the semiconductor substrate has a first major surface and a second major surface and the first active circuitry is formed over the first major surface of the semiconductor substrate. A via is formed within the first semiconductor substrate, wherein the via extends from the first active circuitry to the second major surface of the first semiconductor substrate. A dielectric layer is formed over the second major surface and adjacent the first via. The dielectric layer may include nitrogen and silicon and may be formed by a low pressure, low temperature, or both plasma process.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成有源电路，其中半导体衬底具有第一主表面和第二主表面，并且第一有源电路形成在半导体衬底的第一主表面上。通孔形成在第一半导体衬底内，其中通孔从第一有源电路延伸到第一半导体衬底的第二主表面。介电层形成在第二主表面上并与第一通孔相邻。电介质层可以包括氮和硅，并且可以通过低压，低温或两种等离子体工艺形成。

9. 发明授权

US06924184B2 Semiconductor device and method for forming a semiconductor device using post gate stack planarization 有权
标题翻译：半导体器件和使用栅极堆叠平坦化形成半导体器件的方法
公开(公告)号：US06924184B2
公开(公告)日：2005-08-02
申请号：US10394352
申请日：2003-03-21
申请人： Nigel G. Cave , Anna M. Phillips , Terry G. Sparks
发明人： Nigel G. Cave , Anna M. Phillips , Terry G. Sparks
IPC分类号： H01L21/768 , H01L21/8238 , H01L23/48
CPC分类号： H01L21/76819 , H01L21/76802 , H01L21/76835
摘要： Via holes to the source/drains of a transistor are made to have very uniform depths so that photoresist thickness can be minimized to reduce the problems associated with small hole vias and vias that are at minimum pitches. This is achieved by polishing a dielectric over the gate stack to a polish stop present over the gate stack to result in having a top surface that is coplanar with the top surface of the polish stop layer over the gate stack. This establishes a top surface that is very uniform in height above the substrate across the wafer. A subsequent dielectric formed on this top surface is thus also very uniform in height over the wafer. The photoresist thickness then can be selected to the least thickness necessary based upon the expectation of maintaining a pattern for etching through a layer of very uniform thickness.
摘要翻译：通孔到晶体管的源极/漏极被制成具有非常均匀的深度，使得光致抗蚀剂厚度可以最小化，以减少与以最小间距的小孔通孔和通孔相关的问题。这是通过将栅极堆叠上的电介质抛光到存在于栅极堆叠上的抛光停止来实现的，以使得具有与栅极堆叠上的抛光停止层的顶表面共面的顶表面。这建立了在晶片上方的衬底上高度非常均匀的顶表面。因此，在该顶表面上形成的随后的电介质在晶片上的高度也是非常均匀的。基于期望保持用于蚀刻的图案通过非常均匀的厚度的层，光致抗蚀剂厚度然后可以被选择为所需的最小厚度。

10. 发明授权

US06884727B2 Semiconductor fabrication process for modifying the profiles of patterned features 有权
标题翻译：用于修改图案特征的轮廓的半导体制造工艺
公开(公告)号：US06884727B2
公开(公告)日：2005-04-26
申请号：US10224675
申请日：2002-08-21
申请人： Da Zhang , Terry G. Sparks
发明人： Da Zhang , Terry G. Sparks
IPC分类号： H01L21/027 , H01L21/033 , H01L21/3213 , H01L21/311
CPC分类号： H01L21/0337 , H01L21/0273 , H01L21/0338 , H01L21/32139
摘要： A method for forming a sacrificial layer (30) over patterned structures (28) to allow structures (28) to be trimmed laterally without incurring much loss vertically. Structures (28) are patterned on a first layer (26) of a substrate (24). Thereafter, sacrificial layer (30) is deposited on structures (28). During this deposition, the thickness of sacrificial layer (28) grows vertically above structures (28) faster than it grows laterally adjacent to the structures' sidewalls. Sacrificial layer (30) and patterned structures (28) are then etched where the etch rate uniformity ensures that the sacrificial layer (30) covering the sidewalls is cleared before the sacrificial layer covering the horizontal portions thereby enabling etching of the patterned structure sidewalls without reducing the patterned structure height. The sacrificial layer may comprise a polymer formed with a low energy fluorocarbon plasma while the subsequent etch may employ an oxygen plasma.
摘要翻译：一种用于在图案化结构（28）上形成牺牲层（30）的方法，以允许结构（28）被横向修剪，而不会垂直引起大量损失。在衬底（24）的第一层（26）上构图（28）。此后，牺牲层（30）沉积在结构（28）上。在该沉积期间，牺牲层（28）的厚度比在其结构侧壁附近生长更快地在结构（28）上方垂直地生长。然后蚀刻牺牲层（30）和图案化结构（28），其中蚀刻速率均匀性确保覆盖侧壁的牺牲层（30）在覆盖水平部分的牺牲层之前被清除，从而能够蚀刻图案化结构侧壁而不减少图案结构高度。牺牲层可以包括用低能量碳氟化合物等离子体形成的聚合物，而随后的蚀刻可以使用氧等离子体。

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