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1. 发明授权

US08061185B2 Method for testing a slurry used to form a semiconductor device 有权
标题翻译：用于测试用于形成半导体器件的浆料的方法
公开(公告)号：US08061185B2
公开(公告)日：2011-11-22
申请号：US12091693
申请日：2005-10-25
申请人： Philippe Monnoyer , Janos Farkas , Farid Sebaai
发明人： Philippe Monnoyer , Janos Farkas , Farid Sebaai
IPC分类号： G01N29/04 , G01N29/28
CPC分类号： C09G1/02 , G01N15/04 , G01N29/032 , G01N2291/02416
摘要： A method for forming a semiconductor device, the method includes providing a semiconductor substrate, applying a slurry to the semiconductor substrate, wherein the slurry was tested using a testing method includes taking a first undiluted sample from a top of the slurry; determining a first particle size distribution characteristic of the first undiluted sample; taking a second undiluted sample from a bottom of the slurry; determining a second particle size distribution characteristic of the second undiluted sample; and comparing a difference between the first particle size distribution characteristic and the second particle size distribution characteristics with a first predetermined value.
摘要翻译：一种形成半导体器件的方法，所述方法包括提供半导体衬底，向半导体衬底施加浆料，其中使用测试方法测试所述浆料，包括从所述浆料的顶部取出第一未稀释的样品; 确定第一未稀释样品的第一粒度分布特性; 从浆料的底部取出第二个未稀释的样品; 确定第二未稀释样品的第二粒度分布特征; 以及将第一粒度分布特性和第二粒度分布特性之间的差与第一预定值进行比较。

2. 发明授权

US07951729B2 Semiconductor device including a coupled dielectric layer and metal layer, method of fabrication thereor, and material for coupling a dielectric layer and a metal layer in a semiconductor device 有权
标题翻译：包括耦合电介质层和金属层的半导体器件，其制造方法以及用于在半导体器件中耦合电介质层和金属层的材料
公开(公告)号：US07951729B2
公开(公告)日：2011-05-31
申请号：US12705038
申请日：2010-02-12
申请人： Janos Farkas , Srdjan Kordic , Cindy Goldberg
发明人： Janos Farkas , Srdjan Kordic , Cindy Goldberg
IPC分类号： H01L21/31 , H01L23/58
CPC分类号： H01L21/3105 , C04B35/5603 , C04B35/565 , C04B2235/483 , C08G77/60 , C08L83/16 , C09D183/16 , H01L21/02063 , H01L21/02126 , H01L21/02164 , H01L21/02203 , H01L21/288 , H01L21/76801 , H01L21/7682 , H01L21/76838
摘要： A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device. In one example, the passivating coupling material has multiple Si atoms in its chemical composition, which desirably increases the thermal stability of the material.
摘要翻译：一种钝化耦合材料，一方面使半导体器件中的电介质层钝化，另一方面，用于在随后的工艺步骤中允许或至少促进液相金属沉积。在具体实例中，电介质层可以是具有理想的降低介电常数k的多孔材料，并且钝化耦合材料提供空间屏蔽基团，其基本上阻止环境水分吸附和吸收到多孔介电层中。与金属沉积相比，钝化耦合材料还提供金属成核侧，用于促进金属沉积在液相中，而不存在钝化偶联材料。使用液相金属沉积工艺有助于随后的半导体器件的制造。在一个实例中，钝化偶联材料在其化学组成中具有多个Si原子，这有利地增加了材料的热稳定性。

3. 发明申请

US20110021024A1 SURFACE TREATMENT IN SEMICONDUCTOR MANUFACTURING 有权
标题翻译：半导体制造中的表面处理
公开(公告)号：US20110021024A1
公开(公告)日：2011-01-27
申请号：US12934277
申请日：2008-04-11
申请人： Maria Luisa Calvo-Munoz , Janos Farkas
发明人： Maria Luisa Calvo-Munoz , Janos Farkas
IPC分类号： H01L21/44 , C23C16/00 , C23C16/52
CPC分类号： H01L21/02074 , H01L21/321 , H01L21/76877 , H01L21/76883
摘要： The present invention provides a process for forming a capping layer on a conducting interconnect for a semiconductor device, the process comprising: providing a substrate comprising one or more conductors in a dielectric layer, the conductors having an oxide layer at their surface; exposing the surface of the substrate to a vapour of β-diketone or a β-ketoimine; and depositing a capping layer on the surface of at least some of the one or more conductors. The present invention further provides an apparatus for carrying out this method.
摘要翻译：本发明提供了一种用于在半导体器件的导电互连上形成覆盖层的方法，该方法包括：提供包括在介电层中的一个或多个导体的基底，所述导体在其表面具有氧化物层; 将基材的表面暴露于二 - 二酮或α-酮亚胺的蒸气; 以及在所述一个或多个导体中的至少一些导体的表面上沉积覆盖层。本发明还提供一种用于执行该方法的装置。

4. 发明申请

US20100177641A1 Fault Localisation in Multiple Spanning Tree Based Architectures 有权
标题翻译：多个基于生成树的架构中的故障定位
公开(公告)号：US20100177641A1
公开(公告)日：2010-07-15
申请号：US12525713
申请日：2007-02-08
申请人： Janos Farkas , Wei Zhao
发明人： Janos Farkas , Wei Zhao
IPC分类号： H04L12/26
CPC分类号： H04L41/0677 , H04L45/48
摘要： A method of localising a fault in a network is disclosed. The network comprises nodes (SW1 . . . SW4) links, and edge-nodes (EN1 . . . EN4) arranged as a plurality of spanning trees (T1, T2,T3), the spanning trees being partially disjoint. The network further comprises means for network management. The method comprising the steps of receiving information on the configuration of the plurality of tree topologies in the network; monitoring connectivity in the network; upon detection of a loss of connectivity in the network, identifying the failed tree(s), and determining the network elements common to the failed tree(s).
摘要翻译：公开了一种在网络中定位故障的方法。网络包括布置为多个生成树（T1，T2，T3）的节点（SW1 ... SW4）链接和边缘节点（EN1 ... EN4），生成树是部分不相交的。网络还包括用于网络管理的装置。该方法包括以下步骤：接收关于网络中的多个树形拓扑结构的信息; 监控网络中的连通性; 在检测到网络中的连接丢失时，识别故障树，以及确定故障树共有的网络元件。

5. 发明授权

US07674725B2 Treatment solution and method of applying a passivating layer 有权
标题翻译：处理溶液和施加钝化层的方法
公开(公告)号：US07674725B2
公开(公告)日：2010-03-09
申请号：US11914878
申请日：2005-05-25
申请人： Janos Farkas , Sebastien Petitdidier
发明人： Janos Farkas , Sebastien Petitdidier
IPC分类号： H01L21/31
CPC分类号： H01L21/3212 , C11D11/0047 , H01L21/02052 , H01L21/67034 , Y10S438/906
摘要： A treatment solution for a semiconductor wafer comprising water, a passivating reagent and a surfactant. The treatment solution is either mixed with a cleaning fluid, a rinsing fluid or a drying vapor, and is used in a cleaning apparatus employing a Marangoni dryer.
摘要翻译：一种用于包含水，钝化剂和表面活性剂的半导体晶片的处理溶液。处理溶液与清洁液，漂洗液或干燥蒸气混合，并用于采用Marangoni干燥器的清洁装置中。

6. 发明申请

US20080287041A1 System and Method for Removing Particles From a Polishing Pad 有权
标题翻译：用于从抛光垫去除颗粒的系统和方法
公开(公告)号：US20080287041A1
公开(公告)日：2008-11-20
申请号：US12093113
申请日：2005-11-08
申请人： Srdjan Kordic , Sebastien Petitdidier , Janos Farkas , Silvio Del Monaco
发明人： Srdjan Kordic , Sebastien Petitdidier , Janos Farkas , Silvio Del Monaco
IPC分类号： B24B7/00
CPC分类号： B23H5/08 , B24B53/001 , B24B53/017 , C25F1/00
摘要： A system for removing particles from a polishing pad to improve the efficiency of the removal of material by the polishing pad as part of a chemical-mechanical polishing process, the system comprising a polishing pad; a fluid dispenser arranged to dispense a fluid on the polishing pad; and removal means, wherein the removal means include a heater for increasing the temperature of the fluid dispensed on the polishing pad, and/or voltage means for coupling the polishing pad to a voltage source for repelling charged particles from the polishing pad surface while the fluid dispenser is dispensing the fluid on the polishing pad.
摘要翻译：一种用于从抛光垫去除颗粒以提高抛光垫作为化学机械抛光工艺的一部分去除材料的效率的系统，该系统包括抛光垫; 流体分配器，布置成在抛光垫上分配流体; 和去除装置，其中所述去除装置包括用于增加分配在抛光垫上的流体的温度的加热器和/或用于将抛光垫耦合到电压源的电压装置，用于从抛光垫表面排斥带电粒子，同时流体分配器在抛光垫上分配流体。

7. 发明申请

US20080242110A1 Capping Layer Formation Onto a Dual Damescene Interconnect 有权
标题翻译：封盖层形成在双Damecene互连
公开(公告)号：US20080242110A1
公开(公告)日：2008-10-02
申请号：US12065190
申请日：2005-09-01
申请人： Janos Farkas , Lynne Michaelson , Srdjan Kordic
发明人： Janos Farkas , Lynne Michaelson , Srdjan Kordic
IPC分类号： H01L21/469
CPC分类号： H01L21/02074 , H01L21/288 , H01L21/3105 , H01L21/76801 , H01L21/76826 , H01L21/76849
摘要： A process for the formation of a capping layer on a conducting interconnect for a semiconductor device is provided, the process comprising the steps of: (a) providing one or more conductors in a dielectric layer, and (b) depositing a capping layer on an upper surface of at least some of the one or more conductors, characterised in that the process further includes: (c) the step of, prior to depositing the capping layer, reacting the dielectric layer with an organic compound in a liquid phase, the said organic compound having the following general formula: (I) where X is a functional group, R is an organic group or a organosiloxane group, Y1 is either a functional group or an organic group or organosiloxane group, and Y2 is either a functional group or an organic group or organosiloxane group, and where the functional group(s) is/are independently selected from the following: NH2, a secondary amine, a tertiary amine, acetamide, trifluoroacetamide, imidazole, urea, OH, an alkyoxy, acryloxy, acetate, SH, an alkylthiol, sulfonate, methanosulfonate, and cyanide, and salts thereof.
摘要翻译：提供了一种用于在半导体器件的导电互连上形成覆盖层的工艺，该方法包括以下步骤：（a）在电介质层中提供一个或多个导体，以及（b）将覆盖层沉积在所述一个或多个导体中的至少一些的上表面，其特征在于，所述方法还包括：（c）在沉积覆盖层之前使介电层与液相中的有机化合物反应的步骤，所述具有以下通式的有机化合物：（I）其中X是官能团，R是有机基团或有机硅氧烷基团，Y1是官能团或有机基团或有机硅氧烷基团，Y2是官能团或有机基团或有机硅氧烷基团，并且其中官能团独立地选自以下：NH 2，仲胺，叔胺，乙酰胺，三氟乙酰胺，咪唑，脲，OH，烷氧基，丙烯酸 xy，乙酸酯，SH，烷基硫醇，磺酸酯，甲磺酸酯和氰化物，及其盐。

8. 发明申请

US20080221004A1 Cleaning Solution for a Semiconductor Wafer 有权
标题翻译：半导体晶圆的清洁解决方案
公开(公告)号：US20080221004A1
公开(公告)日：2008-09-11
申请号：US11914870
申请日：2005-05-25
申请人： Janos Farkas
发明人： Janos Farkas
IPC分类号： C11D7/00
CPC分类号： H01L21/02052 , C11D1/722 , C11D3/044 , C11D3/3947 , C11D11/0023 , C11D11/0047
摘要： A cleaning solution for a semiconductor wafer comprises ammonia, hydrogen peroxide, a complexing agent and a block copolymer surfactant diluted in water. The cleaning solution can be used in single wafer cleaning tools to remove both particulate contaminants and metallic residues.
摘要翻译：用于半导体晶片的清洁溶液包括氨，过氧化氢，络合剂和在水中稀释的嵌段共聚物表面活性剂。清洁溶液可用于单晶圆清洁工具，以去除颗粒污染物和金属残留物。

9. 发明申请

US20080197487A1 Semiconductor Device Including a Coupled Dielectric Layer and Metal Layer, Method of Fabrication Thereof, and Material for Coupling a Dielectric Layer and a Metal Layer in a Semiconductor Device 有权
标题翻译：包括耦合电介质层和金属层的半导体器件，其制造方法以及用于耦合半导体器件中的介电层和金属层的材料
公开(公告)号：US20080197487A1
公开(公告)日：2008-08-21
申请号：US12065179
申请日：2006-09-01
申请人： Janos Farkas , Srdjan Kordic , Cindy Golberg
发明人： Janos Farkas , Srdjan Kordic , Cindy Golberg
IPC分类号： H01L23/52 , H01L21/768 , C08F230/08
CPC分类号： H01L21/3105 , C04B35/5603 , C04B35/565 , C04B2235/483 , C08G77/60 , C08L83/16 , C09D183/16 , H01L21/02063 , H01L21/02126 , H01L21/02164 , H01L21/02203 , H01L21/288 , H01L21/76801 , H01L21/7682 , H01L21/76838
摘要： A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device. In one example, the passivating coupling material has multiple Si atoms in its chemical composition, which desirably increases the thermal stability of the material.
摘要翻译：一种钝化耦合材料，一方面使半导体器件中的电介质层钝化，另一方面，用于在随后的工艺步骤中允许或至少促进液相金属沉积。在具体实例中，电介质层可以是具有理想的降低介电常数k的多孔材料，并且钝化耦合材料提供空间屏蔽基团，其基本上阻止环境水分吸附和吸收到多孔介电层中。与金属沉积相比，钝化耦合材料还提供金属成核侧，用于促进金属沉积在液相中，而不存在钝化偶联材料。使用液相金属沉积工艺有助于随后的半导体器件的制造。在一个实例中，钝化偶联材料在其化学组成中具有多个Si原子，这有利地增加了材料的热稳定性。

10. 发明申请

US20050035459A1 Semiconductor device having a multiple thickness interconnect 有权
标题翻译：具有多重厚度互连的半导体器件
公开(公告)号：US20050035459A1
公开(公告)日：2005-02-17
申请号：US10946675
申请日：2004-09-22
申请人： Kathleen Yu , Kirk Strozewski , Janos Farkas , Hector Sanchez , Yeong-Jyh Lii
发明人： Kathleen Yu , Kirk Strozewski , Janos Farkas , Hector Sanchez , Yeong-Jyh Lii
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/528 , H01L21/4763 , H01L21/44 , H01L29/40
CPC分类号： H01L23/5283 , H01L21/76807 , H01L21/76816 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.
摘要翻译：导线的厚度变化，有助于克服RC延迟和噪声耦合。通过改变线路厚度，如果需要在导体之间保持规定的最小间距，同时保持预定的期望的RC参数和导线的噪声特性，则避免导体宽度的变化。通过将介电层蚀刻成不同的厚度来实现导体深度变化。电介质层上的不同厚度的导电填充导致厚度变化的导线。在特定金属水平可用的不同的导线厚度可以另外用于除信号或电源导线之外的半导体结构，例如器件的触点，通孔或电极。为了满足期望的设计标准，确定互连厚度如何变化所需的厚度分析可以是自动化的并且作为CAD工具提供。

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