专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5522966A Dry etching process for semiconductor 失效
标题翻译：半导体干蚀刻工艺
公开(公告)号：US5522966A
公开(公告)日：1996-06-04
申请号：US152895
申请日：1993-11-17
申请人： Atsushi Komura , Yoshikazu Sakano , Kenji Kondo , Keiichi Kon , Tetsuhiko Sanbei , Shoji Miura
发明人： Atsushi Komura , Yoshikazu Sakano , Kenji Kondo , Keiichi Kon , Tetsuhiko Sanbei , Shoji Miura
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/00
CPC分类号： H01L21/3065 , Y10S438/906
摘要： A process for forming trenches on a surface of a semiconductor substrate by dry etching using a gas mixture. The gas mixture comprises; (1) an etchant gas comprising at least bromine which etches the semiconductor surface to form trenches, (2) a cleaning gas comprising a halogen which evaporates residue formed by the etching, and (3) a reactive gas, e.g. N.sub.2, capable of reacting with material formed during the etching and capable of controlling the inclination of the trenches.
摘要翻译：一种通过使用气体混合物的干蚀刻在半导体衬底的表面上形成沟槽的工艺。气体混合物包括：（1）至少包含溴的蚀刻剂气体，蚀刻半导体表面以形成沟槽，（2）包含卤素的清洁气体，其蒸发由蚀刻形成的残余物，和（3）反应性气体，例如， N2，能够与蚀刻期间形成的材料反应并且能够控制沟槽的倾斜度。

2. 发明授权

US5423941A Dry etching process for semiconductor 失效
标题翻译：半导体干蚀刻工艺
公开(公告)号：US5423941A
公开(公告)日：1995-06-13
申请号：US152896
申请日：1993-11-17
申请人： Atsushi Komura , Yoshikazu Sakano , Kenji Kondo , Keiichi Kon , Tetsuhiko Sanbei , Shoji Miura
发明人： Atsushi Komura , Yoshikazu Sakano , Kenji Kondo , Keiichi Kon , Tetsuhiko Sanbei , Shoji Miura
IPC分类号： H01L21/302 , H01L21/3065 , C23F1/00
CPC分类号： H01L21/3065
摘要： A process for forming deep trenches on a surface of a semiconductor substrate by forming a mask on the surface of the semiconductor, which prescribes the position of the trenches; and then dry etching the semiconductor surface using a gas mixture comprising (1) an etchant, bromine containing, gas which etches the semiconductor surface to form trenches, (2) a cleaning, halogen containing, gas which evaporates the residue formed by the etching; and (3) a reactive gas capable of reacting with material formed during the etching and capable of decreasing the wastage of the mask by the etchant gas.
摘要翻译：一种通过在半导体的表面上形成掩模来形成半导体衬底的表面上的深沟槽的方法，其规定了沟槽的位置; 然后使用气体混合物干燥蚀刻半导体表面，所述气体混合物包括（1）蚀刻剂，含溴的气体，蚀刻半导体表面以形成沟槽，（2）清洁，含卤素的气体，其蒸发由蚀刻形成的残余物; 和（3）能够与在蚀刻期间形成的材料反应的反应气体，并且能够通过蚀刻剂气体减少掩模的浪费。

3. 发明授权

US5480832A Method for fabrication of semiconductor device 失效
标题翻译：半导体器件制造方法
公开(公告)号：US5480832A
公开(公告)日：1996-01-02
申请号：US75514
申请日：1993-10-21
申请人： Shoji Miura , Takayuki Sugisaka , Atsushi Komura , Toshio Sakakibara
发明人： Shoji Miura , Takayuki Sugisaka , Atsushi Komura , Toshio Sakakibara
IPC分类号： H01L21/762 , H01L21/763 , H01L21/768 , H01L21/76
CPC分类号： H01L21/763 , H01L21/76264 , H01L21/76802 , H01L21/76275 , H01L21/76281 , H01L21/76286 , Y10S148/05 , Y10S148/135 , Y10S438/977
摘要： An object of the invention is to prevent the occurrence of breaking or short-circuiting of a wiring caused by a difference in level in an isolation trench area formed in an SOI substrate. An oxide film is formed for a pad on the main surface of an SOI layer formed on an insulating substrate, a silicon nitride film are formed and an SiO.sub.2 film in order, then an isolation trench reaching to the insulating substrate is by means of an R.I.E process using the SiO.sub.2 film as a mask. Thereafter an insulating film is formed on an inside wall of the isolation trench by means of thermal oxidation, the isolation trench is filled with polysilicon, the polysilicon is etched back while controlling the etching so that the top of the polysilicon in the isolation trench remains higher than the top of the silicon nitride film, an extra part of the polysilicon deposited on the surface of the substrate, is removed and then the SiO.sub.2 film used as a mask when forming the isolation trench is etched off using the polysilicon in the isolation trench and the silicon nitride film as an etching stopper. In this manner, since the SiO.sub.2 film used as a mask is etched off after filling the isolation trench with polysilicon, the oxide film for isolating between the substrates is not etched when removing the mask film. Moreover since the polysilicon is the isolation trench and the silicon nitride film act as an etching stopper when etching off the SiO.sub.2 film used as a mask, the oxide film for a pad existing thereunder and the insulating film formed on an inside wall of the trench can also be prevented from being etched and a flatness at an isolation trench area is not deteriorated.
摘要翻译： PCT No.PCT / JP92 / 01326 Sec。 371日期：1993年10月21日 102（e）日期1993年10月21日PCT提交1992年10月12日PCT公布。公开号WO93 / 08596 日期：1993年04月29日。本发明的目的在于防止在SOI衬底中形成的隔离沟槽区域中的电平差引起的布线断裂或短路。在绝缘基板上形成的SOI层的主表面上形成氧化膜，依次形成氮化硅膜和SiO 2膜，然后通过RIE到达绝缘基板的隔离沟槽使用SiO 2膜作为掩模。此后，通过热氧化在隔离沟槽的内壁上形成绝缘膜，隔离沟槽填充有多晶硅，在控制蚀刻的同时蚀刻多晶硅，使得隔离沟槽中的多晶硅的顶部保持较高除去氮化硅膜的顶部，去除沉积在衬底表面上的多晶硅的额外部分，然后使用隔离沟槽中的多晶硅蚀刻掉形成隔离沟槽时用作掩模的SiO 2膜，作为蚀刻停止层的氮化硅膜。以这种方式，由于在用多晶硅填充隔离沟槽之后蚀刻用作掩模的SiO 2膜，因此在去除掩模膜时不会蚀刻用于隔离的氧化膜。此外，由于多晶硅是隔离沟槽，并且氮化硅膜在蚀刻掉用作掩模的SiO 2膜时用作蚀刻阻挡层，所以存在于其上的垫的氧化膜和形成在沟槽的内壁上的绝缘膜也防止蚀刻，并且隔离沟槽区域的平坦度不会劣化。

4. 发明授权

US07468318B2 Method for manufacturing mold type semiconductor device 有权
标题翻译：模具型半导体器件的制造方法
公开(公告)号：US07468318B2
公开(公告)日：2008-12-23
申请号：US11702498
申请日：2007-02-06
申请人： Naohiko Hirano , Nobuyuki Kato , Takanori Teshima , Yoshitsugu Sakamoto , Shoji Miura , Akihiro Niimi
发明人： Naohiko Hirano , Nobuyuki Kato , Takanori Teshima , Yoshitsugu Sakamoto , Shoji Miura , Akihiro Niimi
IPC分类号： H01L21/4763
CPC分类号： H01L24/33 , H01L23/482 , H01L23/485 , H01L23/488 , H01L24/32 , H01L24/48 , H01L2224/05599 , H01L2224/291 , H01L2224/29111 , H01L2224/32245 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/85444 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/04941 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/3025 , H01L2924/351 , H01L2924/01014 , H01L2924/01028 , H01L2924/3512 , H01L2924/00 , H01L2924/014 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A method for manufacturing a mold type semiconductor device is provided. The device includes a semiconductor chip having a semiconductor part and a metallic member connecting to the chip via a conductive layer and a connecting member. The method includes: forming the semiconductor part on a semiconductor substrate so that a cell portion is provided; forming the conductive layer on the substrate; forming a first resist layer to cover a part of the conductive layer corresponding to the cell portion; etching the conductive layer with the first resist layer as a mask so that a first conductive layer is provided; removing the first resist layer and forming a second conductive layer to cover a surface and an edge of the first conductive layer. The second conductive layer has a Young's modulus equal to or larger than the semiconductor substrate.
摘要翻译：提供了一种用于制造模具型半导体器件的方法。该器件包括具有半导体部件和通过导电层和连接部件与芯片连接的金属部件的半导体芯片。该方法包括：在半导体衬底上形成半导体部分以便提供电池部分; 在所述基板上形成所述导电层; 形成第一抗蚀剂层以覆盖对应于所述电池单元部分的所述导电层的一部分; 用第一抗蚀剂层作为掩模蚀刻导电层，从而提供第一导电层; 去除第一抗蚀剂层并形成第二导电层以覆盖第一导电层的表面和边缘。第二导电层的杨氏模量等于或大于半导体衬底。

5. 发明授权

US07247929B2 Molded semiconductor device with heat conducting members 有权
标题翻译：具有导热构件的模制半导体器件
公开(公告)号：US07247929B2
公开(公告)日：2007-07-24
申请号：US10808567
申请日：2004-03-25
申请人： Shoji Miura , Yoshimi Nakase
发明人： Shoji Miura , Yoshimi Nakase
IPC分类号： H01L23/495
CPC分类号： H01L23/4334 , H01L24/48 , H01L25/072 , H01L2224/05553 , H01L2224/05599 , H01L2224/16 , H01L2224/45099 , H01L2224/48091 , H01L2224/73253 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/18301 , H01L2924/30107 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A power element package includes a semiconductor chip, radiating members, a mold resin member, a lead terminal for control signals, and lead terminals for large electric current. On a heat accepting surface of the radiating member, an insulating layer and a conductive layer are disposed. The lead terminal for control signals is electrically connected with a gate of the semiconductor chip through the conductive layer. An emitter of the semiconductor chip is electrically connected through a solder connection member with a non-insulating portion of the heat accepting surface.
摘要翻译：功率元件封装包括半导体芯片，散热构件，模制树脂构件，用于控制信号的引线端子和用于大电流的引线端子。在散热构件的受热表面上设置绝缘层和导电层。控制信号的引线端子通过导电层与半导体芯片的栅极电连接。半导体芯片的发射极通过焊接连接部件与受热面的非绝缘部分电连接。

6. 发明授权

US07109558B2 Power MOS transistor having capability for setting substrate potential independently of source potential 有权
公开(公告)号：US07109558B2
公开(公告)日：2006-09-19
申请号：US10160098
申请日：2002-06-04
申请人： Takashi Nakano , Satoshi Shiraki , Yutaka Fukuda , Nobumasa Ueda , Shoji Miura
发明人： Takashi Nakano , Satoshi Shiraki , Yutaka Fukuda , Nobumasa Ueda , Shoji Miura
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7811 , H01L23/4824 , H01L29/0696 , H01L29/0847 , H01L29/1087 , H01L29/1095 , H01L29/7802 , H01L29/7816 , H01L29/7835 , Y10S257/901
摘要： A power MOS transistor formed of an array of source cells and drain cells on an IC chip substrate has a plurality of substrate contact cells, each formed external to the source cells, having respective substrate potential-setting electrodes to which an externally supplied substrate bias voltage can be applied, enabling the substrate potential to be set independently of the source potential of the transistor. It thereby becomes possible to modify the threshold voltage of the transistor or maintain a constant potential difference between the substrate potential and that of a gate input signal. Since the requirement for a substrate contact region within each source cell is eliminated, and the number of substrate contact cells can be fewer than that of the source cells, the chip area occupied by the transistor can be reduced by comparison with a prior art configuration providing such a substrate potential control capability.

7. 发明授权

US06972459B2 Metal oxide semiconductor transistor having a nitrogen cluster containing layer embedded in the substrate 失效
标题翻译：金属氧化物半导体晶体管，其具有嵌入到基板中的含氮簇的层
公开(公告)号：US06972459B2
公开(公告)日：2005-12-06
申请号：US10164313
申请日：2002-06-07
申请人： Shoji Miura , Mikimasa Suzuki , Akira Kuroyanagi , Yoshitaka Nakano
发明人： Shoji Miura , Mikimasa Suzuki , Akira Kuroyanagi , Yoshitaka Nakano
IPC分类号： H01L21/336 , H01L29/06 , H01L29/32 , H01L29/78 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/32 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A drift layer is formed on a substrate. A base region is formed on the drift layer. A plurality of source regions are formed in a surficial layer of the base region. A plurality of gate electrodes face to the base region and the source region via a gate insulating film. A source electrode is brought into contact with the base region and the source region. A nitrogen cluster containing layer is embedded in the drift layer so as to extend laterally under the base region so that at least part of the drift region is left under the nitrogen cluster containing layer.
摘要翻译：在基板上形成漂移层。在漂移层上形成基极区域。多个源极区域形成在基极区域的表面层中。多个栅电极经由栅极绝缘膜与基极区域和源极区域面对。源电极与基极区域和源极区域接触。含氮簇层包含在漂移层中，以在基底区域横向延伸，使得漂移区的至少一部分留在含氮簇层的下方。

8. 发明授权

US06809348B1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06809348B1
公开(公告)日：2004-10-26
申请号：US09675209
申请日：2000-09-29
申请人： Mikimasa Suzuki , Akira Kuroyanagi , Takeshi Miyajima , Shoji Miura , Yutaka Tomatsu , Fuminari Suzuki
发明人： Mikimasa Suzuki , Akira Kuroyanagi , Takeshi Miyajima , Shoji Miura , Yutaka Tomatsu , Fuminari Suzuki
IPC分类号： H01L2974
CPC分类号： H01L29/0696 , H01L23/4334 , H01L24/06 , H01L24/48 , H01L24/49 , H01L27/0207 , H01L29/7397 , H01L29/7813 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/4813 , H01L2224/48247 , H01L2224/4846 , H01L2224/49113 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/0106 , H01L2924/01074 , H01L2924/014 , H01L2924/10162 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, several cell blocks provided on the semiconductor substrate, several gate electrodes electrically independent of one another and respectively provided in the cell blocks, and several gate pads respectively connected with the gate electrodes. In this construction, the cell blocks can be determined whether they are defective or not by utilizing the gate pads easily. Therefore, the semiconductor device can be operated only with non-defective cell blocks.
摘要翻译：半导体器件具有半导体衬底，设置在半导体衬底上的几个单元块，彼此电独立且分别设置在单元块中的几个栅极电极以及分别与栅电极连接的多个栅极焊盘。在这种结构中，可以容易地利用栅极焊盘来确定电池块是否有缺陷。因此，半导体器件可以仅用无缺陷单元块操作。

9. 发明授权

US5525831A Semiconductor device with thin film resistor having reduced film thickness sensitivity during trimming process 失效
标题翻译：具有薄膜电阻器的半导体器件在修整过程中具有降低的膜厚灵敏度
公开(公告)号：US5525831A
公开(公告)日：1996-06-11
申请号：US222815
申请日：1994-04-05
申请人： Makoto Ohkawa , Makio Iida , Shoji Miura , Osamu Ishihara , Tetsuaki Kamiya
发明人： Makoto Ohkawa , Makio Iida , Shoji Miura , Osamu Ishihara , Tetsuaki Kamiya
IPC分类号： H01C17/24 , H01L21/02 , H01L29/00 , H01L23/58 , H01L29/76
CPC分类号： H01L28/20 , H01C17/24
摘要： A thin film resistor on a semiconductor device may be laser trimmed while reducing the influence of film thickness of a passivation film formed on the thin film resistor. An underlying oxide film consisting of a BPSG film and a silicon oxide film is formed on an Si substrate. A silicon oxide film and a silicon nitride film are formed on the underlying film as a passivation film, and a silicon oxide film is formed on this assembly. The silicon oxide film contributes to controlling a variation of the laser energy absorption rate of a thin film resistor due to an uneven thickness of the silicon nitride film. Thus, it is possible to stabilize adjustment of the resistance value of the thin film resistor with a laser.
摘要翻译：半导体器件上的薄膜电阻器可以被激光修整，同时减少在薄膜电阻器上形成的钝化膜的膜厚度的影响。在Si衬底上形成由BPSG膜和氧化硅膜构成的底层氧化物膜。在作为钝化膜的基底膜上形成氧化硅膜和氮化硅膜，在该组件上形成氧化硅膜。氧化硅膜有助于控制由于氮化硅膜的不均匀厚度导致的薄膜电阻器的激光能量吸收率的变化。因此，可以通过激光来稳定薄膜电阻器的电阻值的调整。

10. 发明申请

US20070232108A1 WATER DISCHARGE DEVICE 有权
标题翻译：水排放装置
公开(公告)号：US20070232108A1
公开(公告)日：2007-10-04
申请号：US11691802
申请日：2007-03-27
申请人： Shoji Miura , Emiko Sumimoto
发明人： Shoji Miura , Emiko Sumimoto
IPC分类号： H01R13/62
CPC分类号： E03C1/042 , E03C1/0403 , Y10T137/698 , Y10T137/9464
摘要： Disclosed is a water discharge device (1) provided with a device body (2) and a connector (4) and adapted to be attached to a feedwater pipe (6). The water discharge device comprises fixing means (8) for fixing the device body to the connector at a given installation position. The connector has a feedwater-pipe-joining portion (4a) adapted to be joined to the feedwater pipe, and a connector-side engaging thread portion (4b), and the device body has a body-side engaging thread portion (14) positioned in such a manner as to be engaged with the connector-side engaging thread portion once during an operation of attaching the device body to the connector, and located beyond the connector-side engaging thread portion after the device body is fixed at the installation position. The water discharge device of the present invention can reliably prevent falling-off of the device body.
摘要翻译：公开了一种具有装置主体（2）和连接器（4）的排水装置（1），其适于附接到给水管（6）。排水装置包括用于在给定的安装位置将装置主体固定到连接器的固定装置（8）。连接器具有适于与给水管接合的给水管接合部分（4a）和连接器侧接合螺纹部分（4b），并且该装置主体具有主体侧接合螺纹部分（14）），在将装置本体连接到连接器的操作期间，以与连接器侧接合线部分接合的方式定位，并且在装置主体被固定在安装件之后位于连接器侧接合线部分之外位置。本发明的排水装置能够可靠地防止装置主体的脱落。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式