专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06835968B2 High frequency switch, two-band type high frequency switch, three-band type high frequency switch, and mobile communication equipment 有权
标题翻译：高频开关，双频段高频开关，三频段高频开关和移动通信设备
公开(公告)号：US06835968B2
公开(公告)日：2004-12-28
申请号：US10382011
申请日：2003-03-05
申请人： Shoichi Kitazawa , Masaharu Tanaka , Toshio Ishizaki , Toru Yamada
发明人： Shoichi Kitazawa , Masaharu Tanaka , Toshio Ishizaki , Toru Yamada
IPC分类号： H01L2974
CPC分类号： H01P1/15 , H01L2924/0002 , H01L2924/00
摘要： A high frequency switch, has a transmitting terminal; a receiving terminal; an antenna terminal; a first diode having an anode electrically connected to the transmitting terminal and a cathode electrically connected to the antenna terminal; a second diode having an anode connected through a transmission line of ¼ wavelength to the antenna terminal which is electrically connected to the receiving terminal, and having the side of a cathode grounded; and a control terminal provided to a node between the transmitting terminal and the first anode, wherein the first and second diodes have a tradeoff relationship between ON resistance thereof and capacitance between the anode and the cathode, and the ON resistance of the first diode is lower than the ON resistance of the second diode, and the capacitance of the second diode in the OFF state is smaller than the capacitance of the first diode in the OFF state.
摘要翻译：高频开关，发射端子，接收端子，天线端子，第一二极管，具有与发射端子电连接的阳极和与天线端子电连接的阴极;第二二极管，具有通过传输线连接的阳极对天线端子的1/4波长，电连接到接收端子，并且阴极侧接地; 以及提供给发送端子和第一阳极之间的节点的控制端子，其中第一和第二二极管在其导通电阻和阳极和阴极之间的电容之间具有折衷关系，并且第一二极管的导通电阻低于第二二极管的导通电阻和第二二极管在OFF状态下的电容小于第一二极管处于OFF状态的电容。

2. 发明授权

US06809348B1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06809348B1
公开(公告)日：2004-10-26
申请号：US09675209
申请日：2000-09-29
申请人： Mikimasa Suzuki , Akira Kuroyanagi , Takeshi Miyajima , Shoji Miura , Yutaka Tomatsu , Fuminari Suzuki
发明人： Mikimasa Suzuki , Akira Kuroyanagi , Takeshi Miyajima , Shoji Miura , Yutaka Tomatsu , Fuminari Suzuki
IPC分类号： H01L2974
CPC分类号： H01L29/0696 , H01L23/4334 , H01L24/06 , H01L24/48 , H01L24/49 , H01L27/0207 , H01L29/7397 , H01L29/7813 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/4813 , H01L2224/48247 , H01L2224/4846 , H01L2224/49113 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/0106 , H01L2924/01074 , H01L2924/014 , H01L2924/10162 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, several cell blocks provided on the semiconductor substrate, several gate electrodes electrically independent of one another and respectively provided in the cell blocks, and several gate pads respectively connected with the gate electrodes. In this construction, the cell blocks can be determined whether they are defective or not by utilizing the gate pads easily. Therefore, the semiconductor device can be operated only with non-defective cell blocks.
摘要翻译：半导体器件具有半导体衬底，设置在半导体衬底上的几个单元块，彼此电独立且分别设置在单元块中的几个栅极电极以及分别与栅电极连接的多个栅极焊盘。在这种结构中，可以容易地利用栅极焊盘来确定电池块是否有缺陷。因此，半导体器件可以仅用无缺陷单元块操作。

3. 发明授权

US06806510B2 Semiconductor device with surge protective component and method of manufacturing the semiconductor device 失效
标题翻译：具有浪涌保护元件的半导体器件和半导体器件的制造方法
公开(公告)号：US06806510B2
公开(公告)日：2004-10-19
申请号：US10014407
申请日：2001-12-14
申请人： Minoru Suzuki , Susumu Yoshida
发明人： Minoru Suzuki , Susumu Yoshida
IPC分类号： H01L2974
CPC分类号： H01L29/66121 , H01L29/87
摘要： In order to provide a reliable surge protective component with a straightforward manufacturing process, first and second buried layers are diffused over the entire inside surfaces of a semiconductor substrate, and first and second base layers are then diffused over the entire inside surfaces of the first and second buried layers. First and second emitter layers are then partially diffused at the inside of the first and second base layers. The peripheries of the first and second emitter layers are then surrounded by first and second moats, the bottoms of which reach the first and second buried layers. A PN junction formed between the first and second base layers and first and second buried layers is then simply a planar junction.
摘要翻译：为了提供具有直接制造工艺的可靠的浪涌保护部件，第一和第二掩埋层在半导体衬底的整个内表面上扩散，然后第一和第二基底层在第一和第二衬底的整个内表面上扩散第二埋层。然后，第一和第二发射极层在第一和第二基极层的内部部分地扩散。然后，第一和第二发射极层的周边被第一和第二护城河围绕，第一和第二护城河的底部到达第一和第二掩埋层。形成在第一和第二基底层与第一和第二掩埋层之间的PN结就是简单的平面结。

4. 发明授权

US06791122B2 Silicon controlled rectifier electrostatic discharge protection device with external on-chip triggering and compact internal dimensions for fast triggering 有权
标题翻译：具有外部片内触发的可控硅整流器静电放电保护器件，紧凑的内部尺寸可快速触发
公开(公告)号：US06791122B2
公开(公告)日：2004-09-14
申请号：US10007833
申请日：2001-11-05
申请人： Leslie R. Avery , Christian C. Russ , Koen G. M. Verhaege , Markus P. J. Mergens , John Armer
发明人： Leslie R. Avery , Christian C. Russ , Koen G. M. Verhaege , Markus P. J. Mergens , John Armer
IPC分类号： H01L2974
CPC分类号： H01L27/0262 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A silicon controlled rectifier electrostatic discharge protection circuit with external on-chip triggering and compact internal dimensions for fast triggering. The ESD protection circuit includes a silicon controlled rectifier (SCR) having an anode coupled to the protected circuitry and a cathode coupled to ground, where the cathode has at least one high-doped region. At least one trigger-tap is disposed proximate to the at least one high-doped region and an external on-chip triggering device is coupled to the trigger-tap and the protected circuitry.
摘要翻译：具有外部片上触发的可控硅整流器静电放电保护电路，紧凑的内部尺寸可快速触发。 ESD保护电路包括具有耦合到受保护电路的阳极和耦合到地的阴极的可控硅整流器（SCR），其中阴极具有至少一个高掺杂区域。在至少一个高掺杂区域附近设置至少一个触发器抽头，并且外部片上触发器件耦合到触发器抽头和受保护电路。

5. 发明授权

US06727529B2 Semiconductor capacitively-coupled NDR device and related applications in high-density high-speed memories and in power switches 失效
标题翻译：半导体电容耦合NDR器件及相关应用在高密度高速存储器和电源开关中
公开(公告)号：US06727529B2
公开(公告)日：2004-04-27
申请号：US10103241
申请日：2002-03-20
申请人： Farid Nemati , James D. Plummer
发明人： Farid Nemati , James D. Plummer
IPC分类号： H01L2974
CPC分类号： H01L29/74 , G11C11/39 , H01L27/0617 , H01L27/0688 , H01L27/1023 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/41716 , H01L29/42308 , H01L29/749 , H01L29/87
摘要： A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
摘要翻译：可以使用新颖的电容耦合NDR器件来实现各种半导体电路，包括高密度SRAM单元和功率晶闸管结构。在一个示例实施例中，NDR设备用作具有电容耦合门辅助关断和导通机制的薄垂直PNPN结构。基于这种新器件的SRAM在单元面积，待机电流，架构，速度和制造工艺方面相当于相同容量的DRAM。在一个实施例中，基于NDR的SRAM单元仅由两个元件组成，具有8F 2的占位面积，可以在高速和低电压下工作，具有良好的噪声容限，并且与主 - 流CMOS。与其他类型的基于NDR的SRAM相比，该单元显着降低了待机功耗。

6. 发明授权

US06724016B2 Fabricating a molecular electronic device having a protective barrier layer 有权
标题翻译：制造具有保护屏障层的分子电子器件
公开(公告)号：US06724016B2
公开(公告)日：2004-04-20
申请号：US10365946
申请日：2003-02-12
申请人： Yong Chen
发明人： Yong Chen
IPC分类号： H01L2974
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/02 , G11C2213/77 , H01L51/0595 , Y10S438/939 , Y10S438/951
摘要： A process of fabricating a molecular electronic device that preserves the integrity of the active molecular layer of the electronic device during processing is described. In one aspect, a barrier layer is provided to protect a molecular layer sandwiched between a bottom wire layer and a top wire layer from degradation during patterning of the top wire layer. A molecular electronic device structure and a memory system that are formed from this fabrication process are described.
摘要翻译：描述了在加工期间制造保持电子器件的有源分子层的完整性的分子电子器件的工艺。在一个方面，提供阻挡层以保护夹在底部线层和顶部线层之间的分子层在顶部线层的图案化期间不会劣化。描述了由该制造工艺形成的分子电子器件结构和存储器系统。

7. 发明授权

US06690037B1 Field plated Schottky diode 有权
标题翻译：场镀肖特基二极管
公开(公告)号：US06690037B1
公开(公告)日：2004-02-10
申请号：US09653616
申请日：2000-08-31
申请人： John Charles Desko , Michael J Evans , Chung-Ming Hsieh , Tzu-Yen Hsieh , Bailey R Jones , Thomas J. Krutsick , John Michael Siket, Jr. , Brian Eric Thompson , Steven W. Wallace
发明人： John Charles Desko , Michael J Evans , Chung-Ming Hsieh , Tzu-Yen Hsieh , Bailey R Jones , Thomas J. Krutsick , John Michael Siket, Jr. , Brian Eric Thompson , Steven W. Wallace
IPC分类号： H01L2974
CPC分类号： H01L29/402 , H01L29/872
摘要： A Schottky diode is fabricated by a sequence of fabrication by a sequence of fabrication steps. An active region of a semiconductor substrate is defined in which a Schottky diode is fabricated. At least first and second layers of insulating material are applied over the active area. A first layer of insulating material, having a first etching rate, is applied over the active area. A second layer of insulating material having a second, greater, etch rate is applied over the first layer of insulating material to a thickness that is about twice the thickness of the first layer of insulating material. The insulating material is patterned and a window is etched through the layers of insulating material to the semiconductor substrate. Metal is applied and unwanted metal is etched away leaving metal in the window forming a Schottky contact therein. One or more barrier layers may be employed.
摘要翻译：通过一系列制造步骤制造肖特基二极管。定义半导体衬底的有源区，其中制造肖特基二极管。至少第一和第二层绝缘材料施加在有效区域上。在有源区域上施加具有第一蚀刻速率的第一绝缘材料层。具有第二，更大蚀刻速率的第二层绝缘材料施加在绝缘材料的第一层上，其厚度约为第一绝缘材料层厚度的两倍。对绝缘材料进行图案化，并且通过绝缘材料层蚀刻窗口到半导体衬底。金属被施加并且不需要的金属被蚀刻掉，留下窗口中的金属在其中形成肖特基接触。可以采用一个或多个阻挡层。

8. 发明授权

US06680493B1 ESD protective transistor 失效
标题翻译： ESD保护晶体管
公开(公告)号：US06680493B1
公开(公告)日：2004-01-20
申请号：US09889336
申请日：2001-10-20
申请人： Heinrich Wolf , Wolfgang Wilkening , Stephan Mettler
发明人： Heinrich Wolf , Wolfgang Wilkening , Stephan Mettler
IPC分类号： H01L2974
CPC分类号： H01L27/0259
摘要： An ESD protective transistor comprises a heavily doped p-type base region which is arranged in a lightly doped p-well and which is provided with a first terminal. Furthermore, a heavily doped n-type emitter region is arranged in the lightly doped p-well. A heavily doped n-type collector region is separated from the lightly doped p-well through a lightly doped n-type region and is provided with a second terminal. The heavily doped n-type emitter region is not short-circuited with the heavily doped base region viy a common electrode and is of floating design. The doping types of the respective regions may be reversed.
摘要翻译： ESD保护晶体管包括重掺杂的p型基区，其布置在轻掺杂的p阱中并且设置有第一端。此外，重掺杂的n型发射极区域布置在轻掺杂的p阱中。通过轻掺杂的n型区域将重掺杂的n型集电极区域与轻掺杂的p阱分离，并且设置有第二端子。重掺杂的n型发射极区域不会与重掺杂的基极区域短路，并且具有浮动设计。各个区域的掺杂类型可以相反。

9. 发明授权

US06670649B2 Triodic rectifier switch 有权
公开(公告)号：US06670649B2
公开(公告)日：2003-12-30
申请号：US10012397
申请日：2001-12-12
申请人： Choong-Hoon Yi , Un-Chol Oh , Won-Pil Lee , Sun-Hee Yang , Gregory S. Um
发明人： Choong-Hoon Yi , Un-Chol Oh , Won-Pil Lee , Sun-Hee Yang , Gregory S. Um
IPC分类号： H01L2974
CPC分类号： H01L27/0676 , G02F1/1365 , G09G3/3208 , G09G3/367 , G09G2300/0417 , G09G2300/0895
摘要： The present invention discloses a triodic rectifier switch (TRS) having two diodes and one resistor. Each of the two diodes includes first and second electrodes, the first electrode made of a material having a work function of more than 4.5 eV (electron volts), the second electrode made of a material having a work function of less than 4.5 eV, and a semiconductor layer formed between the first and second electrode. The first electrode is made of a material selected from a group including indium tin oxide, Ni, Se, Pt, Os, Ir, Pd, Au, Cu, Ge, Be, Te, and Mo, and the second in electrode is made of a material selected from a group including K, Na, Ca, Li, Mg, In, Ta, Pb, Ag, Al, Zn, Sn, Fe, and Cr. The first and second electrodes may also have multiple layers.

10. 发明授权

US06653665B2 Memory device 失效
标题翻译：内存设备
公开(公告)号：US06653665B2
公开(公告)日：2003-11-25
申请号：US10073338
申请日：2002-02-13
申请人： Takeshi Kajiyama
发明人： Takeshi Kajiyama
IPC分类号： H01L2974
CPC分类号： H01L21/84 , H01L27/11 , H01L27/1203 , H01L29/7436
摘要： A semiconductor device according to an aspect of the present invention includes a substrate having a semiconductor substrate and a semiconductor layer provided on the semiconductor substrate, said semiconductor layer being insulated by an insulating film; a thyristor with a gate, its pnpn structure being laterally formed in said semiconductor layer of said substrate; and a transistor formed in said semiconductor layer of said substrate; said transistor being connected to one terminal of said thyristor. A method of manufacturing a semiconductor device according to other aspect of the present invention includes defining an element forming region isolated by an element isolation insulation film in a semiconductor layer of a first conductivity type provided on a semiconductor substrate, said semiconductor layer being insulated by an insulation film provided on the semiconductor substrate; forming a second base region of a first conductivity type in said element forming region; forming a first gate electrode of the thyristor and a second gate of the transistor above said second base region, said first and second gate electrodes being arranged in parallel; implanting ions to form a source and drain diffused regions of the second conductivity at both sides of said second gate electrode, and to form, at the same time, a second emitter region of the second conductivity type and a first base region, one of said source and drain diffused regions and said second emitter region being common region; providing a hole penetrating said first base region and said insulating film under said base region; and filling said hole with material of the first conductivity type to obtain a plug member as a first emitter region which contacts said semiconductor substrate.
摘要翻译：根据本发明的一个方面的半导体器件包括具有半导体衬底和设置在半导体衬底上的半导体层的衬底，所述半导体层被绝缘膜绝缘; 具有栅极的晶闸管，其pnpn结构横向形成在所述衬底的所述半导体层中; 以及形成在所述衬底的所述半导体层中的晶体管; 所述晶体管连接到所述晶闸管的一个端子。根据本发明的另一方面的制造半导体器件的方法包括限定由设置在半导体衬底上的第一导电类型的半导体层中的元件隔离绝缘膜隔离的元件形成区域，所述半导体层由设置在半导体基板上的绝缘膜; 在所述元件形成区域中形成第一导电类型的第二基区; 形成所述晶闸管的第一栅电极和位于所述第二基极区之上的所述晶体管的第二栅极，所述第一和第二栅极平行布置; 注入离子以在所述第二栅电极的两侧形成源极和漏极扩散区域，并且同时形成第二导电类型的第二发射极区域和第一基极区域，所述第一基极区域中的一个源极和漏极扩散区域和所述第二发射极区域是公共区域; 在所述基底区域提供穿透所述第一基底区域和所述绝缘膜的孔; 以及用所述第一导电类型的材料填充所述孔，以获得作为与所述半导体衬底接触的第一发射极区的插塞构件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式