专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07468318B2 Method for manufacturing mold type semiconductor device 有权
标题翻译：模具型半导体器件的制造方法
公开(公告)号：US07468318B2
公开(公告)日：2008-12-23
申请号：US11702498
申请日：2007-02-06
申请人： Naohiko Hirano , Nobuyuki Kato , Takanori Teshima , Yoshitsugu Sakamoto , Shoji Miura , Akihiro Niimi
发明人： Naohiko Hirano , Nobuyuki Kato , Takanori Teshima , Yoshitsugu Sakamoto , Shoji Miura , Akihiro Niimi
IPC分类号： H01L21/4763
CPC分类号： H01L24/33 , H01L23/482 , H01L23/485 , H01L23/488 , H01L24/32 , H01L24/48 , H01L2224/05599 , H01L2224/291 , H01L2224/29111 , H01L2224/32245 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/85444 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/04941 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/3025 , H01L2924/351 , H01L2924/01014 , H01L2924/01028 , H01L2924/3512 , H01L2924/00 , H01L2924/014 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A method for manufacturing a mold type semiconductor device is provided. The device includes a semiconductor chip having a semiconductor part and a metallic member connecting to the chip via a conductive layer and a connecting member. The method includes: forming the semiconductor part on a semiconductor substrate so that a cell portion is provided; forming the conductive layer on the substrate; forming a first resist layer to cover a part of the conductive layer corresponding to the cell portion; etching the conductive layer with the first resist layer as a mask so that a first conductive layer is provided; removing the first resist layer and forming a second conductive layer to cover a surface and an edge of the first conductive layer. The second conductive layer has a Young's modulus equal to or larger than the semiconductor substrate.
摘要翻译：提供了一种用于制造模具型半导体器件的方法。该器件包括具有半导体部件和通过导电层和连接部件与芯片连接的金属部件的半导体芯片。该方法包括：在半导体衬底上形成半导体部分以便提供电池部分; 在所述基板上形成所述导电层; 形成第一抗蚀剂层以覆盖对应于所述电池单元部分的所述导电层的一部分; 用第一抗蚀剂层作为掩模蚀刻导电层，从而提供第一导电层; 去除第一抗蚀剂层并形成第二导电层以覆盖第一导电层的表面和边缘。第二导电层的杨氏模量等于或大于半导体衬底。

2. 发明授权

US07247929B2 Molded semiconductor device with heat conducting members 有权
标题翻译：具有导热构件的模制半导体器件
公开(公告)号：US07247929B2
公开(公告)日：2007-07-24
申请号：US10808567
申请日：2004-03-25
申请人： Shoji Miura , Yoshimi Nakase
发明人： Shoji Miura , Yoshimi Nakase
IPC分类号： H01L23/495
CPC分类号： H01L23/4334 , H01L24/48 , H01L25/072 , H01L2224/05553 , H01L2224/05599 , H01L2224/16 , H01L2224/45099 , H01L2224/48091 , H01L2224/73253 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/18301 , H01L2924/30107 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A power element package includes a semiconductor chip, radiating members, a mold resin member, a lead terminal for control signals, and lead terminals for large electric current. On a heat accepting surface of the radiating member, an insulating layer and a conductive layer are disposed. The lead terminal for control signals is electrically connected with a gate of the semiconductor chip through the conductive layer. An emitter of the semiconductor chip is electrically connected through a solder connection member with a non-insulating portion of the heat accepting surface.
摘要翻译：功率元件封装包括半导体芯片，散热构件，模制树脂构件，用于控制信号的引线端子和用于大电流的引线端子。在散热构件的受热表面上设置绝缘层和导电层。控制信号的引线端子通过导电层与半导体芯片的栅极电连接。半导体芯片的发射极通过焊接连接部件与受热面的非绝缘部分电连接。

3. 发明授权

US07109558B2 Power MOS transistor having capability for setting substrate potential independently of source potential 有权
公开(公告)号：US07109558B2
公开(公告)日：2006-09-19
申请号：US10160098
申请日：2002-06-04
申请人： Takashi Nakano , Satoshi Shiraki , Yutaka Fukuda , Nobumasa Ueda , Shoji Miura
发明人： Takashi Nakano , Satoshi Shiraki , Yutaka Fukuda , Nobumasa Ueda , Shoji Miura
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7811 , H01L23/4824 , H01L29/0696 , H01L29/0847 , H01L29/1087 , H01L29/1095 , H01L29/7802 , H01L29/7816 , H01L29/7835 , Y10S257/901
摘要： A power MOS transistor formed of an array of source cells and drain cells on an IC chip substrate has a plurality of substrate contact cells, each formed external to the source cells, having respective substrate potential-setting electrodes to which an externally supplied substrate bias voltage can be applied, enabling the substrate potential to be set independently of the source potential of the transistor. It thereby becomes possible to modify the threshold voltage of the transistor or maintain a constant potential difference between the substrate potential and that of a gate input signal. Since the requirement for a substrate contact region within each source cell is eliminated, and the number of substrate contact cells can be fewer than that of the source cells, the chip area occupied by the transistor can be reduced by comparison with a prior art configuration providing such a substrate potential control capability.

4. 发明授权

US06972459B2 Metal oxide semiconductor transistor having a nitrogen cluster containing layer embedded in the substrate 失效
标题翻译：金属氧化物半导体晶体管，其具有嵌入到基板中的含氮簇的层
公开(公告)号：US06972459B2
公开(公告)日：2005-12-06
申请号：US10164313
申请日：2002-06-07
申请人： Shoji Miura , Mikimasa Suzuki , Akira Kuroyanagi , Yoshitaka Nakano
发明人： Shoji Miura , Mikimasa Suzuki , Akira Kuroyanagi , Yoshitaka Nakano
IPC分类号： H01L21/336 , H01L29/06 , H01L29/32 , H01L29/78 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/32 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A drift layer is formed on a substrate. A base region is formed on the drift layer. A plurality of source regions are formed in a surficial layer of the base region. A plurality of gate electrodes face to the base region and the source region via a gate insulating film. A source electrode is brought into contact with the base region and the source region. A nitrogen cluster containing layer is embedded in the drift layer so as to extend laterally under the base region so that at least part of the drift region is left under the nitrogen cluster containing layer.
摘要翻译：在基板上形成漂移层。在漂移层上形成基极区域。多个源极区域形成在基极区域的表面层中。多个栅电极经由栅极绝缘膜与基极区域和源极区域面对。源电极与基极区域和源极区域接触。含氮簇层包含在漂移层中，以在基底区域横向延伸，使得漂移区的至少一部分留在含氮簇层的下方。

5. 发明授权

US06809348B1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06809348B1
公开(公告)日：2004-10-26
申请号：US09675209
申请日：2000-09-29
申请人： Mikimasa Suzuki , Akira Kuroyanagi , Takeshi Miyajima , Shoji Miura , Yutaka Tomatsu , Fuminari Suzuki
发明人： Mikimasa Suzuki , Akira Kuroyanagi , Takeshi Miyajima , Shoji Miura , Yutaka Tomatsu , Fuminari Suzuki
IPC分类号： H01L2974
CPC分类号： H01L29/0696 , H01L23/4334 , H01L24/06 , H01L24/48 , H01L24/49 , H01L27/0207 , H01L29/7397 , H01L29/7813 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/4813 , H01L2224/48247 , H01L2224/4846 , H01L2224/49113 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/0106 , H01L2924/01074 , H01L2924/014 , H01L2924/10162 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, several cell blocks provided on the semiconductor substrate, several gate electrodes electrically independent of one another and respectively provided in the cell blocks, and several gate pads respectively connected with the gate electrodes. In this construction, the cell blocks can be determined whether they are defective or not by utilizing the gate pads easily. Therefore, the semiconductor device can be operated only with non-defective cell blocks.
摘要翻译：半导体器件具有半导体衬底，设置在半导体衬底上的几个单元块，彼此电独立且分别设置在单元块中的几个栅极电极以及分别与栅电极连接的多个栅极焊盘。在这种结构中，可以容易地利用栅极焊盘来确定电池块是否有缺陷。因此，半导体器件可以仅用无缺陷单元块操作。

6. 发明授权

US5525831A Semiconductor device with thin film resistor having reduced film thickness sensitivity during trimming process 失效
标题翻译：具有薄膜电阻器的半导体器件在修整过程中具有降低的膜厚灵敏度
公开(公告)号：US5525831A
公开(公告)日：1996-06-11
申请号：US222815
申请日：1994-04-05
申请人： Makoto Ohkawa , Makio Iida , Shoji Miura , Osamu Ishihara , Tetsuaki Kamiya
发明人： Makoto Ohkawa , Makio Iida , Shoji Miura , Osamu Ishihara , Tetsuaki Kamiya
IPC分类号： H01C17/24 , H01L21/02 , H01L29/00 , H01L23/58 , H01L29/76
CPC分类号： H01L28/20 , H01C17/24
摘要： A thin film resistor on a semiconductor device may be laser trimmed while reducing the influence of film thickness of a passivation film formed on the thin film resistor. An underlying oxide film consisting of a BPSG film and a silicon oxide film is formed on an Si substrate. A silicon oxide film and a silicon nitride film are formed on the underlying film as a passivation film, and a silicon oxide film is formed on this assembly. The silicon oxide film contributes to controlling a variation of the laser energy absorption rate of a thin film resistor due to an uneven thickness of the silicon nitride film. Thus, it is possible to stabilize adjustment of the resistance value of the thin film resistor with a laser.
摘要翻译：半导体器件上的薄膜电阻器可以被激光修整，同时减少在薄膜电阻器上形成的钝化膜的膜厚度的影响。在Si衬底上形成由BPSG膜和氧化硅膜构成的底层氧化物膜。在作为钝化膜的基底膜上形成氧化硅膜和氮化硅膜，在该组件上形成氧化硅膜。氧化硅膜有助于控制由于氮化硅膜的不均匀厚度导致的薄膜电阻器的激光能量吸收率的变化。因此，可以通过激光来稳定薄膜电阻器的电阻值的调整。

7. 发明授权

US07748649B2 Water discharging apparatus 有权
标题翻译：排水装置
公开(公告)号：US07748649B2
公开(公告)日：2010-07-06
申请号：US10503767
申请日：2003-02-06
申请人： Makoto Fujii , Shoji Miura , Yoshihiro Kiyofuji
发明人： Makoto Fujii , Shoji Miura , Yoshihiro Kiyofuji
IPC分类号： B05B1/14
CPC分类号： E03C1/066 , E03C1/0408 , E03C1/06 , E03C2201/30
摘要： It is an object to provide a novel water discharging apparatus capable of rapidly enhancing an outer appearance and a cleaning property and enjoying a plurality of water discharging configurations.In order to achieve the object, the water discharging apparatus comprises a hot and cold water mixing portion including a housing to which a cold water supply tube and a hot water supply tube are connected respectively, and a hot and cold water generating portion provided in the housing and serving to mix cold water and hot water which are supplied from the cold water supply tube and the hot water supply tube, thereby generating hot and cold water, and a water discharging portion coupled to the hot and cold water mixing portion and serving to discharge the generated hot and cold water from at least one water discharging nozzle, wherein the housing of the hot and cold water mixing portion is formed longitudinally in a vertical direction and the water discharging portion is coupled to an upper part and/or a lower part of the housing.
摘要翻译：本发明的目的是提供一种新颖的排水装置，其能够快速提高外观和清洁性能并享受多种排水结构。为了实现该目的，排水装置包括一个冷热水混合部分，该冷热水混合部分包括分别连接有冷水供给管和一个热水供应管的壳体，以及设置在该冷水产生部分中的冷热水产生部分将从冷水供给管和热水供给管供给的冷水和热水混合从而产生冷热水，以及与冷热水混合部连接的排水部，从至少一个排水喷嘴排出产生的冷热水，其中冷热水混合部分的壳体在垂直方向上纵向形成，并且排水部分联接到上部和/或下部的住房。

8. 发明授权

US07361996B2 Semiconductor device having tin-based solder layer and method for manufacturing the same 有权
标题翻译：具有锡基焊料层的半导体装置及其制造方法
公开(公告)号：US07361996B2
公开(公告)日：2008-04-22
申请号：US11220979
申请日：2005-09-08
申请人： Kimiharu Kayukawa , Akira Tanahashi , Chikage Noritake , Shoji Miura
发明人： Kimiharu Kayukawa , Akira Tanahashi , Chikage Noritake , Shoji Miura
IPC分类号： H01L23/52 , H01L23/40 , H01L23/48
CPC分类号： H01L24/29 , H01L23/4827 , H01L24/32 , H01L24/83 , H01L2224/04026 , H01L2224/29101 , H01L2224/29109 , H01L2224/29111 , H01L2224/32245 , H01L2224/83193 , H01L2224/83801 , H01L2224/8482 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/14 , H01L2924/157 , H01L2924/00 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01026 , H01L2924/00012 , H01L2224/37099
摘要： A semiconductor device includes: a semiconductor substrate; a base member; a tin-based solder layer; a first metal layer; and a first alloy layer. The semiconductor substrate is bonded to the base member through the first metal layer, the first alloy layer and the tin-based solder layer in this order. The first alloy layer is made of a first metal in the first metal layer and tin in the tin-based solder layer. The first metal layer is made of at least one of material selected from the group consisting of titanium, aluminum, iron, molybdenum, chromium, vanadium and iron-nickel-chromium alloy.
摘要翻译：半导体器件包括：半导体衬底; 基地会员锡基焊料层; 第一金属层; 和第一合金层。半导体基板通过第一金属层，第一合金层和锡基焊料层依次结合到基底构件。第一合金层由第一金属层中的第一金属和锡基焊料层中的锡制成。第一金属层由选自钛，铝，铁，钼，铬，钒和铁 - 镍 - 铬合金中的至少一种材料制成。

9. 发明授权

US06946711B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06946711B2
公开(公告)日：2005-09-20
申请号：US10164314
申请日：2002-06-07
申请人： Mikimasa Suzuki , Shoji Miura , Akira Kuroyanagi , Noriyuki Iwamori , Takashi Suzuki
发明人： Mikimasa Suzuki , Shoji Miura , Akira Kuroyanagi , Noriyuki Iwamori , Takashi Suzuki
IPC分类号： H01L21/02 , H01L21/18 , H01L21/265 , H01L21/322 , H01L21/336 , H01L27/12 , H01L29/78 , H01L29/786 , H01L29/76
CPC分类号： H01L29/7802 , H01L21/187 , H01L21/263 , H01L21/26506 , H01L21/26566 , H01L21/2658 , H01L21/3221 , H01L21/3226 , H01L29/66712 , H01L29/7805 , Y10S257/913
摘要： In a semiconductor device such as MOSFET, a single crystal semiconductor substrate is provided. An epitaxitial layer is formed on the single crystal semiconductor substrate. A p-well regions are formed on the epitaxitial layer, respectively, and n+ source regions are formed on the p-well regions, respectively. A gate electrode is formed through a gate insulation film on a part of each p-well region and that of each n+ source region. The gate electrode is covered with an insulation film. On the insulation film, a source electrode is formed so that the n-channel MOSFET includes body diodes BD imbedded therein. A drain electrode is formed on the single crystal semiconductor substrate. A cluster-containing layer is implanted in the single crystal semiconductor substrate as a gettering layer so that the cluster-containing layer contains a cluster of nitrogen.
摘要翻译：在诸如MOSFET的半导体器件中，提供单晶半导体衬底。在单晶半导体衬底上形成上覆层。分别在外延层上形成p阱区，并且在p阱区上分别形成n + +源区。在每个p阱区域和每个n +源极区域的一部分上通过栅极绝缘膜形成栅电极。栅电极被绝缘膜覆盖。在绝缘膜上形成源电极，使得n沟道MOSFET包括嵌入其中的体二极管BD。在单晶半导体基板上形成漏电极。将含有簇的层植入单晶半导体衬底中作为吸杂层，使得含簇层含有氮簇。

10. 发明授权

US06927167B2 Method for manufacturing semiconductor device having controlled surface roughness 失效
标题翻译：具有受控表面粗糙度的半导体器件的制造方法
公开(公告)号：US06927167B2
公开(公告)日：2005-08-09
申请号：US10732376
申请日：2003-12-11
申请人： Yutaka Fukuda , Naohiko Hirano , Chikage Noritake , Shoji Miura
发明人： Yutaka Fukuda , Naohiko Hirano , Chikage Noritake , Shoji Miura
IPC分类号： H01L21/28 , H01L21/304 , H01L21/306 , H01L21/331 , H01L21/336 , H01L23/433 , H01L23/495 , H01L29/34 , H01L29/41 , H01L29/78 , H01L21/302
CPC分类号： H01L24/33 , H01L21/304 , H01L21/30604 , H01L23/4334 , H01L23/49562 , H01L24/32 , H01L24/48 , H01L29/34 , H01L29/66333 , H01L2224/05599 , H01L2224/32014 , H01L2224/32245 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/73215 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01051 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/181 , H01L2924/18301 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A method for manufacturing a semiconductor device with a substrate having a device layer and a backside electrode is disclosed. Here, a surface roughness of the substrate is defined as a ratio between a substantial area and a projected area. The method includes polishing and wet-etching a backside surface of the substrate mechanically with using predetermined abrasive grains so that a surface roughness of the backside surface of the substrate becomes to be equal to or larger than 1.04, and forming the backside electrode on the backside surface of the substrate after polishing and wet-etching the backside surface of the substrate.
摘要翻译：公开了一种具有具有器件层和背面电极的衬底的半导体器件的制造方法。这里，基板的表面粗糙度被定义为实质面积和投影面积之间的比率。该方法包括使用预定的磨粒机械地抛光和湿法蚀刻衬底的背面，使得衬底的背面的表面粗糙度等于或大于1.04，并且在背面形成背面电极抛光后的基板的表面和湿法蚀刻基板的背面。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式