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1. 发明授权

US6104076A Semiconductor device and manufacturing method thereof 失效
公开(公告)号：US6104076A
公开(公告)日：2000-08-15
申请号：US748896
申请日：1996-11-15
申请人： Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
发明人： Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
IPC分类号： H01L21/336 , H01L21/8249 , H01L27/02 , H01L27/06 , H01L27/085 , H01L29/739 , H01L29/78 , H01L29/76 , H01L23/58
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0251 , H01L27/0623 , H01L27/085 , H01L29/063 , H01L29/1083 , H01L29/1095 , H01L29/66674 , H01L29/7395 , H01L29/7801 , H01L29/7824 , H01L29/7835
摘要： A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.

2. 发明授权

US06242792B1 Semiconductor device having oblique portion as reflection 有权
标题翻译：具有倾斜部分作为反射的半导体器件
公开(公告)号：US06242792B1
公开(公告)日：2001-06-05
申请号：US09315132
申请日：1999-05-20
申请人： Shoji Miura , Satoshi Shiraki , Tetsuaki Kamiya , Makio Iida
发明人： Shoji Miura , Satoshi Shiraki , Tetsuaki Kamiya , Makio Iida
IPC分类号： H01L2941
CPC分类号： H01L28/20 , H01L22/22 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A laser trimming is favorably performed by a strengthened laser beam energy. A level difference portion having a taper portion that is oblique with respect to the thicknesswise direction of a semiconductor substrate is formed at a surface of a semiconductor substrate. An insulating film is formed thereon and has its surface made flat, and then the thin film element is formed thereon. Thereafter, laser trimming is performed with respect to the thin film resistor. As a result, a state of interference between incident laser beam and reflected laser beam reflected from the interface between the semiconductor substrate and the insulating film is varied to thereby enable the production of a zone where laser beam energy is strengthened and a zone where laser beam energy is weakened.
摘要翻译：通过强化的激光束能量有利地进行激光修整。在半导体基板的表面形成有具有相对于半导体基板的厚度方向倾斜的锥形部的电平差部。在其上形成绝缘膜并使其表面平坦化，然后在其上形成薄膜元件。此后，相对于薄膜电阻器进行激光微调。结果，入射激光束与从半导体衬底和绝缘膜之间的界面反射的反射激光束之间的干涉状态变化，从而能够生成激光束能量增强的区域和激光束能量减弱。

3. 发明授权

US5625218A Semiconductor device equipped with a heat-fusible thin film resistor and production method thereof 失效
标题翻译：配有热熔薄膜电阻的半导体装置及其制造方法
公开(公告)号：US5625218A
公开(公告)日：1997-04-29
申请号：US491543
申请日：1995-06-16
申请人： Hideya Yamadera , Takeshi Ohwaki , Yasunori Taga , Makio Iida , Makoto Ohkawa , Hirofumi Abe , Yoshihiko Isobe
发明人： Hideya Yamadera , Takeshi Ohwaki , Yasunori Taga , Makio Iida , Makoto Ohkawa , Hirofumi Abe , Yoshihiko Isobe
IPC分类号： H01L23/525 , H01L27/10 , H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002
摘要： A fuse fusible type semiconductor device capable of reducing energy required for fusing and a production method of the semiconductor device. In a semiconductor device equipped with a heat-fusible thin film resistor, the thin film resistor formed on a substrate 1 through an insulating film 2 is made of chromium, silicon and tungsten, and films 7 and 8 of a insulator including silicon laminated on the upper surface of the fusing surface, aluminum films 5 are disposed on both sides of the fusing surface and a barrier film 4. This semiconductor device is produced by a lamination step of sequentially forming a first insulating film 2, a thin film resistor 3, a barrier film 4 and an aluminum film 5 on a substrate 1 for reducing drastically fusing energy, an etching step of removing the barrier film 4 and the aluminum film 5 from the fusing region 31 of the thin film resistor 3, and an oxide film formation step of depositing the insulator including silicon films 7 and 8.
摘要翻译：一种能够降低熔融所需的能量的熔断器熔断型半导体器件和半导体器件的制造方法。在配备有热熔薄膜电阻器的半导体装置中，通过绝缘膜2形成在基板1上的薄膜电阻由铬，硅和钨制成，并且包含硅的绝缘体的膜7和8层压在定影表面的上表面，铝膜5设置在定影表面的两侧和阻挡膜4上。该半导体器件通过层叠步骤制造，顺序形成第一绝缘膜2，薄膜电阻3，阻挡膜4和铝膜5，用于降低显着熔化能的蚀刻步骤，从薄膜电阻器3的熔融区域31去除阻挡膜4和铝膜5的蚀刻步骤以及氧化膜形成步骤沉积包括硅膜7和8的绝缘体。

4. 发明授权

US5187559A Semiconductor device and process for producing same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5187559A
公开(公告)日：1993-02-16
申请号：US661240
申请日：1991-02-27
申请人： Yoshihiko Isobe , Makio Iida
发明人： Yoshihiko Isobe , Makio Iida
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L27/06
CPC分类号： H01L28/20 , H01L27/0688
摘要： A semiconductor device provided with a polycrystalline silicon resistor containing an impurity in a high concentration and having a resistance adjusted by a current conduction therethrough at a current density of a threshold value or more, which comprises: a polycrystalline silicon resistor containing a first impurity having a negative value of a temperature coefficient of resistance in a high impurity concentration region of said polycrystalline silicon resistor and a second impurity having a positive value of a temperature coefficient of resistance in a high impurity concentration region of the polycrystalline silicon resistor. A process for producing same is also disclosed.
摘要翻译：一种半导体器件，其具有含有高浓度的杂质的多晶硅电阻体，所述多晶硅电阻器具有以阈值以上的电流密度通过电流导通而调整的电阻，所述电流密度包括：含有第一杂质的多晶硅电阻，在多晶硅电阻器的高杂质浓度区域中，所述多晶硅电阻器的高杂质浓度区域的电阻温度系数的负值和具有温度系数的正值的第二杂质。还公开了其制造方法。

5. 发明授权

US06831331B2 Power MOS transistor for absorbing surge current 失效
标题翻译：功率MOS晶体管，用于吸收浪涌电流
公开(公告)号：US06831331B2
公开(公告)日：2004-12-14
申请号：US09945621
申请日：2001-09-05
申请人： Yasuhiro Kitamura , Toshio Sakakibara , Kenji Kohno , Shoji Mizuno , Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
发明人： Yasuhiro Kitamura , Toshio Sakakibara , Kenji Kohno , Shoji Mizuno , Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
IPC分类号： H01L2976
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0251 , H01L27/0623 , H01L27/085 , H01L29/1087 , H01L29/66674 , H01L29/7395 , H01L29/7801 , H01L29/7824 , H01L29/7835
摘要： A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.
摘要翻译：提供具有功率晶体管结构的半导体器件。功率晶体管结构包括独立地设置在半导体层的表面部分处的多个第一阱; 深部区域，其具有设置在所述第一阱之间的所述半导体层中的部分; 漏电极，连接到所述第一阱中的相应的漏极区; 源电极，其连接到第一阱中的各个源极区域和沟道阱区域，使得漏极电极或源极电极连接到感性负载; 以及连接构件，用于向深区域提供源极电位，其中当漏电极连接到感性负载时，连接构件可配置为连接到漏电极，并且当源电极连接到源电极时连接到源电极表示感性负载。

6. 发明授权

US06287933B1 Semiconductor device having thin film resistor and method of producing same 失效
标题翻译：具有薄膜电阻器的半导体器件及其制造方法
公开(公告)号：US06287933B1
公开(公告)日：2001-09-11
申请号：US08015268
申请日：1992-01-03
申请人： Makio Iida , Shoji Miura , Kanemitsu Terada , Hiroyuki Ban , Kiyoshi Yamamoto , Katsuyoshi Oda , Yoshihiko Isobe
发明人： Makio Iida , Shoji Miura , Kanemitsu Terada , Hiroyuki Ban , Kiyoshi Yamamoto , Katsuyoshi Oda , Yoshihiko Isobe
IPC分类号： H01L2120
CPC分类号： H01L28/24
摘要： A semiconductor device having a thin film resistor which comprises at least chromium, silicon and nitrogen, and formed on a substrate with having a special ratio of the chemical composition, the semiconductor device having a characteristic such that variations of the resistance value thereof due to temperature variations can be effectively suppressed.
摘要翻译：一种具有薄膜电阻器的半导体器件，该薄膜电阻器至少包含铬，硅和氮，并且形成在具有特定比例的化学成分的基板上，该半导体器件具有使其由于温度导致的电阻值的变化的特性可以有效地抑制变化。

7. 发明授权

US6104078A Design for a semiconductor device having elements isolated by insulating regions 失效
标题翻译：设计具有通过绝缘区隔离的元件的半导体器件
公开(公告)号：US6104078A
公开(公告)日：2000-08-15
申请号：US941756
申请日：1997-09-30
申请人： Makio Iida , Mitsuhiro Saitou , Akitaka Murata , Hiroyuki Ban , Tadashi Suzuki , Toshio Sakakibara , Takayuki Sugisaka , Shoji Miura
发明人： Makio Iida , Mitsuhiro Saitou , Akitaka Murata , Hiroyuki Ban , Tadashi Suzuki , Toshio Sakakibara , Takayuki Sugisaka , Shoji Miura
IPC分类号： H01L21/762 , H01L29/36
CPC分类号： H01L21/76264
摘要： A semiconductor device including a semiconductor substrate having a main surface. An insulating film is formed on the main surface of the semiconductor substrate. A semiconductor layer is placed on the insulating film. Side insulating regions extending from a surface of the semiconductor layer to the insulating film divide the semiconductor layer into element regions. The element regions are isolated from each other by the side insulating regions and the insulating film. The semiconductor substrate has a resistivity of 1.5 .OMEGA.cm or lower. A voltage at the semiconductor substrate is set to a given voltage.
摘要翻译：一种半导体器件，包括具有主表面的半导体衬底。绝缘膜形成在半导体衬底的主表面上。半导体层被放置在绝缘膜上。从半导体层的表面延伸到绝缘膜的侧绝缘区域将半导体层分成元件区域。元件区域通过侧绝缘区域和绝缘膜彼此隔离。半导体基板的电阻率为1.5欧姆·厘米或更低。将半导体衬底处的电压设定为给定电压。

8. 发明授权

US5989970A Method for fabricating semiconductor device having thin-film resistor 失效
标题翻译：制造具有薄膜电阻器的半导体器件的方法
公开(公告)号：US5989970A
公开(公告)日：1999-11-23
申请号：US774796
申请日：1996-12-30
申请人： Makoto Ohkawa , Makio Iida , Mikimasa Suzuki
发明人： Makoto Ohkawa , Makio Iida , Mikimasa Suzuki
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/70
CPC分类号： H01L28/24
摘要： Even when a contact hole is formed before thin-film resistor formation, a contact area exposed in the contact hole is prevented from damaging. A semiconductor element is formed in a silicon semiconductor substrate and an oxide film is formed on the surface of the semiconductor substrate. Then, a contact hole is formed on the oxide film and moreover, a CrSiN film serving as a thin-film resistor and a TiW film serving as a barrier metal are formed on the oxide film. The TiW film is patterned by a mask and the CrSiN film is patterned through chemical dry etching. Finally, an Al electrode is formed on the semiconductor element and the CrSiN film through the contact hole and moreover a protective film is formed thereon.
摘要翻译：即使在形成薄膜电阻器之前形成接触孔，也可以防止在接触孔中暴露的接触区域的损伤。半导体元件形成在硅半导体衬底中，并且在半导体衬底的表面上形成氧化物膜。然后，在氧化膜上形成接触孔，此外，在氧化膜上形成用作薄膜电阻器的CrSiN膜和用作阻挡金属的TiW膜。通过掩模对TiW膜进行构图，并通过化学干蚀刻对CrSiN膜进行图案化。最后，通过接触孔在半导体元件和CrSiN膜上形成Al电极，并且在其上形成保护膜。

9. 发明授权

US5747846A Programmable non-volatile memory cell 失效
标题翻译：可编程非易失性存储单元
公开(公告)号：US5747846A
公开(公告)日：1998-05-05
申请号：US346287
申请日：1994-11-23
申请人： Makio Iida , Tetsuo Fujii , Yoshihiko Isobe
发明人： Makio Iida , Tetsuo Fujii , Yoshihiko Isobe
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L27/10
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11531
摘要： A non-volatile memory cell having a structure having improved integration and simplified electrode wiring structure. The programmable non-volatile memory cell of the present invention adopts a mono-layer gate scheme to simplify the electrode wiring structure and to eliminate a current leakage problem of an insulating film between electrodes. A side and bottom of a semiconductor region, which is disposed directly below a capacity electrode section with a gate insulating film interposed therebetween that compose a control electrode, are isolated from another semiconductor region and semiconductor substrate by insulating films. Thus, a high programming control voltage which is not limited by a junction yield voltage between the semiconductor regions and semiconductor substrate may be applied. Due to that, an area of the capacity electrode section of a floating electrode may be considerably reduced.
摘要翻译：具有改进的集成和简化的电极布线结构的结构的非易失性存储单元。本发明的可编程非易失性存储单元采用单层栅极方案来简化电极布线结构，并消除电极之间绝缘膜的漏电问题。通过绝缘膜将另一个半导体区域的半导体区域和半导体区域的半导体区域和半导体衬底的另一个半导体区域和半导体衬底隔离，其中，半导体区域的一侧和底部直接配置在其间具有构成控制电极的栅极绝缘膜因此，可以应用不受半导体区域和半导体衬底之间的接合屈服电压限制的高编程控制电压。因此，浮动电极的电容电极部分的面积可以大大减小。

10. 发明授权

US5592015A Dielectric isolated type semiconductor device provided with bipolar element 失效
标题翻译：具有双极元件的绝缘隔离型半导体器件
公开(公告)号：US5592015A
公开(公告)日：1997-01-07
申请号：US547740
申请日：1995-10-26
申请人： Makio Iida , Tadashi Shibata , Takayuki Sugisaka , Shoji Miura , Toshio Sakakibara
发明人： Makio Iida , Tadashi Shibata , Takayuki Sugisaka , Shoji Miura , Toshio Sakakibara
IPC分类号： H01L29/73 , H01L21/331 , H01L21/762 , H01L21/763 , H01L27/02 , H01L29/732 , H01L29/00 , H01L23/58
CPC分类号： H01L29/7322 , H01L21/76264 , H01L21/763 , H01L27/0248 , H01L21/76286
摘要： A semiconductor device is provided which makes a high withstand voltage bipolar transistor small and prevents deterioration in a switching speed of the transistor. A silicon oxide layer is formed on a silicon substrate, and a semiconductor island of one conductivity type which is isolated laterally by an isolation trench is formed on the silicon oxide layer. A silicon oxide film is formed on an outer periphery portion of the semiconductor island to bury the trench. In the semiconductor island, a bipolar transistor, namely a base region of the other conductivity type, is formed, and in the base region an emitter region of one conductivity type is formed and a collector region of one conductivity type is further formed. In the semiconductor island a diffusion region of the other conductivity type for extracting excessive carriers to which a constant electric potential is applied is further formed.
摘要翻译：提供一种半导体器件，其使得高耐压双极晶体管变小，并防止晶体管的开关速度的劣化。在硅衬底上形成硅氧化物层，在氧化硅层上形成由隔离沟侧向隔离的一种导电型半导体岛。在半导体岛的外周部形成有氧化硅膜，以埋置沟槽。在半导体岛中，形成双极晶体管，即另一种导电型的基极区域，在基极区域形成一个导电型的发射极区域，并进一步形成一种导电型的集电极区域。在半导体岛中，进一步形成用于提取施加恒定电位的过量载流子的另一导电类型的扩散区域。

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