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1. 发明申请

US20080135931A1 Power Semiconductor Devices Having Termination Structures and Methods of Manufacture 有权
标题翻译：具有终端结构和制造方法的功率半导体器件
公开(公告)号：US20080135931A1
公开(公告)日：2008-06-12
申请号：US12032123
申请日：2008-02-15
申请人： Ashok Challa , Alan Elbanhawy , Thomas E. Grebs , Nathan L. Kraft , Dean E. Probst , Rodney S. Ridlay , Steven P. Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter H. Wilson , Joseph A. Yedinak , J.Y. Jung , H.C. Jang , Babak S. Sanl , Richard Stokes , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher L. Rexer , Christopher B. Kocon , Debra S. Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas E. Grebs , Nathan L. Kraft , Dean E. Probst , Rodney S. Ridlay , Steven P. Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter H. Wilson , Joseph A. Yedinak , J.Y. Jung , H.C. Jang , Babak S. Sanl , Richard Stokes , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher L. Rexer , Christopher B. Kocon , Debra S. Woolsey
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region, source regions having the first conductivity type formed in the well region adjacent the active trench, and a first termination trench extending below the well region and disposed at an outer edge of an active region of the device. The sidewalls and bottom of the active trench are lined with dielectric material, and substantially filled with a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode, the upper electrode being disposed above the lower electrode and separated therefrom by inter-electrode dielectric material. The first termination trench can be lined with a layer of dielectric material that is thicker than the dielectric material lining the sidewalls of the active trench, and is substantially filled with conductive material.
摘要翻译：半导体功率器件包括第一导电类型的漂移区域，在漂移区域上方延伸并且具有与第一导电类型相反的第二导电类型的阱区域，延伸穿过阱区域并进入漂移区域的有源沟槽，源极区域具有形成在邻近有源沟槽的阱区中的第一导电类型，以及在阱区下延伸并设置在器件的有源区的外边缘处的第一端接沟槽。有源沟槽的侧壁和底部衬有介电材料，并且基本上填充有形成上电极的第一导电层和形成下电极的第二导电层，上电极设置在下电极之上，电介质材料。第一端接沟槽可以衬有一层电介质材料，其比在有源沟槽侧壁上的电介质材料更厚，并且基本上填充有导电材料。

2. 发明申请

US20120220091A1 METHODS OF MAKING POWER SEMICONDUCTOR DEVICES WITH THICK BOTTOM OXIDE LAYER 有权
标题翻译：制造具有厚底层氧化层的功率半导体器件的方法
公开(公告)号：US20120220091A1
公开(公告)日：2012-08-30
申请号：US13418128
申请日：2012-03-12
申请人： Ashok Challa , Alan Elbanhawy , Thomas E. Grebs , Nathan L. Kraft , Dean E. Probst , Rodney S. Ridley , Steven P. Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter H. Wilson , Joseph A. Yedinak , J.Y. Jung , H.C. Jang , Babak S. Sani , Richard Stokes , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher L. Rexer , Christopher B. Kocon , Debra S. Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas E. Grebs , Nathan L. Kraft , Dean E. Probst , Rodney S. Ridley , Steven P. Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter H. Wilson , Joseph A. Yedinak , J.Y. Jung , H.C. Jang , Babak S. Sani , Richard Stokes , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher L. Rexer , Christopher B. Kocon , Debra S. Woolsey
IPC分类号： H01L21/336 , H01L21/311
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench.
摘要翻译：在半导体衬底中形成的沟槽的底部形成厚氧化物的方法包括通过填充沟槽并覆盖衬底顶表面的亚大气压化学气相沉积工艺形成共形氧化膜。该方法还包括将氧化膜从衬底的顶表面和沟槽内部蚀刻，以留下在沟槽底部具有目标厚度的基本平坦的氧化物层。

3. 发明申请

US20080150020A1 Trenched Shield Gate Power Semiconductor Devices and Methods of Manufacture 有权
标题翻译：宽屏蔽门功率半导体器件及其制造方法
公开(公告)号：US20080150020A1
公开(公告)日：2008-06-26
申请号：US12018166
申请日：2008-01-22
申请人： Ashok Challa , Alan Elbanhawy , Thomas E. Grebs , Nathan L. Kraft , Dean E. Probst , Rodney S. Ridley , Steven P. Sapp , Qi Wang , Chongman Yun , J. G. Lee , Peter H. Wilson , Joseph A. Yedinak , J. Y. Jung , H. C. Jang , Babak S. Sani , Richard Stokes , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher L. Rexer , Christopher B. Kocon , Debra S. Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas E. Grebs , Nathan L. Kraft , Dean E. Probst , Rodney S. Ridley , Steven P. Sapp , Qi Wang , Chongman Yun , J. G. Lee , Peter H. Wilson , Joseph A. Yedinak , J. Y. Jung , H. C. Jang , Babak S. Sani , Richard Stokes , Gary M. Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher L. Rexer , Christopher B. Kocon , Debra S. Woolsey
IPC分类号： H01L29/78
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region. The active trench, which includes sidewalls and bottom lined with dielectric material, is substantially filled with a first conductive layer and a second conductive layer. The second conductive layer forms a gate electrode and is disposed above the first conductive layer and is separated from the first conductive layer by an inter-electrode dielectric material. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trench and a charge control trench that extends deeper into the drift region than the active trench and is substantially filled with material to allow for vertical charge control in the drift region. The charge control trench can be lined with a layer of dielectric material and substantially filled with conductive material. The active trench can include a second shield electrode made of conductive material disposed below the first shield electrode. The first conductive layer inside the active trench can form a secondary gate electrode that is configured to be electrically biased to a desired potential. The semiconductor device can also include a Schottky structure formed between the charge control trench and a second adjacent charge control trench.
摘要翻译：半导体功率器件包括第一导电类型的漂移区域，在漂移区域上方延伸并且具有与第一导电类型相反的第二导电类型的阱区域，延伸穿过阱区域并进入漂移区域的有源沟槽。主要沟槽包括侧壁和衬底与介电材料的底部，其基本上被第一导电层和第二导电层填充。第二导电层形成栅极，并且设置在第一导电层的上方，并且通过电极间电介质材料与第一导电层分离。该器件还包括形成在阱区内并且邻近有源沟槽的第一导电类型的源极区域以及充电控制沟槽，该电荷控制沟槽比有源沟槽更深地延伸到漂移区域中，并且基本上填充有材料以允许垂直电荷控制漂移区域。电荷控制沟槽可以衬有介电材料层并且基本上填充有导电材料。有源沟槽可以包括由设置在第一屏蔽电极下方的导电材料制成的第二屏蔽电极。有源沟槽内的第一导电层可以形成辅助栅电极，其被配置为电偏置到期望的电位。半导体器件还可以包括形成在电荷控制沟槽和第二相邻电荷控制沟槽之间的肖特基结构。

4. 发明申请

US20080138953A1 Methods of Making Power Semiconductor Devices with Thick Bottom Oxide Layer 有权
标题翻译：制造具有厚底层氧化物层的功率半导体器件的方法
公开(公告)号：US20080138953A1
公开(公告)日：2008-06-12
申请号：US12032599
申请日：2008-02-15
申请人： Ashok Challa , Alan Elbanhawy , Dean E. Probst , Steven P. Sapp , Peter H. Wilson , Babak S. Sani , Becky Losee , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher B. Kocon , Debra S. Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Dean E. Probst , Steven P. Sapp , Peter H. Wilson , Babak S. Sani , Becky Losee , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher B. Kocon , Debra S. Woolsey
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film that fills the trench and covers a top surface of the substrate. and etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench. The oxide film can be deposited by sub-atmospheric chemical vapor deposition processes, directional Tetraethoxysilate (TEOS) processes, or high density plasma deposition processes that form a thicker oxide at the bottom of the trench than on the sidewalls of the trench.
摘要翻译：在半导体衬底中形成的沟槽的底部形成厚氧化物的方法包括形成填充沟槽并覆盖衬底的顶表面的共形氧化物膜。并且将氧化膜从衬底的顶表面和沟槽内部蚀刻，以留下在沟槽底部具有目标厚度的基本平坦的氧化物层。氧化膜可以通过亚大气压化学气相沉积工艺，定向四乙氧基硅油（TEOS）工艺或高密度等离子体沉积工艺进行沉积，其在沟槽底部形成比在沟槽的侧壁上更厚的氧化物。

5. 发明授权

US08936985B2 Methods related to power semiconductor devices with thick bottom oxide layers 有权
标题翻译：与厚底层氧化物层的功率半导体器件相关的方法
公开(公告)号：US08936985B2
公开(公告)日：2015-01-20
申请号：US13418128
申请日：2012-03-12
申请人： Ashok Challa , Alan Elbanhawy , Dean E. Probst , Steven P. Sapp , Peter H. Wilson , Babak S. Sani , Becky Losee , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher B. Kocon , Debra S. Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Dean E. Probst , Steven P. Sapp , Peter H. Wilson , Babak S. Sani , Becky Losee , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher B. Kocon , Debra S. Woolsey
IPC分类号： H01L29/78 , H01L29/66 , H01L21/683 , H01L21/311 , H01L29/40 , H01L29/06 , H01L21/3065 , H01L29/739 , H02M3/335 , H02M3/00 , H01L29/10 , H02M7/48 , H01L29/49 , H01L29/423 , H01L29/165 , H01L23/495 , H01L21/265 , H01L29/417 , H01L23/498
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： A method can include forming a drift region, forming a well region above the drift region, and forming an active trench extending through the well region and into the drift region. The method can include forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench. The method also includes forming a charge control trench where the charge control trench is aligned parallel to the active trench and laterally separated from the active trench by a mesa region, and where the portion of the well region is in contact with the charge control trench and excludes any source region. The method also includes forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench.
摘要翻译：一种方法可以包括形成漂移区，在漂移区上形成阱区，以及形成延伸穿过阱区并进入漂移区的有源沟槽。该方法可以包括形成与有源沟槽的第一侧壁接触的第一源极区域和与有源沟槽的第二侧壁接触的第二源极区域。该方法还包括形成电荷控制沟槽，其中电荷控制沟槽平行于有源沟槽对齐并且通过台面区域与有源沟槽横向分离，并且其中阱区域的部分与电荷控制沟槽接触，排除任何来源地区。该方法还包括沿有源沟槽的底部沿着有源沟槽的第一侧壁形成厚度大于氧化物厚度的氧化物。

6. 发明授权

US08143124B2 Methods of making power semiconductor devices with thick bottom oxide layer 有权
标题翻译：制造具有厚底层氧化物层的功率半导体器件的方法
公开(公告)号：US08143124B2
公开(公告)日：2012-03-27
申请号：US12032599
申请日：2008-02-15
申请人： Ashok Challa , Alan Elbanhawy , Dean E. Probst , Steven P. Sapp , Peter H. Wilson , Babak S. Sani , Becky Losee , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher B. Kocon , Debra S. Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Dean E. Probst , Steven P. Sapp , Peter H. Wilson , Babak S. Sani , Becky Losee , Robert Herrick , James J. Murphy , Gordon K. Madson , Bruce D. Marchant , Christopher B. Kocon , Debra S. Woolsey
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom includes forming a drift region, a well region extending above the drift region, an active trench extending through the well region and into the drift region, a charge control trench extending deeper into the drift region than the active trench, an oxide film that fills the active trench, the charge control trench and covers a top surface of the substrate, an electrode in the active trench, and source regions. The method also includes etching the oxide film off the top surface of the substrate and inside the active trench to leave a substantially flat layer of thick oxide having a target thickness at the bottom of the active trench.
摘要翻译：制造具有电荷控制沟槽和具有厚氧化物底部的有源控制沟槽的半导体器件的方法包括形成漂移区，在漂移区上延伸的阱区，延伸穿过阱区并进入漂移区的有源沟槽，比有源沟槽更深地延伸到漂移区域中的电荷控制沟槽，填充有源沟槽，电荷控制沟槽并覆盖衬底的顶表面的氧化物膜，有源沟槽中的电极和源极区域。该方法还包括将氧化膜从衬底的顶表面和有源沟槽内部蚀刻，以留下在有源沟槽的底部具有目标厚度的基本平坦的厚氧化物层。

7. 发明申请

US20050167742A1 Power semiconductor devices and methods of manufacture 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20050167742A1
公开(公告)日：2005-08-04
申请号：US11026276
申请日：2004-12-29
申请人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
IPC分类号： G06F1/26 , H01L21/265 , H01L21/3065 , H01L21/311 , H01L21/336 , H01L21/68 , H01L23/495 , H01L23/498 , H01L29/06 , H01L29/165 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78 , H02M3/00 , H02M3/335
CPC分类号： H01L29/7802 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66734 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2224/16245 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.
摘要翻译：公开了用于改进的功率器件的各种实施例及其制造方法，封装和结合其的用于各种功率电子应用的电路。本发明的一个方面结合了许多电荷平衡技术和用于减小寄生电容的其它技术，以获得具有改进的电压性能，较高开关速度和较低导通电阻的功率器件的不同实施例。本发明的另一方面提供了用于低，中和高电压装置的改进的端接结构。根据本发明的其它方面提供了改进的功率器件制造方法。提出了具体的处理步骤的改进，例如沟槽的形成，沟槽内的电介质层的形成，台面结构的形成以及用于降低衬底厚度的工艺等。根据本发明的另一方面，电荷平衡功率器件在同一管芯上并入温度和电流检测元件，例如二极管。本发明的其它方面改进了用于功率器件的等效串联电阻（ESR），在与功率器件相同的芯片上并入附加电路，并提供对电荷平衡功率器件的封装的改进。

8. 发明申请

US20060214221A1 Power semiconductor devices and methods of manufacture 有权
公开(公告)号：US20060214221A1
公开(公告)日：2006-09-28
申请号：US11445020
申请日：2006-05-31
申请人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
IPC分类号： H01L29/76
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

9. 发明申请

US20060214222A1 Power semiconductor devices and methods of manufacture 有权
公开(公告)号：US20060214222A1
公开(公告)日：2006-09-28
申请号：US11445111
申请日：2006-05-31
申请人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J. Lee , Peter Wilson , Joseph Yedinak , J. Jung , H. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J. Lee , Peter Wilson , Joseph Yedinak , J. Jung , H. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
IPC分类号： H01L29/76
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

10. 发明申请

US20100015769A1 Power Device With Trenches Having Wider Upper Portion Than Lower Portion 有权
标题翻译：具有较宽部分的沟槽的电力设备比较低部分
公开(公告)号：US20100015769A1
公开(公告)日：2010-01-21
申请号：US12567578
申请日：2009-09-25
申请人： Robert Herrick , Becky Losee , Dean Probst
发明人： Robert Herrick , Becky Losee , Dean Probst
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/7802 , Y10S257/905
摘要： A method of forming a semiconductor device includes the following. A masking layer with opening is formed over a silicon layer. The silicon layer is isotropically etched through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each of which includes a middle portion and outer portions extending directly underneath the masking layer. The outer portions form outer sections of corresponding trenches. Additional portions of the silicon layer are removed through the masking layer openings so as to form a middle section of the trenches which extends deeper into the silicon layer than the outer sections of the trenches. A first doped region of a first conductivity type is formed in an upper portion of the silicon layer. An insulating layer is formed within each trench, and extends directly over a portion of the first doped region adjacent each trench sidewall. Silicon is removed from adjacent each trench until, of the first doped region, only the portions adjacent the trench sidewalls remain. The remaining portions of the first doped region adjacent the trench sidewalls form source regions which are self-aligned to the trenches.
摘要翻译：形成半导体器件的方法包括以下。在硅层上形成具有开口的掩模层。硅层通过掩模层开口进行各向同性蚀刻，从而去除硅层的碗状部分，其中每一个包括中间部分和直接在掩模层下方延伸的外部部分。外部部分形成相应沟槽的外部部分。通过掩模层开口去除硅层的附加部分，以形成比沟槽的外部部分更深地延伸到硅层的沟槽的中间部分。第一导电类型的第一掺杂区形成在硅层的上部。绝缘层形成在每个沟槽内，并且直接在邻近每个沟槽侧壁的第一掺杂区域的一部分上延伸。从相邻的每个沟槽去除硅，直到在第一掺杂区域中仅保留与沟槽侧壁相邻的部分。与沟槽侧壁相邻的第一掺杂区域的剩余部分形成与沟槽自对准的源极区域。

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