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1. 发明申请

US20050167742A1 Power semiconductor devices and methods of manufacture 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20050167742A1
公开(公告)日：2005-08-04
申请号：US11026276
申请日：2004-12-29
申请人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
IPC分类号： G06F1/26 , H01L21/265 , H01L21/3065 , H01L21/311 , H01L21/336 , H01L21/68 , H01L23/495 , H01L23/498 , H01L29/06 , H01L29/165 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78 , H02M3/00 , H02M3/335
CPC分类号： H01L29/7802 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66734 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2224/16245 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.
摘要翻译：公开了用于改进的功率器件的各种实施例及其制造方法，封装和结合其的用于各种功率电子应用的电路。本发明的一个方面结合了许多电荷平衡技术和用于减小寄生电容的其它技术，以获得具有改进的电压性能，较高开关速度和较低导通电阻的功率器件的不同实施例。本发明的另一方面提供了用于低，中和高电压装置的改进的端接结构。根据本发明的其它方面提供了改进的功率器件制造方法。提出了具体的处理步骤的改进，例如沟槽的形成，沟槽内的电介质层的形成，台面结构的形成以及用于降低衬底厚度的工艺等。根据本发明的另一方面，电荷平衡功率器件在同一管芯上并入温度和电流检测元件，例如二极管。本发明的其它方面改进了用于功率器件的等效串联电阻（ESR），在与功率器件相同的芯片上并入附加电路，并提供对电荷平衡功率器件的封装的改进。

2. 发明申请

US20060214221A1 Power semiconductor devices and methods of manufacture 有权
公开(公告)号：US20060214221A1
公开(公告)日：2006-09-28
申请号：US11445020
申请日：2006-05-31
申请人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
IPC分类号： H01L29/76
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

3. 发明申请

US20060214222A1 Power semiconductor devices and methods of manufacture 有权
公开(公告)号：US20060214222A1
公开(公告)日：2006-09-28
申请号：US11445111
申请日：2006-05-31
申请人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J. Lee , Peter Wilson , Joseph Yedinak , J. Jung , H. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J. Lee , Peter Wilson , Joseph Yedinak , J. Jung , H. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
IPC分类号： H01L29/76
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

4. 发明申请

US20070082441A1 Trench FET with Improved Body to Gate Alignment 有权
标题翻译：具有改进的阀门对准的沟槽FET
公开(公告)号：US20070082441A1
公开(公告)日：2007-04-12
申请号：US11551992
申请日：2006-10-23
申请人： Nathan Kraft , Ashok Challa , Steven Sapp , Hamza Yilmaz , Daniel Calafut , Dean Probst , Rodney Ridley , Thomas Grebs , Christopher Kocon , Joseph Yedinak , Gary Dolny
发明人： Nathan Kraft , Ashok Challa , Steven Sapp , Hamza Yilmaz , Daniel Calafut , Dean Probst , Rodney Ridley , Thomas Grebs , Christopher Kocon , Joseph Yedinak , Gary Dolny
IPC分类号： H01L21/8242
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.
摘要翻译：场效应晶体管如下形成。沟槽形成在第一导电类型的半导体区域中。每个沟槽部分地填充有一种或多种材料。执行双通角度注入以通过半导体区域的上表面和不被一种或多种材料覆盖的上沟槽侧壁将第二导电类型的掺杂剂注入半导体区域。进行高温处理以将注入的掺杂剂更深地驱动到台面区域中，从而在相邻的沟槽之间形成第二导电类型的体区。然后在每个身体区域中形成第一导电类型的源区域。

5. 发明申请

US20060273386A1 Trench-gate field effect transistors and methods of forming the same 失效
标题翻译：沟槽栅场效应晶体管及其形成方法
公开(公告)号：US20060273386A1
公开(公告)日：2006-12-07
申请号：US11441386
申请日：2006-05-24
申请人： Hamza Yilmaz , Daniel Calafut , Christopher Kocon , Steven Sapp , Dean Probst , Nathan Kraft , Thomas Grebs , Rodney Ridley , Gary Dolny , Bruce Marchant , Joseph Yedinak
发明人： Hamza Yilmaz , Daniel Calafut , Christopher Kocon , Steven Sapp , Dean Probst , Nathan Kraft , Thomas Grebs , Rodney Ridley , Gary Dolny , Bruce Marchant , Joseph Yedinak
IPC分类号： H01L29/94
CPC分类号： H01L29/7827 , H01L21/26586 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/872
摘要： A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.
摘要翻译：场效应晶体管包括在第二导电类型的半导体区域上的第一导电类型的体区。栅极沟槽延伸穿过身体区域并终止在半导体区域内。至少一个导电屏蔽电极设置在栅极沟槽中。栅极电极设置在栅极沟槽中，但与至少一个导电屏蔽电极绝缘。屏蔽介电层绝缘至少一个导电屏蔽电极与半导体区域。栅极电介质层使栅电极与体区绝缘。屏蔽电介质层形成为使其伸出并直接延伸到身体区域下方。

6. 发明申请

US20070032020A1 Structures and methods for forming shielded gate field effect transistors 有权
标题翻译：用于形成屏蔽栅场效应晶体管的结构和方法
公开(公告)号：US20070032020A1
公开(公告)日：2007-02-08
申请号：US11479117
申请日：2006-06-29
申请人： Thomas Grebs , Nathan Kraft , Rodney Ridley , Gary Dolny , Joseph Yedinak , Christopher Kocon , Ashok Challa
发明人： Thomas Grebs , Nathan Kraft , Rodney Ridley , Gary Dolny , Joseph Yedinak , Christopher Kocon , Ashok Challa
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A field effect transistor is formed as follows. A trench is formed in a semiconductor region. A dielectric layer lining the trench sidewalls and bottom is formed. The trench is filled with a conductive material. The conductive material is recessed into the trench to thereby form a shield electrode in a bottom portion of the trench. The recessing of the conductive material includes isotropic etching of the conductive material. An inter-electrode dielectric (IED) is formed over the recessed shield electrode.
摘要翻译：场效应晶体管如下形成。在半导体区域中形成沟槽。形成衬在沟槽侧壁和底部的电介质层。沟槽填充有导电材料。导电材料凹陷到沟槽中，从而在沟槽的底部形成屏蔽电极。导电材料的凹陷包括导电材料的各向同性蚀刻。在凹形屏蔽电极上形成电极间电介质（IED）。

7. 发明申请

US20070155104A1 Power device utilizing chemical mechanical planarization 失效
标题翻译：利用化学机械平面化的功率器件
公开(公告)号：US20070155104A1
公开(公告)日：2007-07-05
申请号：US11327657
申请日：2006-01-05
申请人： Bruce Marchant , Thomas Grebs , Rodney Ridley , Nathan Kraft
发明人： Bruce Marchant , Thomas Grebs , Rodney Ridley , Nathan Kraft
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/7811 , H01L21/3083 , H01L29/0696 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/7813 , Y10S438/942 , Y10S438/95
摘要： A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench.
摘要翻译：沟槽门控场效应晶体管（FET）如下形成。使用一个掩模，多个有源栅极沟槽和至少一个栅极流道沟槽被限定并同时形成在硅区域中，使得（i）至少一个栅极流道沟槽的宽度大于多个栅极沟槽的宽度的有源栅极沟槽，以及（ii）多个有源栅极沟槽与至少一个栅极流道沟槽邻接。

8. 发明申请

US20060030142A1 Semiconductor power device having a top-side drain using a sinker trench 有权
标题翻译：半导体功率器件具有使用沉陷沟槽的顶侧漏极
公开(公告)号：US20060030142A1
公开(公告)日：2006-02-09
申请号：US11194060
申请日：2005-07-28
申请人： Thomas Grebs , Gary Dolny
发明人： Thomas Grebs , Gary Dolny
IPC分类号： H01L21/4763
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/42368 , H01L29/7809 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type over and in contact with the substrate. A first trench extends into and terminates within the epitaxial layer. A sinker trench extends from the top surface of the epitaxial layer through the epitaxial layer and terminates within the substrate. The sinker trench is laterally spaced from the first trench, and is wider and extends deeper than the first trench. The sinker trench is lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the trench and makes electrical contact with an interconnect layer along the top of the trench.
摘要翻译：半导体功率器件包括第一导电类型的衬底和与衬底接触的第一导电类型的外延层。第一沟槽延伸到外延层中并终止于外延层内。沉降沟从外延层的顶表面延伸穿过外延层并终止于衬底内。沉降沟与第一沟槽横向间隔开，并且比第一沟槽更宽并且延伸得更深。沉陷沟槽沿着沉降片沟槽侧壁排列有绝缘体，使得填充沉陷沟槽的导电材料沿着沟槽的底部与衬底电接触，并且沿着沟槽的顶部与互连层电接触。

9. 发明授权

US06573569B2 Trench MOSFET with low gate charge 有权
标题翻译：沟槽MOSFET栅极电荷低
公开(公告)号：US06573569B2
公开(公告)日：2003-06-03
申请号：US09992629
申请日：2001-11-06
申请人： Jifa Hao , Thomas Grebs , Rodney S. Ridley , Louise Skurkey , Chris Gasser
发明人： Jifa Hao , Thomas Grebs , Rodney S. Ridley , Louise Skurkey , Chris Gasser
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/4232 , H01L29/42368 , H01L29/4238
摘要： A trench MOS-gated device has an upper surface and includes a substrate having an upper layer of doped monocrystalline semiconductor material of a first conduction type. A gate trench in the upper layer has sidewalls and a floor lined with a first dielectric material and a centrally disposed core formed of a second dielectric material extending upwardly from the first dielectric material on the trench floor and having lateral and top surfaces. The remainder of the trench is substantially filled with a conductive material that encompasses and contacts the lateral and top surfaces of the core of second dielectric material. A doped well region of a second conduction type overlies a drain zone of the first conduction type in the upper layer, and a heavily doped source region of the first conduction type contiguous to the gate trench and a heavily doped body region of the second conduction type are disposed in the well region at the upper surface of the device. An interlevel dielectric layer disposed on the upper surface overlies the gate trench and the source region, and a metal layer in electrical contact with the source and body regions overlies the upper surface and the interlevel dielectric layer.
摘要翻译：沟槽MOS门控器件具有上表面并且包括具有第一导电类型的掺杂单晶半导体材料的上层的衬底。上层中的栅极沟槽具有侧壁和内衬有第一电介质材料的底板和由第二电介质材料形成的居中设置的芯，该第二电介质材料从沟槽底板上的第一介电材料向上延伸并且具有侧表面和顶表面。沟槽的其余部分基本上填充有导电材料，该导电材料包围并接触第二电介质材料的芯的侧表面和顶表面。第二导电类型的掺杂阱区域覆盖在上层中的第一导电类型的漏极区域和与栅极沟槽连续的第一导电类型的重掺杂源极区域和第二导电类型的重掺杂体区域设置在装置的上表面的阱区域中。设置在上表面上的层间介质层覆盖栅极沟槽和源极区域，与源极和体区电接触的金属层覆盖上表面和层间电介质层。

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