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1. 发明申请

US20060214222A1 Power semiconductor devices and methods of manufacture 有权
公开(公告)号：US20060214222A1
公开(公告)日：2006-09-28
申请号：US11445111
申请日：2006-05-31
申请人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J. Lee , Peter Wilson , Joseph Yedinak , J. Jung , H. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J. Lee , Peter Wilson , Joseph Yedinak , J. Jung , H. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
IPC分类号： H01L29/76
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

2. 发明申请

US20050167742A1 Power semiconductor devices and methods of manufacture 有权
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20050167742A1
公开(公告)日：2005-08-04
申请号：US11026276
申请日：2004-12-29
申请人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
IPC分类号： G06F1/26 , H01L21/265 , H01L21/3065 , H01L21/311 , H01L21/336 , H01L21/68 , H01L23/495 , H01L23/498 , H01L29/06 , H01L29/165 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78 , H02M3/00 , H02M3/335
CPC分类号： H01L29/7802 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66734 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2224/16245 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.
摘要翻译：公开了用于改进的功率器件的各种实施例及其制造方法，封装和结合其的用于各种功率电子应用的电路。本发明的一个方面结合了许多电荷平衡技术和用于减小寄生电容的其它技术，以获得具有改进的电压性能，较高开关速度和较低导通电阻的功率器件的不同实施例。本发明的另一方面提供了用于低，中和高电压装置的改进的端接结构。根据本发明的其它方面提供了改进的功率器件制造方法。提出了具体的处理步骤的改进，例如沟槽的形成，沟槽内的电介质层的形成，台面结构的形成以及用于降低衬底厚度的工艺等。根据本发明的另一方面，电荷平衡功率器件在同一管芯上并入温度和电流检测元件，例如二极管。本发明的其它方面改进了用于功率器件的等效串联电阻（ESR），在与功率器件相同的芯片上并入附加电路，并提供对电荷平衡功率器件的封装的改进。

3. 发明申请

US20060214221A1 Power semiconductor devices and methods of manufacture 有权
公开(公告)号：US20060214221A1
公开(公告)日：2006-09-28
申请号：US11445020
申请日：2006-05-31
申请人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
发明人： Ashok Challa , Alan Elbanhawy , Thomas Grebs , Nathan Kraft , Dean Probst , Rodney Ridley , Steven Sapp , Qi Wang , Chongman Yun , J.G. Lee , Peter Wilson , Joseph Yedinak , J.Y. Jung , H.C. Jang , Babak Sani , Richard Stokes , Gary Dolny , John Mytych , Becky Losee , Adam Selsley , Robert Herrick , James Murphy , Gordon Madson , Bruce Marchant , Christopher Rexer , Christopher Kocon , Debra Woolsey
IPC分类号： H01L29/76
CPC分类号： H01L29/407 , H01L21/26586 , H01L21/3065 , H01L21/30655 , H01L21/31116 , H01L21/6835 , H01L23/4952 , H01L23/49816 , H01L29/0623 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/165 , H01L29/402 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933 , H01L29/495 , H01L29/66348 , H01L29/66734 , H01L29/7396 , H01L29/7802 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7815 , H01L29/7828 , H01L29/7831 , H01L2221/6834 , H01L2221/68363 , H01L2224/16 , H01L2924/01012 , H01L2924/01019 , H01L2924/01078 , H01L2924/10253 , H01L2924/12032 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/1532 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H02M3/00 , H02M3/33592 , H02M7/48 , Y02B70/1475 , H01L2924/00 , H01L2924/00014
摘要： Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

4. 发明申请

US20070082441A1 Trench FET with Improved Body to Gate Alignment 有权
标题翻译：具有改进的阀门对准的沟槽FET
公开(公告)号：US20070082441A1
公开(公告)日：2007-04-12
申请号：US11551992
申请日：2006-10-23
申请人： Nathan Kraft , Ashok Challa , Steven Sapp , Hamza Yilmaz , Daniel Calafut , Dean Probst , Rodney Ridley , Thomas Grebs , Christopher Kocon , Joseph Yedinak , Gary Dolny
发明人： Nathan Kraft , Ashok Challa , Steven Sapp , Hamza Yilmaz , Daniel Calafut , Dean Probst , Rodney Ridley , Thomas Grebs , Christopher Kocon , Joseph Yedinak , Gary Dolny
IPC分类号： H01L21/8242
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.
摘要翻译：场效应晶体管如下形成。沟槽形成在第一导电类型的半导体区域中。每个沟槽部分地填充有一种或多种材料。执行双通角度注入以通过半导体区域的上表面和不被一种或多种材料覆盖的上沟槽侧壁将第二导电类型的掺杂剂注入半导体区域。进行高温处理以将注入的掺杂剂更深地驱动到台面区域中，从而在相邻的沟槽之间形成第二导电类型的体区。然后在每个身体区域中形成第一导电类型的源区域。

5. 发明申请

US20060273386A1 Trench-gate field effect transistors and methods of forming the same 失效
标题翻译：沟槽栅场效应晶体管及其形成方法
公开(公告)号：US20060273386A1
公开(公告)日：2006-12-07
申请号：US11441386
申请日：2006-05-24
申请人： Hamza Yilmaz , Daniel Calafut , Christopher Kocon , Steven Sapp , Dean Probst , Nathan Kraft , Thomas Grebs , Rodney Ridley , Gary Dolny , Bruce Marchant , Joseph Yedinak
发明人： Hamza Yilmaz , Daniel Calafut , Christopher Kocon , Steven Sapp , Dean Probst , Nathan Kraft , Thomas Grebs , Rodney Ridley , Gary Dolny , Bruce Marchant , Joseph Yedinak
IPC分类号： H01L29/94
CPC分类号： H01L29/7827 , H01L21/26586 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/872
摘要： A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.
摘要翻译：场效应晶体管包括在第二导电类型的半导体区域上的第一导电类型的体区。栅极沟槽延伸穿过身体区域并终止在半导体区域内。至少一个导电屏蔽电极设置在栅极沟槽中。栅极电极设置在栅极沟槽中，但与至少一个导电屏蔽电极绝缘。屏蔽介电层绝缘至少一个导电屏蔽电极与半导体区域。栅极电介质层使栅电极与体区绝缘。屏蔽电介质层形成为使其伸出并直接延伸到身体区域下方。

6. 发明申请

US20070032020A1 Structures and methods for forming shielded gate field effect transistors 有权
标题翻译：用于形成屏蔽栅场效应晶体管的结构和方法
公开(公告)号：US20070032020A1
公开(公告)日：2007-02-08
申请号：US11479117
申请日：2006-06-29
申请人： Thomas Grebs , Nathan Kraft , Rodney Ridley , Gary Dolny , Joseph Yedinak , Christopher Kocon , Ashok Challa
发明人： Thomas Grebs , Nathan Kraft , Rodney Ridley , Gary Dolny , Joseph Yedinak , Christopher Kocon , Ashok Challa
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A field effect transistor is formed as follows. A trench is formed in a semiconductor region. A dielectric layer lining the trench sidewalls and bottom is formed. The trench is filled with a conductive material. The conductive material is recessed into the trench to thereby form a shield electrode in a bottom portion of the trench. The recessing of the conductive material includes isotropic etching of the conductive material. An inter-electrode dielectric (IED) is formed over the recessed shield electrode.
摘要翻译：场效应晶体管如下形成。在半导体区域中形成沟槽。形成衬在沟槽侧壁和底部的电介质层。沟槽填充有导电材料。导电材料凹陷到沟槽中，从而在沟槽的底部形成屏蔽电极。导电材料的凹陷包括导电材料的各向同性蚀刻。在凹形屏蔽电极上形成电极间电介质（IED）。

7. 发明申请

US20080042143A1 AVALANCHE PROTECTION FOR WIDE BANDGAP DEVICES 有权
标题翻译： AVALANCHE保护宽带配置
公开(公告)号：US20080042143A1
公开(公告)日：2008-02-21
申请号：US11828283
申请日：2007-07-25
申请人： Joseph Yedinak , Richard Woodin , Christopher Rexer , Praveen Shenoy , Kwanghoon Oh , Chongman Yun
发明人： Joseph Yedinak , Richard Woodin , Christopher Rexer , Praveen Shenoy , Kwanghoon Oh , Chongman Yun
IPC分类号： H01L31/0312 , H01L21/00
CPC分类号： H01L29/872 , H01L27/0248 , H01L29/1608 , H01L29/8618 , H01L29/87
摘要： A method and device for protecting wide bandgap devices from failing during suppression of voltage transients. An improvement in avalanche capability is achieved by placing one or more diodes, or a PNP transistor, across the blocking junction of the wide bandgap device.
摘要翻译：一种用于在抑制电压瞬变期间保护宽带隙器件不发生故障的方法和装置。通过在宽带隙器件的阻塞结上放置一个或多个二极管或PNP晶体管来实现雪崩能力的改善。

8. 发明申请

US20140273374A1 Vertical Doping and Capacitive Balancing for Power Semiconductor Devices 审中-公开
标题翻译：功率半导体器件的垂直掺杂和电容平衡
公开(公告)号：US20140273374A1
公开(公告)日：2014-09-18
申请号：US13842694
申请日：2013-03-15
申请人： Joseph Yedinak , Richard Stokes , Sukhendu Deb Roy , Steven Sapp
发明人： Joseph Yedinak , Richard Stokes , Sukhendu Deb Roy , Steven Sapp
IPC分类号： H01L29/66
CPC分类号： H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7805 , H01L29/7813
摘要： Vertical doping in power semiconductor devices and methods for making such dopant profiles are described. The methods include providing a semiconductor substrate, providing an epitaxial layer on the substrate, the epitaxial layer comprising a bottom portion containing a first conductivity type dopant in a substantially constant, first concentration throughout the bottom portion; and an upper portion containing a first conductivity type dopant having a second concentration lower than the first concentration; providing a trench in the epitaxial layer; forming a transistor structure in the trench; and forming a well region in the upper part of the epitaxial layer adjacent the trench, the well region containing a second conductivity type dopant that is opposite the first conductivity type. Other embodiments are described.
摘要翻译：描述了功率半导体器件中的垂直掺杂和用于制造这种掺杂剂分布的方法。所述方法包括提供半导体衬底，在衬底上提供外延层，所述外延层包含底部，该底部包含基本上恒定的第一浓度遍及整个底部的第一导电型掺杂剂; 和含有第二浓度低于第一浓度的第一导电型掺杂剂的上部; 在外延层中提供沟槽; 在沟槽中形成晶体管结构; 以及在与所述沟槽相邻的所述外延层的上部中形成阱区，所述阱区包含与所述第一导电类型相反的第二导电型掺杂剂。描述其他实施例。

9. 发明申请

US20070181927A1 Charge balance insulated gate bipolar transistor 审中-公开
标题翻译：电荷平衡绝缘栅双极晶体管
公开(公告)号：US20070181927A1
公开(公告)日：2007-08-09
申请号：US11408812
申请日：2006-04-21
申请人： Joseph Yedinak , Kwang Oh , Chongman Yun , Jae Lee
发明人： Joseph Yedinak , Kwang Oh , Chongman Yun , Jae Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/7395 , H01L29/0634 , H01L29/0696 , H01L29/0834 , H01L29/1095 , H01L29/7397
摘要： An IGBT includes a first silicon region over a collector region, and a plurality of pillars of first and second conductivity types arranged in an alternating manner over the first silicon region. The IGBT further includes a plurality of well regions each extending over and being in electrical contact with one of the pillars of the first conductivity type, and a plurality of gate electrodes each extending over a portion of a corresponding well region. The physical dimensions of each of the first and second conductivity type pillars and the doping concentration of charge carriers in each of the first and second conductivity type pillars are selected so as to create a charge imbalance between a net charge in each pillar of first conductivity and a net charge in its adjacent pillar of the second conductivity type.
摘要翻译： IGBT包括在集电极区域上的第一硅区域和在第一硅区域上以交替方式布置的多个第一和第二导电类型的柱。 IGBT进一步包括多个阱区，每个阱区延伸并且与第一导电类型的一个柱中的一个电接触，并且多个栅电极各自延伸在对应的阱区的一部分上。选择第一和第二导电型柱中的每一个的物理尺寸和第一和第二导电类型柱中的每一个中的载流子的掺杂浓度，以便在第一导电性的每个支柱中的净电荷和其第二导电类型的相邻支柱中的净电荷。

10. 发明申请

US20100207205A1 Structures and Methods for Improving Trench-Shielded Semiconductor Devices and Schottky Barrier Rectifier Devices 有权
标题翻译：用于改进沟槽屏蔽半导体器件和肖特基势垒整流器件的结构和方法
公开(公告)号：US20100207205A1
公开(公告)日：2010-08-19
申请号：US12389335
申请日：2009-02-19
申请人： Thomas E. Grebs , Mark Rinehimer , Joseph Yedinak , Dean E. Probst , Gary Dolny , John Benjamin
发明人： Thomas E. Grebs , Mark Rinehimer , Joseph Yedinak , Dean E. Probst , Gary Dolny , John Benjamin
IPC分类号： H01L27/088 , G03F1/00 , H01L21/8234 , H01L21/336
CPC分类号： H01L29/872 , H01L23/544 , H01L29/0657 , H01L29/66143 , H01L29/7811 , H01L29/8725 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described.
摘要翻译：描述了用于改善沟槽屏蔽功率半导体器件等的性能的各种结构和方法。

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