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1. 发明申请

US20090230482A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090230482A1
公开(公告)日：2009-09-17
申请号：US12404562
申请日：2009-03-16
申请人： Yoshiaki KATO , Yoshiharu ANDA , Akiyoshi TAMURA
发明人： Yoshiaki KATO , Yoshiharu ANDA , Akiyoshi TAMURA
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L27/0605 , H01L27/0883 , H01L29/66462 , H01L29/7783
摘要： A semiconductor device in which an E-FET and a D-FET are integrated on the same substrate, wherein an epitaxial layer includes, in the following order from the semiconductor substrate: a first threshold adjustment layer that adjusts a threshold voltage of a gate of the E-FET and a threshold voltage of a gate of the D-FET; a first etching-stopper layer that stops etching performed from an uppermost layer to a layer abutting on the first etching-stopper layer; a second threshold adjustment layer that adjusts the threshold voltage of the gate of the D-FET; and a second etching-stopper layer that stops the etching performed from the uppermost layer to a layer abutting on the second etching-stopper layer, and at least one of the first etching-stopper layer and the second threshold adjustment layer includes an n-type doped region.
摘要翻译：一种半导体器件，其中E-FET和D-FET集成在同一衬底上，其中外延层从半导体衬底按以下顺序包括：第一阈值调节层，其调节栅极的阈值电压 E-FET和D-FET的栅极的阈值电压; 第一蚀刻停止层，其停止从最上层到邻接于所述第一蚀刻停止层的层的蚀刻; 调节D-FET的栅极的阈值电压的第二阈值调整层; 以及第二蚀刻停止层，其将从最上层进行的蚀刻停止到与第二蚀刻停止层相邻的层，并且第一蚀刻停止层和第二阈值调整层中的至少一个包括n型掺杂区域。

2. 发明申请

US20120153355A1 NITRIDE SEMICONDUCTOR DEVICE 有权
标题翻译：氮化物半导体器件
公开(公告)号：US20120153355A1
公开(公告)日：2012-06-21
申请号：US13402631
申请日：2012-02-22
申请人： Hidekazu UMEDA , Yoshiharu Anda , Tetsuzo Ueda , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Hidekazu UMEDA , Yoshiharu Anda , Tetsuzo Ueda , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L29/78
CPC分类号： H01L29/2003 , H01L29/1066 , H01L29/4175 , H01L29/66462 , H01L29/7787 , H01L29/861
摘要： A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.
摘要翻译：氮化物半导体器件包括半导体衬底和形成在半导体衬底上的氮化物半导体层。半导体衬底包括正常区域和围绕法线区域的界面电流阻挡区域。氮化物半导体层包括元件区域和围绕元件区域的隔离区域。元件区域形成在正常区域上。界面电流阻挡区域含有杂质，并且在氮化物半导体层和半导体衬底之间的界面处产生的载流子形成势垒。

3. 发明申请

US20090309134A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090309134A1
公开(公告)日：2009-12-17
申请号：US12423347
申请日：2009-04-14
申请人： Akihiko Nishio , Yoshiaki Shimada , Yoshiaki Kato , Yoshiharu Anda
发明人： Akihiko Nishio , Yoshiaki Shimada , Yoshiaki Kato , Yoshiharu Anda
IPC分类号： H01L29/812 , H01L21/335
CPC分类号： H01L29/66462 , H01L29/7787
摘要： A multilayer structure including a first electron supply layer and a second electron supply layer is used for an electron supply layer. A multilayer structure including an SiN film and an SiO2 film is used for an insulating film to be formed on the surface of a semiconductor. In forming an opening for exposing the electron supply layer in the insulating film, the SiN film that is in contact with the semiconductor is side-etched. Accordingly, it is possible to avoid a contact between a gate electrode and a portion, which is located on the side of the electron supply layer, of the inner peripheral surface of the opening, and further to expose only the second electron supply layer in the vicinity of the gate electrode.
摘要翻译：包括第一电子供应层和第二电子供应层的多层结构被用于电子供应层。使用包括SiN膜和SiO 2膜的多层结构来形成在半导体的表面上的绝缘膜。在形成用于暴露绝缘膜中的电子供给层的开口时，与半导体接触的SiN膜被侧蚀刻。因此，可以避免栅电极与位于电子供给层一侧的部分之间的开口的内周面的接触，并且还可以仅暴露于第二电子供给层栅电极附近。

4. 发明申请

US20070295991A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070295991A1
公开(公告)日：2007-12-27
申请号：US11757533
申请日：2007-06-04
申请人： Yoshiaki KATO , Yoshiharu ANDA , Akiyoshi TAMURA
发明人： Yoshiaki KATO , Yoshiharu ANDA , Akiyoshi TAMURA
IPC分类号： H01L29/812 , H01L21/338
CPC分类号： H01L29/8128 , H01L29/42316 , H01L29/66863 , H01L29/778
摘要： A semiconductor device according to the present invention includes: a semiconductor substrate; a channel layer formed on the semiconductor substrate; a donor layer formed on the channel layer; a first Schottky layer formed on the donor layer; a second Schottky layer formed on the first Schottky layer; a first gate electrode formed on the first Schottky layer to form a Schottky barrier junction with the first Schottky layer; a first source electrode and a first drain electrode formed so as to sandwich the first gate electrode and electrically connected to the channel layer; a second gate electrode formed on the second Schottky layer and made of a material different from the first gate electrode to form a Schottky barrier junction with the second Schottky layer; and a second source electrode and a second drain electrode formed so as to sandwich the second gate electrode and electrically connected to the channel layer.
摘要翻译：根据本发明的半导体器件包括：半导体衬底; 形成在所述半导体衬底上的沟道层; 在沟道层上形成的施主层; 形成在供体层上的第一肖特基层; 形成在第一肖特基层上的第二肖特基层; 形成在所述第一肖特基层上以与所述第一肖特基层形成肖特基势垒结的第一栅电极; 第一源电极和第一漏电极，其形成为夹着所述第一栅电极并电连接到所述沟道层; 第二栅电极，形成在所述第二肖特基层上，并且由与所述第一栅电极不同的材料制成，以与所述第二肖特基层形成肖特基势垒结; 以及第二源电极和第二漏电极，其形成为夹着所述第二栅极并电连接到所述沟道层。

5. 发明授权

US07199014B2 Field effect transistor and method of manufacturing the same 失效
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US07199014B2
公开(公告)日：2007-04-03
申请号：US11000239
申请日：2004-12-01
申请人： Yoshiharu Anda
发明人： Yoshiharu Anda
IPC分类号： H01L21/336
CPC分类号： H01L29/66462 , H01L29/7784
摘要： There is provided a field effect transistor which is suitable for a power amplifier application or the like, and have a double recess structure with superior repeatability. A film thickness of an AlGaAs layer can determine a depth of a second step of a recess uniquely by using the AlGaAs layer and an InGaP layer with a higher etching selection ratio, a double recess structure can be formed with desirable repeatability, and a high withstand voltage device suitable for a power amplifier application or the like is achieved by making both side surfaces of a gate electrode into the AlGaAs layer.
摘要翻译：提供了适用于功率放大器应用等的场效应晶体管，并且具有优异的重复性的双凹槽结构。 AlGaAs层的膜厚度可以通过使用AlGaAs层和具有较高蚀刻选择比的InGaP层来唯一地确定凹部的第二阶梯深度，可以形成具有所需重复性的双凹槽结构，并且具有高耐受性通过使栅电极的两个侧表面成为AlGaAs层来实现适用于功率放大器应用等的电压装置。

6. 发明授权

US06967360B2 Pseudomorphic high electron mobility transistor with Schottky electrode including lanthanum and boron, and manufacturing method thereof 失效
标题翻译：包含镧和硼的肖特基电极的假晶高电子迁移率晶体管及其制造方法
公开(公告)号：US06967360B2
公开(公告)日：2005-11-22
申请号：US10617793
申请日：2003-07-14
申请人： Yoshiharu Anda , Akiyoshi Tamura
发明人： Yoshiharu Anda , Akiyoshi Tamura
IPC分类号： H01L21/28 , H01L21/335 , H01L21/338 , H01L29/423 , H01L29/47 , H01L29/778 , H01L29/812 , H01L29/872 , H01L31/0328
CPC分类号： H01L29/66462 , H01L29/475 , H01L29/7784
摘要： A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel layer 323, a spacer layer 324, a carrier supply layer 325, a spacer layer 326, a Schottky layer 327 composed of an undoped In0.48Ga0.52P material, and an n+-type GaAs cap layer 328. A gate electrode 330 is formed on the Schottky layer 327, and is composed of LaB6 and has a Schottky contact with the Schottky layer 327, and ohmic electrodes 340 are formed on the n+-type GaAs cap layer 328.
摘要翻译：一种半导体器件及其制造方法。半导体器件具有半绝缘GaAs衬底310，形成在半绝缘GaAs衬底310上的GaAs缓冲层321，AlGaAs缓冲层322，沟道层323，间隔层324，载流子供应层325，间隔层326，由未掺杂的In 0.48 Ga 0.52 P材料构成的肖特基层327和n + 栅电极330形成在肖特基层327上，由LaB 6构成，与肖特基层327具有肖特基接触，并且欧姆电极340形成在第n + +型GaAs覆盖层328。

7. 发明授权

US08872227B2 Nitride semiconductor device 有权
标题翻译：氮化物半导体器件
公开(公告)号：US08872227B2
公开(公告)日：2014-10-28
申请号：US13402631
申请日：2012-02-22
申请人： Hidekazu Umeda , Yoshiharu Anda , Tetsuzo Ueda , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Hidekazu Umeda , Yoshiharu Anda , Tetsuzo Ueda , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L29/66 , H01L29/778 , H01L29/417 , H01L29/20
CPC分类号： H01L29/2003 , H01L29/1066 , H01L29/4175 , H01L29/66462 , H01L29/7787 , H01L29/861
摘要： A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.
摘要翻译：氮化物半导体器件包括半导体衬底和形成在半导体衬底上的氮化物半导体层。半导体衬底包括正常区域和围绕法线区域的界面电流阻挡区域。氮化物半导体层包括元件区域和围绕元件区域的隔离区域。元件区域形成在正常区域上。界面电流阻挡区域含有杂质，并且在氮化物半导体层和半导体衬底之间的界面处产生的载流子形成势垒。

8. 发明申请

US20060237753A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060237753A1
公开(公告)日：2006-10-26
申请号：US11388545
申请日：2006-03-24
申请人： Yoshiharu Anda , Akiyoshi Tamura , Mitsuru Nishitsuji
发明人： Yoshiharu Anda , Akiyoshi Tamura , Mitsuru Nishitsuji
IPC分类号： H01L31/112
CPC分类号： H01L29/7784 , H01L21/28575 , H01L21/28587 , H01L29/66462
摘要： A field effect transistor according to the present invention includes a channel layer formed above a semi-insulating substrate, a Schottky layer formed above the channel layer, a gate electrode formed on the Schottky layer, Ohmic contact layers that are located above the Schottky layer with the gate electrode interposed therebetween and formed of InGaAs, and a source electrode and a drain electrode that are formed on the Ohmic contact layers. The source electrode, the drain electrode and the gate electrode have a layered structure in which their corresponding layers are formed of the same material, a lowermost layer is a WSi layer and a layer containing Al is provided above the lowermost layer. A field effect transistor that has an electrode resistance equivalent to a conventional level and can reduce a cost of manufacturing a field effect transistor and a method for manufacturing the same are provided.
摘要翻译：根据本发明的场效应晶体管包括形成在半绝缘衬底上的沟道层，形成在沟道层上方的肖特基层，形成在肖特基层上的栅电极，位于肖特基层上方的欧姆接触层，介于其间并由InGaAs形成的栅电极以及形成在欧姆接触层上的源电极和漏电极。源电极，漏电极和栅电极具有层叠结构，其相应的层由相同的材料形成，最下层是WSi层，并且在最下层上设置含有Al的层。提供具有等同于常规水平的电极电阻并且可以降低制造场效应晶体管的成本的场效应晶体管及其制造方法。

9. 发明申请

US20050139868A1 Field effect transistor and method of manufacturing the same 失效
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20050139868A1
公开(公告)日：2005-06-30
申请号：US11000239
申请日：2004-12-01
申请人： Yoshiharu Anda
发明人： Yoshiharu Anda
IPC分类号： H01L29/417 , H01L21/335 , H01L21/338 , H01L29/47 , H01L29/778 , H01L29/812 , H01L29/872 , H01S5/00 , H01L29/745 , H01L29/76
CPC分类号： H01L29/66462 , H01L29/7784
摘要： There is provided a field effect transistor which is suitable for a power amplifier application or the like, and have a double recess structure with superior repeatability. A film thickness of an AlGaAs layer can determine a depth of a second step of a recess uniquely by using the AlGaAs layer and an InGaP layer with a higher etching selection ratio, a double recess structure can be formed with desirable repeatability, and a high withstand voltage device suitable for a power amplifier application or the like is achieved by making both side surfaces of a gate electrode into the AlGaAs layer.
摘要翻译：提供了适用于功率放大器应用等的场效应晶体管，并且具有优异的重复性的双凹槽结构。 AlGaAs层的膜厚度可以通过使用AlGaAs层和具有较高蚀刻选择比的InGaP层来唯一地确定凹部的第二阶梯深度，可以形成具有所需重复性的双凹槽结构，并且具有高耐受性通过使栅电极的两个侧表面成为AlGaAs层来实现适用于功率放大器应用等的电压装置。

10. 发明授权

US06548838B1 Field-effect transistor, bipolar transistor, and methods of fabricating the same 失效
标题翻译：场效应晶体管，双极晶体管及其制造方法
公开(公告)号：US06548838B1
公开(公告)日：2003-04-15
申请号：US09666157
申请日：2000-09-19
申请人： Yoshiharu Anda , Mitsuru Nishitsuji , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Yoshiharu Anda , Mitsuru Nishitsuji , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L310328
CPC分类号： H01L29/66462 , H01L29/41725 , H01L29/7784
摘要： A field-effect transistor of the present invention has first semiconductor layers disposed in at least two regions located above a substrate and spaced apart in a direction parallel to a substrate surface, second semiconductor layers disposed on the respective first semiconductor layers to protrude from the respective side surfaces of the first semiconductor layers, and ohmic electrodes disposed on the respective second semiconductor layers. The field-effect transistor also has a gate electrode formed by self alignment relative to the ohmic electrodes, which is disposed in a region located above the substrate and lying between the first semiconductor layers in spaced relation to the respective side surfaces of the first semiconductor layers.
摘要翻译：本发明的场效应晶体管具有位于基板上方的至少两个区域中的第一半导体层，并且在平行于衬底表面的方向上间隔开，第二半导体层设置在相应的第一半导体层上以从相应的第一半导体层的侧表面和设置在相应的第二半导体层上的欧姆电极。场效应晶体管还具有通过相对于欧姆电极进行自对准而形成的栅电极，该欧姆电极设置在位于衬底上方的区域中，并且位于第一半导体层之间，与第一半导体层的相应侧表面间隔开。

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