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1. 发明申请

US20060237753A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060237753A1
公开(公告)日：2006-10-26
申请号：US11388545
申请日：2006-03-24
申请人： Yoshiharu Anda , Akiyoshi Tamura , Mitsuru Nishitsuji
发明人： Yoshiharu Anda , Akiyoshi Tamura , Mitsuru Nishitsuji
IPC分类号： H01L31/112
CPC分类号： H01L29/7784 , H01L21/28575 , H01L21/28587 , H01L29/66462
摘要： A field effect transistor according to the present invention includes a channel layer formed above a semi-insulating substrate, a Schottky layer formed above the channel layer, a gate electrode formed on the Schottky layer, Ohmic contact layers that are located above the Schottky layer with the gate electrode interposed therebetween and formed of InGaAs, and a source electrode and a drain electrode that are formed on the Ohmic contact layers. The source electrode, the drain electrode and the gate electrode have a layered structure in which their corresponding layers are formed of the same material, a lowermost layer is a WSi layer and a layer containing Al is provided above the lowermost layer. A field effect transistor that has an electrode resistance equivalent to a conventional level and can reduce a cost of manufacturing a field effect transistor and a method for manufacturing the same are provided.
摘要翻译：根据本发明的场效应晶体管包括形成在半绝缘衬底上的沟道层，形成在沟道层上方的肖特基层，形成在肖特基层上的栅电极，位于肖特基层上方的欧姆接触层，介于其间并由InGaAs形成的栅电极以及形成在欧姆接触层上的源电极和漏电极。源电极，漏电极和栅电极具有层叠结构，其相应的层由相同的材料形成，最下层是WSi层，并且在最下层上设置含有Al的层。提供具有等同于常规水平的电极电阻并且可以降低制造场效应晶体管的成本的场效应晶体管及其制造方法。

2. 发明授权

US06548838B1 Field-effect transistor, bipolar transistor, and methods of fabricating the same 失效
标题翻译：场效应晶体管，双极晶体管及其制造方法
公开(公告)号：US06548838B1
公开(公告)日：2003-04-15
申请号：US09666157
申请日：2000-09-19
申请人： Yoshiharu Anda , Mitsuru Nishitsuji , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Yoshiharu Anda , Mitsuru Nishitsuji , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L310328
CPC分类号： H01L29/66462 , H01L29/41725 , H01L29/7784
摘要： A field-effect transistor of the present invention has first semiconductor layers disposed in at least two regions located above a substrate and spaced apart in a direction parallel to a substrate surface, second semiconductor layers disposed on the respective first semiconductor layers to protrude from the respective side surfaces of the first semiconductor layers, and ohmic electrodes disposed on the respective second semiconductor layers. The field-effect transistor also has a gate electrode formed by self alignment relative to the ohmic electrodes, which is disposed in a region located above the substrate and lying between the first semiconductor layers in spaced relation to the respective side surfaces of the first semiconductor layers.
摘要翻译：本发明的场效应晶体管具有位于基板上方的至少两个区域中的第一半导体层，并且在平行于衬底表面的方向上间隔开，第二半导体层设置在相应的第一半导体层上以从相应的第一半导体层的侧表面和设置在相应的第二半导体层上的欧姆电极。场效应晶体管还具有通过相对于欧姆电极进行自对准而形成的栅电极，该欧姆电极设置在位于衬底上方的区域中，并且位于第一半导体层之间，与第一半导体层的相应侧表面间隔开。

3. 发明授权

US06570464B1 High frequency apparatus 失效
标题翻译：高频设备
公开(公告)号：US06570464B1
公开(公告)日：2003-05-27
申请号：US09648498
申请日：2000-08-25
申请人： Mitsuru Tanabe , Mitsuru Nishitsuji , Yoshiharu Anda
发明人： Mitsuru Tanabe , Mitsuru Nishitsuji , Yoshiharu Anda
IPC分类号： H01P500
CPC分类号： H01P3/003 , H01P11/003
摘要： A high frequency apparatus includes a dielectric substrate having a surface including a first area and at least one second area; a first dielectric thin layer provided on a portion of a first area; and a uniplanar transmission line provided on the first dielectric thin layer and on a portion of the second area, the uniplanar transmission line extending, continuously on the second area and the first dielectric thin layer.
摘要翻译：高频装置包括具有包括第一区域和至少一个第二区域的表面的电介质基板; 设置在第一区域的一部分上的第一电介质薄层; 以及设置在所述第一电介质薄层上和所述第二区域的一部分上的所述单面传输线，所述单面传输线在所述第二区域和所述第一电介质薄层上连续地延伸。

4. 发明授权

US06300190B1 Method for fabricating semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US06300190B1
公开(公告)日：2001-10-09
申请号：US09452389
申请日：1999-12-01
申请人： Mitsuru Nishitsuji , Yoshiharu Anda , Katsuhiko Kawashima , Tsuyoshi Tanaka
发明人： Mitsuru Nishitsuji , Yoshiharu Anda , Katsuhiko Kawashima , Tsuyoshi Tanaka
IPC分类号： H01L218242
CPC分类号： H01L29/66863 , H01L21/28587 , H01L27/0629
摘要： First, an insulating film is formed over the entire surface of a semiconductor substrate including a channel region for a field effect transistor. The insulating film has a gate electrode opening over the channel region. Next, a protective film is deposited over the entire surface of the insulating film. Then, a lower electrode, a capacitive insulating film and an upper electrode are formed in this order in a region on the protective film where a capacitor will be formed. Subsequently, part of the protective film, with which the gate electrode opening of the insulating film has been filled in, is removed, thereby exposing the semiconductor substrate within the gate electrode opening. And then a gate electrode is formed to fill in the gate electrode opening again.
摘要翻译：首先，在包括场效应晶体管的沟道区域的半导体衬底的整个表面上形成绝缘膜。绝缘膜具有在沟道区域上开口的栅电极。接下来，在绝缘膜的整个表面上沉积保护膜。然后，在保护膜上将形成电容器的区域中，依次形成下电极，电容绝缘膜和上电极。随后，去除绝缘膜的栅电极开口已经填充的保护膜的一部分，从而使半导体衬底暴露在栅电极开口内。然后形成栅电极以再次填充栅电极开口。

5. 发明授权

US06329227B2 Method of patterning organic polymer film and method for fabricating semiconductor device 有权
公开(公告)号：US06329227B2
公开(公告)日：2001-12-11
申请号：US09789738
申请日：2001-02-22
申请人： Yoshiharu Anda , Mitsuru Nishitsuji , Katsuhiko Kawashima , Tsuyoshi Tanaka
发明人： Yoshiharu Anda , Mitsuru Nishitsuji , Katsuhiko Kawashima , Tsuyoshi Tanaka
IPC分类号： H01L2100
CPC分类号： H01L21/02118 , H01L21/0212 , H01L21/02274 , H01L21/28581 , H01L21/28587 , H01L21/3081 , H01L21/3088 , H01L21/31138 , H01L21/312
摘要： An organic polymer film patterning method includes the steps of: defining a resist film on a selected area of a substrate; depositing an organic polymer film over the substrate by a plasma CVD process so that the resist film is covered with part of the organic polymer film; and removing the resist film along with the part of the organic polymer film that has covered the resist film.

6. 发明授权

US06967360B2 Pseudomorphic high electron mobility transistor with Schottky electrode including lanthanum and boron, and manufacturing method thereof 失效
标题翻译：包含镧和硼的肖特基电极的假晶高电子迁移率晶体管及其制造方法
公开(公告)号：US06967360B2
公开(公告)日：2005-11-22
申请号：US10617793
申请日：2003-07-14
申请人： Yoshiharu Anda , Akiyoshi Tamura
发明人： Yoshiharu Anda , Akiyoshi Tamura
IPC分类号： H01L21/28 , H01L21/335 , H01L21/338 , H01L29/423 , H01L29/47 , H01L29/778 , H01L29/812 , H01L29/872 , H01L31/0328
CPC分类号： H01L29/66462 , H01L29/475 , H01L29/7784
摘要： A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel layer 323, a spacer layer 324, a carrier supply layer 325, a spacer layer 326, a Schottky layer 327 composed of an undoped In0.48Ga0.52P material, and an n+-type GaAs cap layer 328. A gate electrode 330 is formed on the Schottky layer 327, and is composed of LaB6 and has a Schottky contact with the Schottky layer 327, and ohmic electrodes 340 are formed on the n+-type GaAs cap layer 328.
摘要翻译：一种半导体器件及其制造方法。半导体器件具有半绝缘GaAs衬底310，形成在半绝缘GaAs衬底310上的GaAs缓冲层321，AlGaAs缓冲层322，沟道层323，间隔层324，载流子供应层325，间隔层326，由未掺杂的In 0.48 Ga 0.52 P材料构成的肖特基层327和n + 栅电极330形成在肖特基层327上，由LaB 6构成，与肖特基层327具有肖特基接触，并且欧姆电极340形成在第n + +型GaAs覆盖层328。

7. 发明申请

US20060076585A1 Semiconductor resistor and method for manufacturing the same 审中-公开
标题翻译：半导体电阻及其制造方法
公开(公告)号：US20060076585A1
公开(公告)日：2006-04-13
申请号：US11234172
申请日：2005-09-26
申请人： Yoshiaki Kato , Yoshiharu Anda , Akiyoshi Tamura
发明人： Yoshiaki Kato , Yoshiharu Anda , Akiyoshi Tamura
IPC分类号： H01L31/112
CPC分类号： H01L27/0605 , H01L27/0629
摘要： An object of the present invention is to provide a semiconductor resistor that allows improvement in saturation voltage characteristics and a method for manufacturing the same. The semiconductor resistor of the present invention is formed on the substrate on which a GaAs FET is formed. The GaAs FET includes: a channel layer; a Schottky layer formed on the channel layer and made of undoped InGaP; and a contact layer formed on the Schottky layer. The semiconductor resistor includes: a contact layer including a part of the contact layer isolated from the GaAs FET; an active region including a part of the Schottky layer and a part of the channel layer, both of which are isolated from the GaAs FET; and two ohmic electrodes formed on the contact layer, and the Schottky layer isolated from the GaAs FET is exposed in an area between the two ohmic electrodes.
摘要翻译：本发明的一个目的是提供一种允许提高饱和电压特性的半导体电阻器及其制造方法。本发明的半导体电阻器形成在其上形成有GaAs FET的基板上。 GaAs FET包括：沟道层; 形成在沟道层上并由未掺杂的InGaP制成的肖特基层; 以及形成在肖特基层上的接触层。半导体电阻器包括：接触层，其包括与GaAs FET隔离的部分接触层; 包括肖特基层的一部分和沟道层的一部分的有源区域，两者都与GaAs FET隔离; 并且形成在接触层上的两个欧姆电极，并且从GaAs FET隔离的肖特基层暴露在两个欧姆电极之间的区域中。

8. 发明申请

US20050121695A1 Semiconductor device with Schottky electrode including lanthanum and boron, and manufacturing method thereof 有权
标题翻译：含有镧和硼的肖特基电极的半导体器件及其制造方法
公开(公告)号：US20050121695A1
公开(公告)日：2005-06-09
申请号：US11032164
申请日：2005-01-11
申请人： Yoshiharu Anda , Akiyoshi Tamura
发明人： Yoshiharu Anda , Akiyoshi Tamura
IPC分类号： H01L21/28 , H01L21/335 , H01L21/338 , H01L29/423 , H01L29/47 , H01L29/778 , H01L29/812 , H01L29/872 , H01L31/072 , H01L29/739
CPC分类号： H01L29/66462 , H01L29/475 , H01L29/7784
摘要： A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel layer 323, a spacer layer 324, a carrier supply layer 325, a spacer layer 326, a Schottky layer 327 composed of an undoped In0.48Ga0.52P material, and an n+-type GaAs cap layer 328. A gate electrode 330 is formed on the Schottky layer 327, and is composed of LaB6 and has a Schottky contact with the Schottky layer 327, and ohmic electrodes 340 are formed on the n+-type GaAs cap layer 328.
摘要翻译：一种半导体器件及其制造方法。半导体器件具有半绝缘GaAs衬底310，形成在半绝缘GaAs衬底310上的GaAs缓冲层321，AlGaAs缓冲层322，沟道层323，间隔层324，载流子供应层325，间隔层326，由未掺杂的In 0.48 Ga 0.52 P材料构成的肖特基层327和n + 栅电极330形成在肖特基层327上，由LaB 6构成，与肖特基层327具有肖特基接触，并且欧姆电极340形成在第n + +型GaAs覆盖层328。

9. 发明授权

US07495268B2 Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07495268B2
公开(公告)日：2009-02-24
申请号：US11757533
申请日：2007-06-04
申请人： Yoshiaki Kato , Yoshiharu Anda , Akiyoshi Tamura
发明人： Yoshiaki Kato , Yoshiharu Anda , Akiyoshi Tamura
IPC分类号： H01L29/812
CPC分类号： H01L29/8128 , H01L29/42316 , H01L29/66863 , H01L29/778
摘要： A semiconductor device according to the present invention includes: a semiconductor substrate; a channel layer formed on the semiconductor substrate; a donor layer formed on the channel layer; a first Schottky layer formed on the donor layer; a second Schottky layer formed on the first Schottky layer; a first gate electrode formed on the first Schottky layer to form a Schottky barrier junction with the first Schottky layer; a first source electrode and a first drain electrode formed so as to sandwich the first gate electrode and electrically connected to the channel layer; a second gate electrode formed on the second Schottky layer and made of a material different from the first gate electrode to form a Schottky barrier junction with the second Schottky layer; and a second source electrode and a second drain electrode formed so as to sandwich the second gate electrode and electrically connected to the channel layer.
摘要翻译：根据本发明的半导体器件包括：半导体衬底; 形成在所述半导体衬底上的沟道层; 在沟道层上形成的施主层; 形成在供体层上的第一肖特基层; 形成在第一肖特基层上的第二肖特基层; 形成在所述第一肖特基层上以与所述第一肖特基层形成肖特基势垒结的第一栅电极; 第一源电极和第一漏电极，其形成为夹着所述第一栅电极并电连接到所述沟道层; 第二栅电极，形成在所述第二肖特基层上，并且由与所述第一栅电极不同的材料制成，以与所述第二肖特基层形成肖特基势垒结; 以及第二源电极和第二漏电极，其形成为夹着所述第二栅极并电连接到所述沟道层。

10. 发明申请

US20060281237A1 METHOD OF MANUFACTURING JUNCTION FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：制造场效应晶体管的方法
公开(公告)号：US20060281237A1
公开(公告)日：2006-12-14
申请号：US11382991
申请日：2006-05-12
申请人： Akiyoshi Kudo , Yoshiharu Anda , Akiyoshi Tamura
发明人： Akiyoshi Kudo , Yoshiharu Anda , Akiyoshi Tamura
IPC分类号： H01L21/338
CPC分类号： H01L29/207 , H01L29/66924 , H01L29/808
摘要： A method of manufacturing a junction field-effect transistor which controls variations of p-type impurities in a gate region and obtains a favorable PN junction characteristic includes: depositing ZnO in a thin layer by a sputtering method on a surface of a region in which a gate electrode of an n+-AlGaAs layer formed on a GaAs substrate is to be formed; forming a p-type gate region by solid-phase diffusion which is performed by processes of rapid heating and fast cooling; removing the ZnO with wet etching using tartaric acid and the like so as to expose the p-type gate region; and forming the gate electrode on the exposed p-type gate region.
摘要翻译：一种控制栅极区域中的p型杂质的变化并获得良好的PN结特性的结型场效应晶体管的制造方法包括：在溅射法的薄层中，在要形成在GaAs衬底上形成的n + + / - AlGaAs层的栅电极; 通过快速加热和快速冷却过程进行的固相扩散形成p型栅极区; 用酒石酸等湿法蚀刻除去ZnO，露出p型栅区; 以及在暴露的p型栅极区上形成栅电极。

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