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1. 发明授权

US07989845B2 Semiconductor device having a hetero-junction bipolar transistor and manufacturing method thereof 有权
标题翻译：具有异质结双极晶体管的半导体器件及其制造方法
公开(公告)号：US07989845B2
公开(公告)日：2011-08-02
申请号：US12126395
申请日：2008-05-23
申请人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
发明人： Keiichi Murayama , Akiyoshi Tamura , Hirotaka Miyamoto , Kenichi Miyajima
IPC分类号： H01L31/0328
CPC分类号： H01L27/0605 , H01L21/8249 , H01L21/8252 , H01L27/0623
摘要： The object of the present invention is to provide a semiconductor device and the manufacturing method thereof which are capable of preventing decrease in the collector breakdown voltage and reducing the collector resistance. The semiconductor device according to the present invention includes: a HBT formed on a first region of a semiconductor substrate; and an HFET formed on a second region of the semiconductor substrate, wherein the HBT includes: an emitter layer of a first conductivity; a base layer of a second conductivity that has a band gap smaller than that of the emitter layer; a collector layer of the first conductivity or a non-doped collector layer; and a sub-collector layer of the first conductivity which are formed sequentially on the first region, and the HFET includes an electron donor layer including a part of the emitter layer, and a channel layer formed under the electron donor layer.
摘要翻译：本发明的目的是提供一种能够防止集电极击穿电压降低并且集电极电阻降低的半导体器件及其制造方法。根据本发明的半导体器件包括：形成在半导体衬底的第一区域上的HBT; 以及形成在所述半导体衬底的第二区域上的HFET，其中所述HBT包括：具有第一导电性的发射极层; 具有比发射极层的带隙小的带隙的第二导电性的基底层; 第一电导率的集电极层或非掺杂集电极层; 以及在第一区域上依次形成的第一导电性的副集电极层，并且HFET包括包含发射极层的一部分的电子供体层和形成在电子供体层下面的沟道层。

2. 发明申请

US20060237753A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060237753A1
公开(公告)日：2006-10-26
申请号：US11388545
申请日：2006-03-24
申请人： Yoshiharu Anda , Akiyoshi Tamura , Mitsuru Nishitsuji
发明人： Yoshiharu Anda , Akiyoshi Tamura , Mitsuru Nishitsuji
IPC分类号： H01L31/112
CPC分类号： H01L29/7784 , H01L21/28575 , H01L21/28587 , H01L29/66462
摘要： A field effect transistor according to the present invention includes a channel layer formed above a semi-insulating substrate, a Schottky layer formed above the channel layer, a gate electrode formed on the Schottky layer, Ohmic contact layers that are located above the Schottky layer with the gate electrode interposed therebetween and formed of InGaAs, and a source electrode and a drain electrode that are formed on the Ohmic contact layers. The source electrode, the drain electrode and the gate electrode have a layered structure in which their corresponding layers are formed of the same material, a lowermost layer is a WSi layer and a layer containing Al is provided above the lowermost layer. A field effect transistor that has an electrode resistance equivalent to a conventional level and can reduce a cost of manufacturing a field effect transistor and a method for manufacturing the same are provided.
摘要翻译：根据本发明的场效应晶体管包括形成在半绝缘衬底上的沟道层，形成在沟道层上方的肖特基层，形成在肖特基层上的栅电极，位于肖特基层上方的欧姆接触层，介于其间并由InGaAs形成的栅电极以及形成在欧姆接触层上的源电极和漏电极。源电极，漏电极和栅电极具有层叠结构，其相应的层由相同的材料形成，最下层是WSi层，并且在最下层上设置含有Al的层。提供具有等同于常规水平的电极电阻并且可以降低制造场效应晶体管的成本的场效应晶体管及其制造方法。

3. 发明授权

US06982141B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06982141B2
公开(公告)日：2006-01-03
申请号：US10937366
申请日：2004-09-10
申请人： Masanobu Nogome , Akiyoshi Tamura , Keiichi Murayama , Kazutsune Miyanaga , Yoshitaka Kuroishi
发明人： Masanobu Nogome , Akiyoshi Tamura , Keiichi Murayama , Kazutsune Miyanaga , Yoshitaka Kuroishi
IPC分类号： G03F7/00
CPC分类号： H01L21/76898 , H01L21/8252 , H01L23/481 , H01L27/0605 , H01L2924/0002 , Y10S430/136 , H01L2924/00
摘要： A GaAs substrate 200 is rotated, a photosensitive silicone resist 260 is applied on a surface of the GaAs substrate 200 on which an aperture of a hole 310 to be a via hole, and an inside of the hole 310 to be the via hole is filled in with the photosensitive silicone resist 260. Next, the GaAs substrate 200 is further rotated, changing the number of revolutions (rpm), and the photosensitive silicone resist 260 on the GaAs substrate is flattened. Next, a reverse side of the GaAs substrate is grinded, the hole 310 to be the via hole penetrates the GaAs substrate 200 from the surface to the reverse side and the via hole 220 is formed. Next, a reverse side electrode 240 is formed on the reverse side of the GaAs substrate 200. Next, the GaAs sustrate 200 is divided chip by chip and chips are laid on a substrate for assembly 270 via an adhesive metal 280.
摘要翻译：在GaAs衬底200旋转的同时，在GaAs衬底200的表面上施加感光性硅氧烷抗蚀剂260，在该衬底200的表面上填充孔310作为通孔的孔，填充孔310的内部与感光性硅氧烷抗蚀剂260接触。接着，进一步旋转GaAs衬底200，改变转速（rpm），使GaAs衬底上的感光性硅氧烷抗蚀剂260变平。接下来，研磨GaAs衬底的反面，作为通路孔的孔310从表面向反面侧穿过GaAs衬底200，形成通路孔220。接下来，在GaAs衬底200的相反侧上形成反向侧电极240.接下来，将GaAs衬垫200逐个分割，并且通过粘合金属280将芯片放置在用于组件270的衬底上。

4. 发明申请

US20050199910A1 Hetero-junction bipolar transistor and manufacturing method thereof 有权
公开(公告)号：US20050199910A1
公开(公告)日：2005-09-15
申请号：US11100511
申请日：2005-04-07
申请人： Keiichi Murayama , Akiyoshi Tamura , Masanobu Nogome
发明人： Keiichi Murayama , Akiyoshi Tamura , Masanobu Nogome
IPC分类号： H01L21/331 , H01L29/08 , H01L29/737 , H01L29/739 , H01L31/0328
CPC分类号： H01L29/0821 , H01L29/7371
摘要： A hetero-junction bipolar transistor that satisfies high resistance required to avoid a potential breakdown includes: an n-type sub-collector layer 110 that is made of GaAs; an n-type first collector 121 that is made of a semiconductor material with a smaller avalanche coefficient than that of the sub-collector 110 and is formed on the sub-collector layer 110; a second collector layer 132 that is made of n-type or i-type GaAs with lower dopant concentration than that of the sub-collector layer 110 and is formed on the first collector layer 121; a p-type base layer 133 that is made of GaAs and is formed on the second collector layer 132; and emitter layer 134 that is made of a semiconductor material with a larger band gap than that of the base layer 133 and is formed on the base layer 133.

5. 发明授权

US06380573B1 Semiconductor memory device and method for producing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06380573B1
公开(公告)日：2002-04-30
申请号：US09460062
申请日：1999-12-14
申请人： Akiyoshi Tamura
发明人： Akiyoshi Tamura
IPC分类号： H01L2976
CPC分类号： H01L21/28291 , H01L29/78391
摘要： A semiconductor memory device includes a semiconductor substrate having a channel therein; a gate insulating layer formed of a ferroelectric material provided on the semiconductor substrate; and a gate electrode provided on the gate insulating layer. The ferroelectric material includes a nitrogen (N) and at least one element selected from the group consisting of Mg, Sr, Ba and Ca.
摘要翻译：半导体存储器件包括其中具有通道的半导体衬底; 设置在所述半导体基板上的铁电体形成的栅极绝缘层; 以及设置在栅极绝缘层上的栅电极。铁电材料包括氮（N）和至少一种选自Mg，Sr，Ba和Ca的元素。

6. 发明申请

US20110250726A1 SEMICONDUCTOR DEVICE HAVING A HETERO-JUNCTION BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有异质结双极晶体管的半导体器件及其制造方法
公开(公告)号：US20110250726A1
公开(公告)日：2011-10-13
申请号：US13165889
申请日：2011-06-22
申请人： Keiichi MURAYAMA , Akiyoshi TAMURA , Kenichi MIYAJIMA
发明人： Keiichi MURAYAMA , Akiyoshi TAMURA , Kenichi MIYAJIMA
IPC分类号： H01L21/8248
CPC分类号： H01L27/0605 , H01L21/8249 , H01L21/8252 , H01L27/0623
摘要： Method for manufacturing a semiconductor device. A channel layer is formed by epitaxially growing a semiconductor layer, in which an ion species of a first conductivity is implanted on a semiconductor substrate. A source region, a drain region, and an emitter region which are of the first conductivity, are formed by activating, using annealing, a portion of the semiconductor substrate in which the ion species has been implanted. An emitter layer of the first conductivity, a base layer of a second conductivity having a band gap smaller than a band gap of the emitter layer, and a collector layer of the first conductivity or a non-doped collector layer are sequentially and epitaxially grown on the channel layer.
摘要翻译：半导体器件的制造方法通过外延生长半导体层形成沟道层，其中第一导电性的离子种类被注入到半导体衬底上。通过使用退火激活已经注入了离子种的半导体衬底的一部分来形成具有第一导电性的源极区，漏极区和发射极区。第一导电性的发射极层，具有小于发射极层的带隙的带隙的第二导电性的基底层和第一导电性或非掺杂的集电极层的集电极层依次并外延生长在通道层。

7. 发明申请

US20100187571A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100187571A1
公开(公告)日：2010-07-29
申请号：US12690296
申请日：2010-01-20
申请人： Kenichi MIYAJIMA , Akiyoshi TAMURA , Keiichi MURAYAMA
发明人： Kenichi MIYAJIMA , Akiyoshi TAMURA , Keiichi MURAYAMA
IPC分类号： H01L29/08 , H01L21/8222
CPC分类号： H01L29/7371 , H01L21/8252 , H01L27/0605 , H01L29/205 , H01L29/207 , H01L29/66242 , H01L29/66462 , H01L29/7783
摘要： An object of the present invention is to provide a semiconductor resistive element having excellent linearity. A semiconductor device according to the present invention includes a HBT which is formed on a GaAs substrate and includes a group III-V compound semiconductor, and a semiconductor resistive element made of at least one layer included in a semiconductor epitaxial layer included in the HBT, and the semiconductor resistive element includes helium impurities.
摘要翻译：本发明的目的是提供具有优异线性的半导体电阻元件。根据本发明的半导体器件包括HBT，其形成在GaAs衬底上并且包括III-V族化合物半导体，以及由包括在HBT中的包括在半导体外延层中的至少一层制成的半导体电阻元件，并且半导体电阻元件包括氦杂质。

8. 发明申请

US20090230431A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090230431A1
公开(公告)日：2009-09-17
申请号：US12400376
申请日：2009-03-09
申请人： Keiichi MURAYAMA , Akiyoshi TAMURA , Hirotaka MIYAMOTO , Kenichi MIYAJIMA
发明人： Keiichi MURAYAMA , Akiyoshi TAMURA , Hirotaka MIYAMOTO , Kenichi MIYAJIMA
IPC分类号： H01L27/06 , H01L21/331
CPC分类号： H01L27/0623 , H01L21/8248 , H01L27/0605 , H01L29/7371 , H01L29/802
摘要： The present invention has as an objective to provide: a semiconductor device to satisfy both of the trade-off characteristic advantages of the HBT; and the HFET and a manufacturing method thereof. The semiconductor device in the present invention is an HBT and HFET integrated circuit. The HBT includes a sub-collector layer, a GaAs collector layer, a GaAs base layer, and an InGaP emitter layer which are sequentially stacked. The sub-collector layer includes a GaAs external sub-collector region, and a GaAs internal sub-collector region disposed on the GaAs external sub-collector region. A mesa-shaped collector part and a collector electrode are separately formed on the GaAs external sub-collector region. The HFET includes a GaAs cap layer, a source electrode, and a drain electrode, the GaAs cap layer including portion of the GaAs external sub-collector region, and the source electrode and the drain electrode being formed on the GaAs cap layer.
摘要翻译：本发明的目的是提供一种半导体装置，以满足HBT的两个折衷特征优点; 和HFET及其制造方法。本发明的半导体器件是HBT和HFET集成电路。 HBT包括依次层叠的副集电极层，GaAs集电极层，GaAs基极层和InGaP发射极层。子集电极层包括GaAs外部副集电极区域和设置在GaAs外部子集电极区域上的GaAs内部子集电极区域。在GaAs外部副集电极区域上分别形成台状集电体部和集电极。 HFET包括GaAs覆盖层，源电极和漏电极，GaAs覆盖层包括GaAs外部副集电极区域的一部分，源电极和漏电极形成在GaAs覆盖层上。

9. 发明授权

US07495268B2 Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07495268B2
公开(公告)日：2009-02-24
申请号：US11757533
申请日：2007-06-04
申请人： Yoshiaki Kato , Yoshiharu Anda , Akiyoshi Tamura
发明人： Yoshiaki Kato , Yoshiharu Anda , Akiyoshi Tamura
IPC分类号： H01L29/812
CPC分类号： H01L29/8128 , H01L29/42316 , H01L29/66863 , H01L29/778
摘要： A semiconductor device according to the present invention includes: a semiconductor substrate; a channel layer formed on the semiconductor substrate; a donor layer formed on the channel layer; a first Schottky layer formed on the donor layer; a second Schottky layer formed on the first Schottky layer; a first gate electrode formed on the first Schottky layer to form a Schottky barrier junction with the first Schottky layer; a first source electrode and a first drain electrode formed so as to sandwich the first gate electrode and electrically connected to the channel layer; a second gate electrode formed on the second Schottky layer and made of a material different from the first gate electrode to form a Schottky barrier junction with the second Schottky layer; and a second source electrode and a second drain electrode formed so as to sandwich the second gate electrode and electrically connected to the channel layer.
摘要翻译：根据本发明的半导体器件包括：半导体衬底; 形成在所述半导体衬底上的沟道层; 在沟道层上形成的施主层; 形成在供体层上的第一肖特基层; 形成在第一肖特基层上的第二肖特基层; 形成在所述第一肖特基层上以与所述第一肖特基层形成肖特基势垒结的第一栅电极; 第一源电极和第一漏电极，其形成为夹着所述第一栅电极并电连接到所述沟道层; 第二栅电极，形成在所述第二肖特基层上，并且由与所述第一栅电极不同的材料制成，以与所述第二肖特基层形成肖特基势垒结; 以及第二源电极和第二漏电极，其形成为夹着所述第二栅极并电连接到所述沟道层。

10. 发明申请

US20060281237A1 METHOD OF MANUFACTURING JUNCTION FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：制造场效应晶体管的方法
公开(公告)号：US20060281237A1
公开(公告)日：2006-12-14
申请号：US11382991
申请日：2006-05-12
申请人： Akiyoshi Kudo , Yoshiharu Anda , Akiyoshi Tamura
发明人： Akiyoshi Kudo , Yoshiharu Anda , Akiyoshi Tamura
IPC分类号： H01L21/338
CPC分类号： H01L29/207 , H01L29/66924 , H01L29/808
摘要： A method of manufacturing a junction field-effect transistor which controls variations of p-type impurities in a gate region and obtains a favorable PN junction characteristic includes: depositing ZnO in a thin layer by a sputtering method on a surface of a region in which a gate electrode of an n+-AlGaAs layer formed on a GaAs substrate is to be formed; forming a p-type gate region by solid-phase diffusion which is performed by processes of rapid heating and fast cooling; removing the ZnO with wet etching using tartaric acid and the like so as to expose the p-type gate region; and forming the gate electrode on the exposed p-type gate region.
摘要翻译：一种控制栅极区域中的p型杂质的变化并获得良好的PN结特性的结型场效应晶体管的制造方法包括：在溅射法的薄层中，在要形成在GaAs衬底上形成的n + + / - AlGaAs层的栅电极; 通过快速加热和快速冷却过程进行的固相扩散形成p型栅极区; 用酒石酸等湿法蚀刻除去ZnO，露出p型栅区; 以及在暴露的p型栅极区上形成栅电极。

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