专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4426680A Data processor using read only memories for optimizing main memory access and identifying the starting position of an operand 失效
标题翻译：数据处理器使用只读存储器来优化主存储器访问并识别操作数的起始位置
公开(公告)号：US4426680A
公开(公告)日：1984-01-17
申请号：US219809
申请日：1980-12-24
申请人： Steven A. Tague , Virendra S. Negi
发明人： Steven A. Tague , Virendra S. Negi
IPC分类号： G06F7/00 , G06F7/76 , G06F9/22 , G06F7/38
CPC分类号： G06F9/226
摘要： A data processing system which includes a commercial instruction processor for executing decimal alphanumeric instructions uses read only memories in the alignment of the operands. The characteristics of the operands, string or packed decimal, as well as the length and position of the most significant decimal digit in a main memory word, are specified by data descriptors. The read only memories are responsive to the data descriptor information as well as the instruction being executed to generate signals which specify whether the direction words are read from main memory, high order word first or low order word first, the number of double words in the operand and the location of the least or most significant decimal digit within the word as stored in registers of the commercial instruction processor.
摘要翻译：包括用于执行十进制字母数字指令的商业指令处理器的数据处理系统在操作数的对齐中使用只读存储器。操作数，字符串或压缩十进制的特征以及主存储器字中最重要的十进制数字的长度和位置由数据描述符指定。只读存储器响应于数据描述符信息以及正在执行的指令，以产生指定从主存储器读取方向字，高位字首先还是低位字首先被读取的信号，操作数和存储在商业指令处理器的寄存器中的单词内最小或最重要的十进制数字的位置。

2. 发明授权

US4390961A Data processor performing a decimal multiply operation using a read only memory 失效
标题翻译：数据处理器使用只读存储器执行十进制乘法运算
公开(公告)号：US4390961A
公开(公告)日：1983-06-28
申请号：US220218
申请日：1980-12-24
申请人： Virendra S. Negi , Steven A. Tague
发明人： Virendra S. Negi , Steven A. Tague
IPC分类号： G06F7/483 , G06F7/491 , G06F7/496 , G06F7/508 , G06F7/52 , G06F7/523 , G06F7/527
CPC分类号： G06F7/4915
摘要： A data processor performs a decimal multiply operation using apparatus including a register for storing multiplier decimal digits, a register for storing a multiplicand operand of decimal digits, a register for storing partial products and arithmetic logic units, and a read only memory for storing the units and tens product digits. The multiplier digit and a selected multiplicand digit are applied to the address terminals of the read only memory. On successive cycles, the units product digit and the tens product digit are added respectively to selected partial product digits and the sum replaces the selected partial product digits.
摘要翻译：数据处理器使用包括用于存储乘法器十进制数字的寄存器，用于存储小数位的被乘数操作数的寄存器，用于存储部分乘积的寄存器和算术逻辑单元的装置以及用于存储单位的只读存储器来执行十进制乘法运算和十个商品数字。乘数和选择的被乘数被施加到只读存储器的地址端。在连续循环中，单位产品数字和十位产品数字分别添加到选定的部分产品数字，并且和代替了所选择的部分产品数字。

3. 发明授权

US4384343A Firmware controlled search and verify apparatus and method for a data processing system 失效
标题翻译：用于数据处理系统的固件控制搜索和验证装置和方法
公开(公告)号：US4384343A
公开(公告)日：1983-05-17
申请号：US308782
申请日：1981-10-05
申请人： Victor M. Morganti , Virendra S. Negi , Michael J. D. Graesser
发明人： Victor M. Morganti , Virendra S. Negi , Michael J. D. Graesser
IPC分类号： G06F17/30 , G06F7/04
CPC分类号： G06F17/30982 , Y10S707/99933
摘要： An alphanumeric search apparatus wherein a plurality of search indicia stored in a first operand and a plurality of elements stored in a second operand are operated upon by a data processing system to determine by means of search or verify operations whether any of the elements included in the second operand correspond to any one of the indicia included in the first operand. The second operand may be arranged in a sequential string of elements or in an array or table of elements and a search is conducted by comparing each element sequentially with all the search indicia and by so processing the elements until a match is found. A verify procedure is conducted by comparing each element with the search indicia to verify that there is a counterpart for each search element in the list of search indicia. For a search procedure, an output is generated indicating the storage locations within their respective operands of the search indicia and the element which produced the match. For a verify procedure an output is generated indicating the first storage location of a search element that is not included in the list of search indicia.
摘要翻译：一种字母数字搜索装置，其中存储在第一操作数中的多个搜索标记和存储在第二操作数中的多个元素由数据处理系统进行操作，以通过搜索或验证操作来确定是否包括在第二操作数对应于包括在第一操作数中的任何一个标记。第二操作数可以被排列成元素的顺序串或元素的数组或表格，并且通过将每个元素与所有搜索标记进行顺序比较，并且通过如此处理元素直到找到匹配来进行搜索。通过将每个元素与搜索标记进行比较来验证验证过程，以验证搜索标记列表中每个搜索元素的对应物。对于搜索过程，产生指示搜索标记的相应操作数内的存储位置和产生匹配的元素的输出。对于验证过程，生成指示搜索元素的未包括在搜索标记列表中的第一存储位置的输出。

4. 发明授权

US4384341A Data processor having carry apparatus supporting a decimal divide operation 失效
标题翻译：具有支持小数除法运算的进位装置的数据处理器
公开(公告)号：US4384341A
公开(公告)日：1983-05-17
申请号：US219638
申请日：1980-12-24
申请人： Steven A. Tague , Virendra S. Negi
发明人： Steven A. Tague , Virendra S. Negi
IPC分类号： G06F7/496 , G06F7/483 , G06F7/491 , G06F7/493 , G06F7/508 , G06F7/52 , G06F7/533
CPC分类号： G06F7/4917
摘要： A commercial instruction processor executes a decimal divide instruction by counting the number of subtractions by the divisor resulting in a positive remainder to develop the quotient. Apparatus compares the most significant decimal digit of the divisor with the most significant decimal digit of the remainder after each subtraction pass to predict if the next subtraction pass would result in a negative remainder. If so, a quotient decimal digit is stored in a memory, the divisor is shifted one decimal digit position to the right, and a series of subtraction passes are made to develop the next quotient decimal digit.
摘要翻译：商业指令处理器通过对由除数产生的正数余数进行计数来执行十进制除法指令来开发商。设备将除数的最有意义的十进制数与每次减法通过后余数中最有效的十进制数进行比较，以预测下一个减法通过是否会导致负余数。如果是这样的话，一个商数十进制数存储在一个存储器中，除数将一个十进制数位置向右移位，并进行一系列的减法遍数来形成下一个十进制数字。

5. 发明授权

US4322846A Self-evaluation system for determining the operational integrity of a data processing system 失效
标题翻译：用于确定数据处理系统的操作完整性的自我评估系统
公开(公告)号：US4322846A
公开(公告)日：1982-03-30
申请号：US140621
申请日：1980-04-15
申请人： Elmer W. Carroll , Virendra S. Negi , Arthur Peters
发明人： Elmer W. Carroll , Virendra S. Negi , Arthur Peters
IPC分类号： G06F11/22 , G06F11/273 , G06F11/32 , G06F11/00
CPC分类号： G06F11/2736 , G06F11/22 , G06F11/32
摘要： In a data processing system, a self-diagnosing system selectively initiates the operation of subprocessing units in the data processing system in a predetermined sequence to determine whether the subprocessing units are operating correctly. A control store stores a plurality of sequences of control data which are selectively accessed to control the operation of the subprocessing units to perform self-diagnosing error tests. A display unit displays an indication of which of the sequences of control data is currently controlling the operation of the subprocessing units in order to aid error diagnosis should an error be discovered during the operation of the self-diagnosing system.
摘要翻译：在数据处理系统中，自诊断系统以预定的顺序选择性地启动数据处理系统中的子处理单元的操作，以确定子处理单元是否正确地操作。控制存储器存储多个控制数据序列，其被选择性地访问以控制子处理单元的操作以执行自诊断错误测试。显示单元显示控制数据序列当前正在控制子处理单元的操作的指示，以便在自诊断系统的操作期间应该发现错误时帮助错误诊断。

6. 发明授权

US4245328A Binary coded decimal correction apparatus for use in an arithmetic unit of a data processing unit 失效
标题翻译：二进制编码十进制校正装置，用于数据处理单元的算术单元
公开(公告)号：US4245328A
公开(公告)日：1981-01-13
申请号：US735
申请日：1979-01-03
申请人： Virendra S. Negi , Arthur Peters
发明人： Virendra S. Negi , Arthur Peters
IPC分类号： G06F7/494 , G06F7/50 , G06F7/508 , H03M7/12
CPC分类号： G06F7/494 , G06F2207/4921
摘要： Binary coded decimal operands may be operated on by use of a binary arithmetic logic unit and the result corrected to provide a binary coded decimal result by use of correction logic which is responsive to the result produced by the binary arithmetic logic unit, the type of operation being performed and whether the binary arithmetic logic unit produced a carry as a result of its arithmetic operation on such operands.
摘要翻译：二进制编码十进制操作数可以通过使用二进制算术逻辑单元进行操作，并且校正结果以通过使用校正逻辑来提供二进制编码的十进制结果，校正逻辑响应于二进制运算逻辑单元产生的结果，操作类型并且二进制运算逻辑单元是否作为其对这些操作数的算术运算的结果产生进位。

7. 发明授权

US4667288A Enable/disable control checking apparatus 失效
标题翻译：启用/禁用控制检查装置
公开(公告)号：US4667288A
公开(公告)日：1987-05-19
申请号：US509898
申请日：1983-06-30
申请人： James W. Keeley , Robert V. Ledoux , Virendra S. Negi
发明人： James W. Keeley , Robert V. Ledoux , Virendra S. Negi
IPC分类号： G06F11/07 , G06F11/10 , G06F11/22 , G06F12/00 , G06F12/12 , G11C29/00
CPC分类号： G11C29/88 , G06F11/073 , G06F11/0772 , G06F11/2289 , G06F12/126 , G06F11/10 , G06F12/00 , G06F2212/1032
摘要： A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test control apparatus which couples to the directory error checking apparatus operates to selectively enable and disable the directory error checking circuits in response to commands received from a central processing unit so as to enable the testing of the cache directory and other portions of the cache system using common test routines.
摘要翻译：其目录和高速缓存存储器被组织到存储器位置的级别的多级组关联缓存系统包括控制装置，其响应于来自目录错误检查电路的错误信号而选择性地降级高速缓存操作到被检测为没有错误的那些级别。耦合到目录错误检查装置的测试控制装置操作以响应于从中央处理单元接收的命令选择性地启用和禁用目录错误检查电路，以便能够使用高速缓存系统的高速缓存目录和其他部分的测试常用测试程序。

8. 发明授权

US4462072A Clock system having a stall capability to enable processing of errors 失效
标题翻译：具有能够处理错误的失速能力的时钟系统
公开(公告)号：US4462072A
公开(公告)日：1984-07-24
申请号：US250810
申请日：1981-04-03
申请人： Steven A. Tague , Virendra S. Negi
发明人： Steven A. Tague , Virendra S. Negi
IPC分类号： G06F1/08 , G06F11/07 , G06F7/00 , G06F11/00
CPC分类号： G06F11/073 , G06F1/08 , G06F11/0721 , G06F11/0793
摘要： A microprogrammed commercial instruction processor (CIP) is placed in a stall mode during the transfer of information between the CIP and main memory by stalling a free running clock signal. When the transfer of information is completed, the free running clock cycles. If main memory indicates an error condition, then the free running clock signal is again stalled after one cycle to allow the firmware in the CIP to process the error.
摘要翻译：通过停止自由运行的时钟信号，在CIP和主存储器之间的信息传送期间，微程序商业指令处理器（CIP）被置于停止模式。当信息传输完成时，自由运行的时钟周期。如果主存储器指示错误状况，则自由运行的时钟信号在一个周期后再次停止，以允许CIP中的固件处理该错误。

9. 发明授权

US4271484A Condition code accumulator apparatus for a data processing system 失效
标题翻译：用于数据处理系统的条件代码累加器装置
公开(公告)号：US4271484A
公开(公告)日：1981-06-02
申请号：US841
申请日：1979-01-03
申请人： Arthur Peters , Virendra S. Negi
发明人： Arthur Peters , Virendra S. Negi
IPC分类号： G06F9/32 , G06F9/38 , G06F11/30
CPC分类号： G06F9/3885 , G06F11/302 , G06F11/3093 , G06F9/30058 , G06F9/30094
摘要： Signals representing the past and present states of a condition under test during an instruction execution cycle, as well as a signal indicating that an execute cycle has taken place, are utilized as address signals applied to a memory which feeds an output to control a bistable element. The bistable element is set to the state of the memory output signal and supplies the address signal indicative of the past state of the condition under test. The memory is coded to respond at its output with signals controlling the bistable element such that once a given state of the condition under test is detected and stored in the bistable element, the latter is inhibited from switching regardless of any further changes in the condition under test during the current instruction execution cycle.
摘要翻译：在指令执行周期期间表示被测状态的过去和现在状态的信号以及表示执行周期的信号被用作施加到存储器的地址信号，所述存储器馈送输出以控制双稳态元件。双稳态元件设置为存储器输出信号的状态，并提供表示被测状态的过去状态的地址信号。存储器被编码以在其输出处响应控制双稳态元件的信号，使得一旦检测到被测状态的给定状态并将其存储在双稳态元件中，则后者被禁止切换，而不管条件下的任何进一步变化如何在当前指令执行周期内进行测试。

10. 发明授权

US4224668A Control store address generation logic for a data processing system 失效
标题翻译：用于数据处理系统的控制存储地址生成逻辑
公开(公告)号：US4224668A
公开(公告)日：1980-09-23
申请号：US864
申请日：1979-01-03
申请人： Arthur Peters , Virendra S. Negi
发明人： Arthur Peters , Virendra S. Negi
IPC分类号： G06F9/42 , G06F9/20
CPC分类号： G06F9/4426
摘要： A control store in a data processor is addressed by means of next address generation logic which includes a first multiplexer utilized to address the control store, which multiplexer has several inputs. One of such inputs is received from a latching mechanism which allows more than one test condition to be simultaneously utilized for addressing the control store on a free flow basis. These test conditions, as well as information from an addressed control word, are utilized in a multiplexed arrangement as one input of the first multiplexer. By use of other inputs of such first multiplexer, the control store may be addressed by use of branch address information, as well as other test condition information. A page register provides the page address, to a plurality of pages included in this control store with the locations in each such page addressed by use of the above noted multiplexer combination.
摘要翻译：数据处理器中的控制存储器通过下一个地址生成逻辑来寻址，该地址生成逻辑包括用于寻址控制存储器的第一多路复用器，该多路复用器具有多个输入。从锁定机构接收这样的输入之一，其允许同时利用多于一个的测试条件来以自由流为基础对控制存储器进行寻址。这些测试条件以及来自寻址的控制字的信息以多路复用方式用作第一多路复用器的一个输入。通过使用这种第一多路复用器的其他输入，可以通过使用分支地址信息以及其他测试条件信息来寻址控制存储器。页面寄存器将页面地址提供给包含在该控制存储器中的多个页面，其中通过使用上述复用器组合寻址每个这样的页面中的位置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式