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1. 发明授权

US4323967A Local bus interface for controlling information transfers between units in a central subsystem 失效
标题翻译：用于控制中央子系统中单元之间的信息传输的本地总线接口
公开(公告)号：US4323967A
公开(公告)日：1982-04-06
申请号：US140622
申请日：1980-04-15
申请人： Arthur Peters , Virendra S. Negi , David E. Cushing , Richard P. Brown , Thomas F. Joyce
发明人： Arthur Peters , Virendra S. Negi , David E. Cushing , Richard P. Brown , Thomas F. Joyce
IPC分类号： G06F9/46 , G06F12/08 , G06F13/36 , G06F13/364 , G06F13/40 , G06F3/00
CPC分类号： G06F13/364 , G06F12/084 , G06F13/4059
摘要： In a data processing system, a central subsystem includes a plurality of special purpose processing units with one of the processing units serving as a control processing unit within a central subsystem. The processing units are coupled to a common subsystem bus for the transfer of data, control information, and address information within the central subsystem. Access to the subsystem bus is allocated by a bus control unit which also interfaces the central subsystem with other processing units such as a system memory or system I/O devices that are included in the data processing system.
摘要翻译：在数据处理系统中，中央子系统包括多个专用处理单元，其中一个处理单元用作中央子系统内的控制处理单元。处理单元耦合到公共子系统总线，用于在中央子系统内传送数据，控制信息和地址信息。子系统总线的访问由总线控制单元分配，总线控制单元还将中央子系统与诸如包括在数据处理系统中的系统存储器或系统I / O设备的其他处理单元接口。

2. 发明授权

US4271484A Condition code accumulator apparatus for a data processing system 失效
标题翻译：用于数据处理系统的条件代码累加器装置
公开(公告)号：US4271484A
公开(公告)日：1981-06-02
申请号：US841
申请日：1979-01-03
申请人： Arthur Peters , Virendra S. Negi
发明人： Arthur Peters , Virendra S. Negi
IPC分类号： G06F9/32 , G06F9/38 , G06F11/30
CPC分类号： G06F9/3885 , G06F11/302 , G06F11/3093 , G06F9/30058 , G06F9/30094
摘要： Signals representing the past and present states of a condition under test during an instruction execution cycle, as well as a signal indicating that an execute cycle has taken place, are utilized as address signals applied to a memory which feeds an output to control a bistable element. The bistable element is set to the state of the memory output signal and supplies the address signal indicative of the past state of the condition under test. The memory is coded to respond at its output with signals controlling the bistable element such that once a given state of the condition under test is detected and stored in the bistable element, the latter is inhibited from switching regardless of any further changes in the condition under test during the current instruction execution cycle.
摘要翻译：在指令执行周期期间表示被测状态的过去和现在状态的信号以及表示执行周期的信号被用作施加到存储器的地址信号，所述存储器馈送输出以控制双稳态元件。双稳态元件设置为存储器输出信号的状态，并提供表示被测状态的过去状态的地址信号。存储器被编码以在其输出处响应控制双稳态元件的信号，使得一旦检测到被测状态的给定状态并将其存储在双稳态元件中，则后者被禁止切换，而不管条件下的任何进一步变化如何在当前指令执行周期内进行测试。

3. 发明授权

US4224668A Control store address generation logic for a data processing system 失效
标题翻译：用于数据处理系统的控制存储地址生成逻辑
公开(公告)号：US4224668A
公开(公告)日：1980-09-23
申请号：US864
申请日：1979-01-03
申请人： Arthur Peters , Virendra S. Negi
发明人： Arthur Peters , Virendra S. Negi
IPC分类号： G06F9/42 , G06F9/20
CPC分类号： G06F9/4426
摘要： A control store in a data processor is addressed by means of next address generation logic which includes a first multiplexer utilized to address the control store, which multiplexer has several inputs. One of such inputs is received from a latching mechanism which allows more than one test condition to be simultaneously utilized for addressing the control store on a free flow basis. These test conditions, as well as information from an addressed control word, are utilized in a multiplexed arrangement as one input of the first multiplexer. By use of other inputs of such first multiplexer, the control store may be addressed by use of branch address information, as well as other test condition information. A page register provides the page address, to a plurality of pages included in this control store with the locations in each such page addressed by use of the above noted multiplexer combination.
摘要翻译：数据处理器中的控制存储器通过下一个地址生成逻辑来寻址，该地址生成逻辑包括用于寻址控制存储器的第一多路复用器，该多路复用器具有多个输入。从锁定机构接收这样的输入之一，其允许同时利用多于一个的测试条件来以自由流为基础对控制存储器进行寻址。这些测试条件以及来自寻址的控制字的信息以多路复用方式用作第一多路复用器的一个输入。通过使用这种第一多路复用器的其他输入，可以通过使用分支地址信息以及其他测试条件信息来寻址控制存储器。页面寄存器将页面地址提供给包含在该控制存储器中的多个页面，其中通过使用上述复用器组合寻址每个这样的页面中的位置。

4. 发明授权

US4272828A Arithmetic logic apparatus for a data processing system 失效
标题翻译：一种用于数据处理系统的算术逻辑装置
公开(公告)号：US4272828A
公开(公告)日：1981-06-09
申请号：US842
申请日：1979-01-03
申请人： Virendra S. Negi , Arthur Peters
发明人： Virendra S. Negi , Arthur Peters
IPC分类号： G06F7/57 , G06F12/04 , G06F7/50
CPC分类号： G06F7/57 , G06F12/04
摘要： Arithmetic logic apparatus having two independent register files, one for each operand. Each register file has also associated therewith independently controlled incrementing and/or decrementing address mechanisms. Each such register file is coupled for addressing on a digit, byte or word basis. Operation of such apparatus is under the control of control instructions received from a control store included in a data processor in which such apparatus is also included.
摘要翻译：具有两个独立寄存器文件的算术逻辑设备，每个操作数一个。每个寄存器文件也与其独立控制的递增和/或递减地址机制相关联。每个这样的寄存器文件被耦合用于以数字，字节或字为基础进行寻址。这种装置的操作在从包括在其中也包括这种装置的数据处理器中的控制存储器接收的控制指令的控制下。

5. 发明授权

US4258420A Control file apparatus for a data processing system 失效
标题翻译：用于数据处理系统的控制文件装置
公开(公告)号：US4258420A
公开(公告)日：1981-03-24
申请号：US733
申请日：1979-01-03
申请人： Virendra S. Negi , Arthur Peters
发明人： Virendra S. Negi , Arthur Peters
IPC分类号： G06F15/16 , G06F9/38 , G06F15/167 , G06F15/80
CPC分类号： G06F9/3877 , G06F15/8007 , G06F9/3879
摘要： Information from a main data processor is transferred to an auxiliary data processor of the system and is stored in a control file which may be addressed by either a firmware word from a control store or by use of the function code received in an instruction from the main processor. Information in such control file is used for the purpose of addressing main memory. The address for main memory may be incremented or decremented simultaneously as operands are being fetched from main memory for execution.
摘要翻译：来自主数据处理器的信息被传送到系统的辅助数据处理器，并且被存储在控制文件中，该控制文件可以通过来自控制存储器的固件字来寻址或者通过使用在主指令中接收的功能码处理器。这种控制文件中的信息用于寻址主存储器。当从主存储器中取出操作数进行执行时，主存储器的地址可以同时递增或递减。

6. 发明授权

US4322846A Self-evaluation system for determining the operational integrity of a data processing system 失效
标题翻译：用于确定数据处理系统的操作完整性的自我评估系统
公开(公告)号：US4322846A
公开(公告)日：1982-03-30
申请号：US140621
申请日：1980-04-15
申请人： Elmer W. Carroll , Virendra S. Negi , Arthur Peters
发明人： Elmer W. Carroll , Virendra S. Negi , Arthur Peters
IPC分类号： G06F11/22 , G06F11/273 , G06F11/32 , G06F11/00
CPC分类号： G06F11/2736 , G06F11/22 , G06F11/32
摘要： In a data processing system, a self-diagnosing system selectively initiates the operation of subprocessing units in the data processing system in a predetermined sequence to determine whether the subprocessing units are operating correctly. A control store stores a plurality of sequences of control data which are selectively accessed to control the operation of the subprocessing units to perform self-diagnosing error tests. A display unit displays an indication of which of the sequences of control data is currently controlling the operation of the subprocessing units in order to aid error diagnosis should an error be discovered during the operation of the self-diagnosing system.
摘要翻译：在数据处理系统中，自诊断系统以预定的顺序选择性地启动数据处理系统中的子处理单元的操作，以确定子处理单元是否正确地操作。控制存储器存储多个控制数据序列，其被选择性地访问以控制子处理单元的操作以执行自诊断错误测试。显示单元显示控制数据序列当前正在控制子处理单元的操作的指示，以便在自诊断系统的操作期间应该发现错误时帮助错误诊断。

7. 发明授权

US4245328A Binary coded decimal correction apparatus for use in an arithmetic unit of a data processing unit 失效
标题翻译：二进制编码十进制校正装置，用于数据处理单元的算术单元
公开(公告)号：US4245328A
公开(公告)日：1981-01-13
申请号：US735
申请日：1979-01-03
申请人： Virendra S. Negi , Arthur Peters
发明人： Virendra S. Negi , Arthur Peters
IPC分类号： G06F7/494 , G06F7/50 , G06F7/508 , H03M7/12
CPC分类号： G06F7/494 , G06F2207/4921
摘要： Binary coded decimal operands may be operated on by use of a binary arithmetic logic unit and the result corrected to provide a binary coded decimal result by use of correction logic which is responsive to the result produced by the binary arithmetic logic unit, the type of operation being performed and whether the binary arithmetic logic unit produced a carry as a result of its arithmetic operation on such operands.
摘要翻译：二进制编码十进制操作数可以通过使用二进制算术逻辑单元进行操作，并且校正结果以通过使用校正逻辑来提供二进制编码的十进制结果，校正逻辑响应于二进制运算逻辑单元产生的结果，操作类型并且二进制运算逻辑单元是否作为其对这些操作数的算术运算的结果产生进位。

8. 发明授权

US4309753A Apparatus and method for next address generation in a data processing system 失效
标题翻译：在数据处理系统中下一个地址产生的装置和方法
公开(公告)号：US4309753A
公开(公告)日：1982-01-05
申请号：US000734
申请日：1979-01-03
申请人： Virendra S. Negi , Arthur Peters
发明人： Virendra S. Negi , Arthur Peters
IPC分类号： G06F9/26 , G06F9/22 , G06F9/42
CPC分类号： G06F9/4426
摘要： A data processing system having a control store storing firmware words for controlling the system, logic for executing logical operations on input data, including the performing of a first and second data processing routine, and apparatus for addressing the control store to access selected firmware words to control the execution of desired logical operations on the input data. The system operates in a particular mode of control to suspend the operation of the first routine in order to execute the second routine whereby the logical apparatus includes a register for saving a return address associated with the last instruction of the first routine. When the system terminates the second routine and restores the first routine to operation, the contents of the save register are employed, with the lowest order bit thereof inverted, to access the control store to fetch the firmware word used to reenter the first routine.
摘要翻译：一种数据处理系统，具有存储用于控制系统的固件字的控制存储器，用于执行对输入数据的逻辑运算的逻辑，包括执行第一和第二数据处理程序，以及用于寻址控制存储以访问所选择的固件字的装置控制对输入数据的所需逻辑运算的执行。系统以特定控制模式操作以暂停第一例程的操作，以便执行第二程序，由此逻辑设备包括用于保存与第一程序的最后指令相关联的返回地址的寄存器。当系统终止第二程序并恢复第一程序进行操作时，采用存储寄存器的内容，其最低位被反转，以访问控制存储器以获取用于重新进入第一程序的固件字。

9. 发明授权

US4484300A Data processor having units carry and tens carry apparatus supporting a decimal multiply operation 失效
标题翻译：具有单元的数据处理器进位和十进位装置支持十进制乘法运算
公开(公告)号：US4484300A
公开(公告)日：1984-11-20
申请号：US219810
申请日：1980-12-24
申请人： Virendra S. Negi , Steven A. Tague
发明人： Virendra S. Negi , Steven A. Tague
IPC分类号： G06F7/38 , G06F7/483 , G06F7/491 , G06F7/496 , G06F7/508 , G06F7/52 , G06F7/527
CPC分类号： G06F7/4915
摘要： A data processing system executes a decimal multiply instruction by storing the product of a multiplier decimal digit and a multiplicand decimal digit in a read only memory and storing partial product decimal digits in a register. The units product decimal digit is read from the read only memory during one cycle and added to a partial product decimal digit. A resulting units carry is stored in a units carry flip-flop. The tens product decimal digit is read from the read only memory during another cycle and added to a higher order partial product decimal digit. A resulting tens carry is stored in a tens carry flip-flop. A multiplexer selects the output of the units carry flip-flop for adding the units carry during the next units cycle in which the next units product decimal digit is added to the higher order partial product decimal digit. The multiplexer selects the output of the tens carry flip-flop for adding the tens carry during the next tens cycle in which the next tens product decimal digit is added to a next higher order partial product decimal digit.
摘要翻译：数据处理系统通过将乘数十进制数和乘数十进制数的乘积存储在只读存储器中并将部分乘积十进制数字存储在寄存器中来执行十进制乘法指令。单位产品十进制数字在一个周期内从只读存储器读取，并添加到部分乘积十进制数字。结果单位进位存储在单位进位触发器中。在另一个周期内，从只读存储器读取十位数十进制数，并将其加到较高阶部分乘积十进制数字。结果十进位存储在十进位触发器中。多路复用器在下一个单位周期内，将下一个单位乘积十进制数字加到较高阶部分乘积十进制数字中，选择输入单元的单元进位触发器来添加单位进位。多路复用器选择十位进位触发器的输出，在下一个十位周期中将下一个十位乘数十进制数字加到下一个高阶部分乘积十进制数字的十进位。

10. 发明授权

US4410984A Diagnostic testing of the data path in a microprogrammed data processor 失效
标题翻译：在微程序数据处理器中对数据路径进行诊断测试
公开(公告)号：US4410984A
公开(公告)日：1983-10-18
申请号：US250820
申请日：1981-04-03
申请人： Virendra S. Negi , Steven A. Tague
发明人： Virendra S. Negi , Steven A. Tague
IPC分类号： G06F11/267 , G06F11/00
CPC分类号： G06F11/2236
摘要： A microprogrammed controlled commercial instruction processor coupled to a common bus executes a diagnostic microprogram to check the data path of the common bus interface registers and their associated internal registers. Decoded bits of a predetermined microword of the diagnostic microprogram generate a signal which transfers a predetermined data word containing a plurality of bytes stored in a first of the internal registers sequentially through the interface registers to a second of the internal registers during one microword cycle. Apparatus generates bad parity for selected bytes. Subsequent microwords compare the contents of the first and second internal registers and verify the detection of the "bad" parity.
摘要翻译：耦合到公共总线的微程序控制商业指令处理器执行诊断微程序，以检查公共总线接口寄存器及其相关内部寄存器的数据路径。诊断微程序的预定微字的解码位产生一个信号，该信号在一个微字循环期间通过接口寄存器顺序地将存储在第一内部寄存器中的包含多个字节的预定数据字传送到第二个内部寄存器。设备为选定的字节产生不良的奇偶校验。后续微词比较第一和第二内部寄存器的内容，并验证“坏”奇偶校验的检测。

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