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1. 发明授权

US4667288A Enable/disable control checking apparatus 失效
标题翻译：启用/禁用控制检查装置
公开(公告)号：US4667288A
公开(公告)日：1987-05-19
申请号：US509898
申请日：1983-06-30
申请人： James W. Keeley , Robert V. Ledoux , Virendra S. Negi
发明人： James W. Keeley , Robert V. Ledoux , Virendra S. Negi
IPC分类号： G06F11/07 , G06F11/10 , G06F11/22 , G06F12/00 , G06F12/12 , G11C29/00
CPC分类号： G11C29/88 , G06F11/073 , G06F11/0772 , G06F11/2289 , G06F12/126 , G06F11/10 , G06F12/00 , G06F2212/1032
摘要： A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test control apparatus which couples to the directory error checking apparatus operates to selectively enable and disable the directory error checking circuits in response to commands received from a central processing unit so as to enable the testing of the cache directory and other portions of the cache system using common test routines.
摘要翻译：其目录和高速缓存存储器被组织到存储器位置的级别的多级组关联缓存系统包括控制装置，其响应于来自目录错误检查电路的错误信号而选择性地降级高速缓存操作到被检测为没有错误的那些级别。耦合到目录错误检查装置的测试控制装置操作以响应于从中央处理单元接收的命令选择性地启用和禁用目录错误检查电路，以便能够使用高速缓存系统的高速缓存目录和其他部分的测试常用测试程序。

2. 发明授权

US4686621A Test apparatus for testing a multilevel cache system with graceful degradation capability 失效
标题翻译：用于测试具有优雅降级能力的多级缓存系统的测试装置
公开(公告)号：US4686621A
公开(公告)日：1987-08-11
申请号：US510079
申请日：1983-06-30
申请人： James W. Keeley , Robert V. Ledoux , Virendra S. Negi
发明人： James W. Keeley , Robert V. Ledoux , Virendra S. Negi
IPC分类号： G06F11/20 , G06F11/267 , G06F12/08 , G11C29/00 , G06F11/00 , G11C7/00
CPC分类号： G06F12/126 , G06F12/0864 , G11C29/88 , G06F11/2236 , G06F2212/1032
摘要： A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test apparatus coupled to the control apparatus and operates to selectively alter the operational states of the cache levels in response to commands received from a central processing unit for enabling testing of such control apparatus in addition to the other cache control areas.
摘要翻译：其目录和高速缓存存储器被组织到存储器位置的级别的多级组关联缓存系统包括控制装置，其响应于从目录错误检查电路到被检测为没有错误的那些级别的错误信号选择性地降级缓存操作。测试装置耦合到控制装置并且操作以响应于从中央处理单元接收到的命令来选择性地改变高速缓存级别的操作状态，用于除了其他高速缓存控制区域之外还能够对这种控制装置进行测试。

3. 发明授权

US4562536A Directory test error mode control apparatus 失效
标题翻译：目录测试错误模式控制装置
公开(公告)号：US4562536A
公开(公告)日：1985-12-31
申请号：US509825
申请日：1983-06-30
申请人： James W. Keeley , Robert V. Ledoux , Virendra S. Negi
发明人： James W. Keeley , Robert V. Ledoux , Virendra S. Negi
IPC分类号： G06F11/00 , G06F11/10 , G06F11/267 , G06F12/08 , G06F12/12 , G11C29/00 , G11C29/02 , G06F13/00
CPC分类号： G06F11/1666 , G06F11/2215 , G06F12/0864 , G06F12/126 , G11C29/02 , G11C29/88 , G06F11/1064 , G06F11/20 , G06F2201/85 , G06F2212/1032
摘要： A multilevel set associative cache system whose directory and cache store organized into levels of memory locations. Round robin replacement apparatus is used to identify in which level information is to be replaced. The directory includes error checking apparatus for generating address check bits which are written into directory locations together with addresses. Control apparatus in response to error signals from the error checking apparatus degrades cache operation to those levels detected to be free from errors. Test error mode control apparatus which couples to the replacement and check bit apparatuses causes the address check bits to be selectively forced to incorrect values in response to commands received from a central processing unit enabling the verification of both the checking and control apparatus without interference from other operations initiated by the central processing unit.
摘要翻译：一个多级集合关联缓存系统，其目录和高速缓存存储组织到内存级别的位置。轮询更换装置用于识别要更换哪个级别的信息。该目录包括用于产生与地址一起写入目录位置的地址校验位的错误检查装置。响应于来自错误检查装置的错误信号的控制装置将高速缓存操作降级到被检测为没有错误的那些级别。耦合到替换和检查比特装置的测试错误模式控制装置使得地址校验位响应于从中央处理单元接收到的命令被选择性地强制为不正确的值，从而能够对来自其他的干扰的校验和控制装置进行验证由中央处理单元发起的操作。

4. 发明授权

US5193181A Recovery method and apparatus for a pipelined processing unit of a multiprocessor system 失效
标题翻译：多处理器系统管道处理单元的恢复方法和装置
公开(公告)号：US5193181A
公开(公告)日：1993-03-09
申请号：US593458
申请日：1990-10-05
申请人： George J. Barlow , James W. Keeley , Richard A. Lemay , Jian-Kuo Shen , Robert V. Ledoux, deceased , Thomas F. Joyce , Richard P. Kelly , Robert C. Miller
发明人： George J. Barlow , James W. Keeley , Richard A. Lemay , Jian-Kuo Shen , Robert V. Ledoux, deceased , Thomas F. Joyce , Richard P. Kelly , Robert C. Miller
IPC分类号： G06F11/00 , G06F11/22
CPC分类号： G06F11/0793 , G06F11/0724 , G06F11/0766 , G06F11/004 , G06F11/2205
摘要： The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode. Control circuits execute a UEV handler microcode routine which reads the contents of syndrome registers included on each board containing the UEV indicator states in addition to error signals into register file working locations. The UEV signal is then cleared enabling the BIU to resume communications with the sytem bus.

5. 发明授权

US4764862A Resilient bus system 失效
标题翻译：弹性总线系统
公开(公告)号：US4764862A
公开(公告)日：1988-08-16
申请号：US717201
申请日：1985-03-28
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F11/00 , G06F13/42 , G06F13/14
CPC分类号： G06F13/4213 , G06F11/00
摘要： A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and like checking apparatus for verifying that the different parts of a request received from such unit over the bus are valid based upon the states of accompanying function identification signals. When less than all of the parts of the request defined as requiring verification are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.
摘要翻译：数据处理系统包括多个单元，其被耦合以在分配的总线传送周期期间通过系统总线在单元之间传送包括数据，命令和完整性信号的请求。每个单元包括用于确认从其他单元接收的请求的响应装置。多个单元中的每一个还包括重试设备和类似的检查装置，用于根据伴随的功能识别信号的状态来验证从该单元接收的请求的不同部分是否有效。当被检测为需要验证的请求的全部部分被检测为有效时，接收单元不接受该请求并禁止其响应装置产生响应。这样可以防止系统完整性受到损害，并允许每个重试设备的单元在随后的总线传输周期内重试该请求。

6. 发明授权

US4724519A Channel number priority assignment apparatus 失效
标题翻译：频道编号优先分配装置
公开(公告)号：US4724519A
公开(公告)日：1988-02-09
申请号：US750117
申请日：1985-06-28
申请人： George J. Barlow , James W. Keeley , Elmer W. Carroll
发明人： George J. Barlow , James W. Keeley , Elmer W. Carroll
IPC分类号： G06F13/14 , G06F12/06 , G06F13/362 , G06F13/368 , G06F13/378 , G06F13/36
CPC分类号： G06F13/368 , G06F12/0623 , G06F13/378
摘要： A data processing system has a system bus network which includes a distributed priority network for transferring data asynchronously between a number of subsystems which couple to the bus. Each subsystem includes priority logic circuits coupled to receive a group of priority signals from the priority network which establish when the subsystem has the highest priority of the requesting subsystems to access the bus. The number of subsystems include a plurality of identical subsystems, each of which has a channel number assignment apparatus. The apparatus of each identical subsystem is connected to receive the same of at least one of the group of priority signals. During the idle state of the system bus, the apparatus of each identical subsystem operates to store a unique state of the priority signal which is defined as a function of the subsystem's position on the bus thereby automatically establishing a unique channel number value for each identical subsystem.
摘要翻译：数据处理系统具有系统总线网络，该系统总线网络包括用于在耦合到总线的多个子系统之间异步地传送数据的分布式优先级网络。每个子系统包括优先级逻辑电路，其被耦合以从优先级网络接收一组优先级信号，该优先级信号建立当子系统具有请求子系统访问总线的最高优先级时。子系统的数量包括多个相同的子系统，每个子系统具有信道号分配装置。每个相同子系统的装置被连接以接收该组优先级信号中的至少一个。在系统总线的空闲状态期间，每个相同子系统的装置操作以存储优先级信号的唯一状态，其被定义为总线上子系统位置的函数，从而为每个相同的子系统自动建立唯一的信道数值。

7. 发明授权

US08116330B2 Bridge apparatus and methods for coupling multiple non-fibre channel devices to a fibre channel arbitrated loop 失效
标题翻译：用于将多个非光纤信道设备耦合到光纤信道仲裁环路的桥接设备和方法
公开(公告)号：US08116330B2
公开(公告)日：2012-02-14
申请号：US12475838
申请日：2009-06-01
申请人： James W. Keeley , Douglas E. Sanders , Andrew Hyonil Chong
发明人： James W. Keeley , Douglas E. Sanders , Andrew Hyonil Chong
IPC分类号： H04L12/56
CPC分类号： G06F13/404
摘要： Apparatus and methods for an enhanced bridge device for coupling multiple non-Fiber Channel storage devices to a Fiber Channel Arbitrated Loop (FC-AL) communication medium. Features and aspects hereof provide for FC-AL enhanced circuits for processing loop port bypass (LPB) and loop port enable (LPE) primitive sequences addressed to any target arbitrated loop physical address (T-ALPA) associated with a storage device coupled with the bridge regardless of the present bypassed/non-bypassed status of other T-ALPAs processed by the bridge device and associated with other storage devices coupled with the bridge device.
摘要翻译：用于将多个非光纤通道存储设备耦合到光纤通道仲裁环（FC-AL）通信介质的增强桥接设备的装置和方法。其特征和方面提供了用于处理环路端口旁路（LPB）和环路端口使能（LPE）原语序列的FC-AL增强电路，寻址到与桥耦合的存储设备相关联的任何目标仲裁环物理地址（T-ALPA）而不考虑由桥接设备处理并与与桥接设备耦合的其他存储设备相关联的其他T-ALPA的当前旁路/非旁路状态。

8. 发明授权

US5664200A Apparatus and method for providing more effective reiterations of interrupt requests in a multiprocessor system 失效
标题翻译：在多处理器系统中提供更有效重复中断请求的装置和方法
公开(公告)号：US5664200A
公开(公告)日：1997-09-02
申请号：US414983
申请日：1995-03-31
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F9/46 , G06F13/24 , G06F13/26 , G06F15/16 , G06F15/17 , G06F15/177 , G06F13/18
CPC分类号： G06F13/24 , G06F13/26 , G06F15/17
摘要： A multiprocessor computer system includes a number of processors, each processor having an interrupt mechanism and connecting in common to a system bus over which interrupt requests are communicated. When a processor accepts an interrupt request from another processor, it generates an acknowledge response on the system bus. If such processor contains a previous and pending interrupt request of an equal or higher priority level, it generates a not acknowledge response on the system bus and refuses the interrupt request. At the completion of servicing an interrupt request, each processor places on the system bus, an interrupt completed command including an address identifying such processor, a code designating a priority level to which it has switched and a code indicating that the processor has completing servicing an interrupt request. Each interrupt mechanism further includes interrupt retry means containing a refused interrupt register means for storing the channel address of the processor generating the not acknowledge in response and the priority level code contained in the interrupt request, and a level monitor logic unit connected to the system bus. The level monitor logic unit detects interrupt completed commands and compares the channel address and priority level code in the interrupt completed command to channel address and level code stored in the refused interrupt register means. When the processor channel addresses match and the level code is less than the level stored in the refused interrupt register means, the monitor logic unit generates a retry interrupt output. The processor retries the corresponding previously refused interrupt request upon receipt of the retry interrupt output.
摘要翻译：多处理器计算机系统包括多个处理器，每个处理器具有中断机制并且共同连接到通过其传送中断请求的系统总线。当处理器接受另一个处理器的中断请求时，它会在系统总线上产生一个确认响应。如果这样的处理器包含等于或更高优先级的先前和未决的中断请求，它将在系统总线上产生不确认响应并拒绝中断请求。在完成对中断请求的服务的完成时，每个处理器放置在系统总线上，一个中断完成命令，包括一个标识这样的处理器的地址，一个指定其所切换的优先级的代码，以及一个指示处理器完成服务的代码中断请求。每个中断机制还包括中断重试装置，其中包含一个拒绝中断寄存器装置，用于存储响应中产生不应答的处理器的通道地址以及中断请求中包含的优先级代码，以及连接到系统总线的电平监视逻辑单元。电平监视逻辑单元检测中断完成命令，并将中断完成命令中的通道地址和优先级代码与存储在拒绝中断寄存器装置中的通道地址和电平代码进行比较。当处理器通道地址匹配并且电平代码小于存储在拒绝中断寄存器装置中的电平时，监视器逻辑单元产生重试中断输出。接收到重试中断输出后，处理器重试相应的先前拒绝的中断请求。

9. 发明授权

US5446847A Programmable system bus priority network 失效
标题翻译：可编程系统总线优先网络
公开(公告)号：US5446847A
公开(公告)日：1995-08-29
申请号：US531
申请日：1993-01-04
申请人： James W. Keeley , George J. Barlow , Richard A. Lemay
发明人： James W. Keeley , George J. Barlow , Richard A. Lemay
IPC分类号： G06F13/372 , G06F13/18
CPC分类号： G06F13/372
摘要： A bus interface priority network provides access to a system bus by a plurality of different types of requestors as a function of the types of transactions they are required to process. The network includes programmable circuit for identifying the type of requestor and selecting a delay for accessing the system bus on the basis of requestor type thereby eliminating the need to adjust timing to the slowest requestor.
摘要翻译：总线接口优先级网络通过多个不同类型的请求者提供对系统总线的访问，作为它们需要处理的事务的类型的函数。该网络包括用于识别请求者的类型的可编程电路，并且基于请求者类型选择访问系统总线的延迟，从而消除了对最慢请求者调整定时的需要。

10. 发明授权

US5341495A Bus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocols 失效
标题翻译：总线控制器具有用于转换命令和控制从具有不同总线协议的系统总线到同步总线的访问的状态机
公开(公告)号：US5341495A
公开(公告)日：1994-08-23
申请号：US771297
申请日：1991-10-04
申请人： Thomas F. Joyce , James W. Keeley , Richard A. Lemay , Bruno DiPlacido, Jr. , Martin M. Massucci
发明人： Thomas F. Joyce , James W. Keeley , Richard A. Lemay , Bruno DiPlacido, Jr. , Martin M. Massucci
IPC分类号： G06F13/40 , G06F13/42 , G06F13/00 , G06F13/38
CPC分类号： G06F13/4027
摘要： A processing unit tightly couples to a system bus which utilizes a split cycle bus protocol and includes a local memory which is accessible from such bus. The local memory couples to a high speed synchronous bus which operates according to a predetermined bus protocol. The processing unit includes a state machine which couples to the high speed synchronous bus and to the asynchronous system bus. The state machine emulates the predetermined bus synchronous protocol in transferring commands issued to the local memory from the system bus which uses the split cycle protocol.
摘要翻译：处理单元紧密地耦合到利用分离循环总线协议的系统总线，并且包括可以从这种总线访问的本地存储器。本地存储器耦合到根据预定总线协议操作的高速同步总线。处理单元包括耦合到高速同步总线和异步系统总线的状态机。状态机在从使用分离周期协议的系统总线传送发给本地存储器的命令时模拟预定的总线同步协议。

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