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1. 发明授权

US4462072A Clock system having a stall capability to enable processing of errors 失效
标题翻译：具有能够处理错误的失速能力的时钟系统
公开(公告)号：US4462072A
公开(公告)日：1984-07-24
申请号：US250810
申请日：1981-04-03
申请人： Steven A. Tague , Virendra S. Negi
发明人： Steven A. Tague , Virendra S. Negi
IPC分类号： G06F1/08 , G06F11/07 , G06F7/00 , G06F11/00
CPC分类号： G06F11/073 , G06F1/08 , G06F11/0721 , G06F11/0793
摘要： A microprogrammed commercial instruction processor (CIP) is placed in a stall mode during the transfer of information between the CIP and main memory by stalling a free running clock signal. When the transfer of information is completed, the free running clock cycles. If main memory indicates an error condition, then the free running clock signal is again stalled after one cycle to allow the firmware in the CIP to process the error.
摘要翻译：通过停止自由运行的时钟信号，在CIP和主存储器之间的信息传送期间，微程序商业指令处理器（CIP）被置于停止模式。当信息传输完成时，自由运行的时钟周期。如果主存储器指示错误状况，则自由运行的时钟信号在一个周期后再次停止，以允许CIP中的固件处理该错误。

2. 发明授权

US4384340A Data processor having apparatus for controlling the selection of decimal digits of an operand when executing decimal arithmetic instructions 失效
标题翻译：数据处理器具有用于在执行十进制运算指令时控制操作数的小数位的选择的装置
公开(公告)号：US4384340A
公开(公告)日：1983-05-17
申请号：US220220
申请日：1980-12-24
申请人： Steven A. Tague , Virendra S. Negi
发明人： Steven A. Tague , Virendra S. Negi
IPC分类号： G06F7/38 , G06F7/00 , G06F7/496 , G06F7/506 , G06F7/525 , G06F9/22 , G06F7/50 , G06F7/52
CPC分类号： G06F9/226
摘要： A commercial instruction processor executes decimal arithmetic instructions on string decimal and packed decimal operands. A read only memory is responsive to control signals generated from the operation code portion of the instruction, a type signal from a descriptor word of the instruction, and signals indicating the present decimal digit position being processed to generate signals indicating next decimal digit position to be processed.
摘要翻译：商业指令处理器对字符串十进制和压缩十进制操作数执行十进制运算指令。只读存储器响应于从指令的操作代码部分生成的控制信号，来自指令的描述符字的类型信号和指示当前十位数位置的信号被处理以产生指示下一个十位数位置的信号为处理。

3. 发明授权

US4484300A Data processor having units carry and tens carry apparatus supporting a decimal multiply operation 失效
标题翻译：具有单元的数据处理器进位和十进位装置支持十进制乘法运算
公开(公告)号：US4484300A
公开(公告)日：1984-11-20
申请号：US219810
申请日：1980-12-24
申请人： Virendra S. Negi , Steven A. Tague
发明人： Virendra S. Negi , Steven A. Tague
IPC分类号： G06F7/38 , G06F7/483 , G06F7/491 , G06F7/496 , G06F7/508 , G06F7/52 , G06F7/527
CPC分类号： G06F7/4915
摘要： A data processing system executes a decimal multiply instruction by storing the product of a multiplier decimal digit and a multiplicand decimal digit in a read only memory and storing partial product decimal digits in a register. The units product decimal digit is read from the read only memory during one cycle and added to a partial product decimal digit. A resulting units carry is stored in a units carry flip-flop. The tens product decimal digit is read from the read only memory during another cycle and added to a higher order partial product decimal digit. A resulting tens carry is stored in a tens carry flip-flop. A multiplexer selects the output of the units carry flip-flop for adding the units carry during the next units cycle in which the next units product decimal digit is added to the higher order partial product decimal digit. The multiplexer selects the output of the tens carry flip-flop for adding the tens carry during the next tens cycle in which the next tens product decimal digit is added to a next higher order partial product decimal digit.
摘要翻译：数据处理系统通过将乘数十进制数和乘数十进制数的乘积存储在只读存储器中并将部分乘积十进制数字存储在寄存器中来执行十进制乘法指令。单位产品十进制数字在一个周期内从只读存储器读取，并添加到部分乘积十进制数字。结果单位进位存储在单位进位触发器中。在另一个周期内，从只读存储器读取十位数十进制数，并将其加到较高阶部分乘积十进制数字。结果十进位存储在十进位触发器中。多路复用器在下一个单位周期内，将下一个单位乘积十进制数字加到较高阶部分乘积十进制数字中，选择输入单元的单元进位触发器来添加单位进位。多路复用器选择十位进位触发器的输出，在下一个十位周期中将下一个十位乘数十进制数字加到下一个高阶部分乘积十进制数字的十进位。

4. 发明授权

US4410984A Diagnostic testing of the data path in a microprogrammed data processor 失效
标题翻译：在微程序数据处理器中对数据路径进行诊断测试
公开(公告)号：US4410984A
公开(公告)日：1983-10-18
申请号：US250820
申请日：1981-04-03
申请人： Virendra S. Negi , Steven A. Tague
发明人： Virendra S. Negi , Steven A. Tague
IPC分类号： G06F11/267 , G06F11/00
CPC分类号： G06F11/2236
摘要： A microprogrammed controlled commercial instruction processor coupled to a common bus executes a diagnostic microprogram to check the data path of the common bus interface registers and their associated internal registers. Decoded bits of a predetermined microword of the diagnostic microprogram generate a signal which transfers a predetermined data word containing a plurality of bytes stored in a first of the internal registers sequentially through the interface registers to a second of the internal registers during one microword cycle. Apparatus generates bad parity for selected bytes. Subsequent microwords compare the contents of the first and second internal registers and verify the detection of the "bad" parity.
摘要翻译：耦合到公共总线的微程序控制商业指令处理器执行诊断微程序，以检查公共总线接口寄存器及其相关内部寄存器的数据路径。诊断微程序的预定微字的解码位产生一个信号，该信号在一个微字循环期间通过接口寄存器顺序地将存储在第一内部寄存器中的包含多个字节的预定数据字传送到第二个内部寄存器。设备为选定的字节产生不良的奇偶校验。后续微词比较第一和第二内部寄存器的内容，并验证“坏”奇偶校验的检测。

5. 发明授权

US4426680A Data processor using read only memories for optimizing main memory access and identifying the starting position of an operand 失效
标题翻译：数据处理器使用只读存储器来优化主存储器访问并识别操作数的起始位置
公开(公告)号：US4426680A
公开(公告)日：1984-01-17
申请号：US219809
申请日：1980-12-24
申请人： Steven A. Tague , Virendra S. Negi
发明人： Steven A. Tague , Virendra S. Negi
IPC分类号： G06F7/00 , G06F7/76 , G06F9/22 , G06F7/38
CPC分类号： G06F9/226
摘要： A data processing system which includes a commercial instruction processor for executing decimal alphanumeric instructions uses read only memories in the alignment of the operands. The characteristics of the operands, string or packed decimal, as well as the length and position of the most significant decimal digit in a main memory word, are specified by data descriptors. The read only memories are responsive to the data descriptor information as well as the instruction being executed to generate signals which specify whether the direction words are read from main memory, high order word first or low order word first, the number of double words in the operand and the location of the least or most significant decimal digit within the word as stored in registers of the commercial instruction processor.
摘要翻译：包括用于执行十进制字母数字指令的商业指令处理器的数据处理系统在操作数的对齐中使用只读存储器。操作数，字符串或压缩十进制的特征以及主存储器字中最重要的十进制数字的长度和位置由数据描述符指定。只读存储器响应于数据描述符信息以及正在执行的指令，以产生指定从主存储器读取方向字，高位字首先还是低位字首先被读取的信号，操作数和存储在商业指令处理器的寄存器中的单词内最小或最重要的十进制数字的位置。

6. 发明授权

US4390961A Data processor performing a decimal multiply operation using a read only memory 失效
标题翻译：数据处理器使用只读存储器执行十进制乘法运算
公开(公告)号：US4390961A
公开(公告)日：1983-06-28
申请号：US220218
申请日：1980-12-24
申请人： Virendra S. Negi , Steven A. Tague
发明人： Virendra S. Negi , Steven A. Tague
IPC分类号： G06F7/483 , G06F7/491 , G06F7/496 , G06F7/508 , G06F7/52 , G06F7/523 , G06F7/527
CPC分类号： G06F7/4915
摘要： A data processor performs a decimal multiply operation using apparatus including a register for storing multiplier decimal digits, a register for storing a multiplicand operand of decimal digits, a register for storing partial products and arithmetic logic units, and a read only memory for storing the units and tens product digits. The multiplier digit and a selected multiplicand digit are applied to the address terminals of the read only memory. On successive cycles, the units product digit and the tens product digit are added respectively to selected partial product digits and the sum replaces the selected partial product digits.
摘要翻译：数据处理器使用包括用于存储乘法器十进制数字的寄存器，用于存储小数位的被乘数操作数的寄存器，用于存储部分乘积的寄存器和算术逻辑单元的装置以及用于存储单位的只读存储器来执行十进制乘法运算和十个商品数字。乘数和选择的被乘数被施加到只读存储器的地址端。在连续循环中，单位产品数字和十位产品数字分别添加到选定的部分产品数字，并且和代替了所选择的部分产品数字。

7. 发明授权

US4384341A Data processor having carry apparatus supporting a decimal divide operation 失效
标题翻译：具有支持小数除法运算的进位装置的数据处理器
公开(公告)号：US4384341A
公开(公告)日：1983-05-17
申请号：US219638
申请日：1980-12-24
申请人： Steven A. Tague , Virendra S. Negi
发明人： Steven A. Tague , Virendra S. Negi
IPC分类号： G06F7/496 , G06F7/483 , G06F7/491 , G06F7/493 , G06F7/508 , G06F7/52 , G06F7/533
CPC分类号： G06F7/4917
摘要： A commercial instruction processor executes a decimal divide instruction by counting the number of subtractions by the divisor resulting in a positive remainder to develop the quotient. Apparatus compares the most significant decimal digit of the divisor with the most significant decimal digit of the remainder after each subtraction pass to predict if the next subtraction pass would result in a negative remainder. If so, a quotient decimal digit is stored in a memory, the divisor is shifted one decimal digit position to the right, and a series of subtraction passes are made to develop the next quotient decimal digit.
摘要翻译：商业指令处理器通过对由除数产生的正数余数进行计数来执行十进制除法指令来开发商。设备将除数的最有意义的十进制数与每次减法通过后余数中最有效的十进制数进行比较，以预测下一个减法通过是否会导致负余数。如果是这样的话，一个商数十进制数存储在一个存储器中，除数将一个十进制数位置向右移位，并进行一系列的减法遍数来形成下一个十进制数字。

8. 发明授权

US4447870A Apparatus for setting the basic clock timing in a data processing system 失效
标题翻译：用于在数据处理系统中设置基本时钟定时的装置
公开(公告)号：US4447870A
公开(公告)日：1984-05-08
申请号：US250823
申请日：1981-04-03
申请人： Steven A. Tague , Virendra S. Negi
发明人： Steven A. Tague , Virendra S. Negi
IPC分类号： G06F1/08 , G06F1/04
CPC分类号： G06F1/08
摘要： A microprogrammed commercial instruction processor in a data processing system includes a bank of switches coupled to a multitapped delay line for selecting delay line signals for setting the basic clock timing. Another of the switches when activated conditions the commercial instruction processor so that when it is reset a special clock setting firmware loop is entered. The loop provides an uninterrupted succession of clock pulses which allows one to adjust the basic clock timing within specification.
摘要翻译：数据处理系统中的微程序商业指令处理器包括耦合到多重延迟线的开关组，用于选择用于设置基本时钟时序的延迟线信号。当激活条件时，另一个开关条件使商业指令处理器复位时，输入一个特殊的时钟设置固件循环。该环路提供了不间断的时钟脉冲序列，可以在规范内调整基本时钟时序。

9. 发明授权

US4423483A Data processor using a read only memory for selecting a part of a register into which data is written 失效
标题翻译：数据处理器使用只读存储器来选择写入数据的寄存器的一部分
公开(公告)号：US4423483A
公开(公告)日：1983-12-27
申请号：US220219
申请日：1980-12-24
申请人： Steven A. Tague , Virendra S. Negi
发明人： Steven A. Tague , Virendra S. Negi
IPC分类号： G06F7/38 , G06F7/00 , G06F7/496 , G06F7/506 , G06F7/525 , G06F9/22 , G06F7/50
CPC分类号： G06F9/226
摘要： A data processing system includes a commercial instruction processor (CIP) for executing decimal arithmetic instructions. The operands processed by the CIP include packed decimal and string decimal operands. The decimal arithmetic instruction includes descriptors for describing the characteristics of the operands. A register coupled to an arithmetic logic unit stores double words of the operands which are written into the register as double words, bytes or decimal digits. A multiplexer is responsive to control store signals and descriptor signals for generating write control signals which are applied to a read only memory. The read only memory output write signals select the decimal digit, byte or double word positions of the register for writing.
摘要翻译：数据处理系统包括用于执行十进制算术指令的商业指令处理器（CIP）。由CIP处理的操作数包括压缩十进制和字符串十进制操作数。十进制算术指令包含描述操作数特征的描述符。耦合到算术逻辑单元的寄存器存储作为双字，字节或十进制数字写入寄存器的操作数的双字。复用器响应于控制存储信号和描述符信号，用于产生施加到只读存储器的写入控制信号。只读存储器输出写入信号选择写入寄存器的十进制数字，字节或双字位置。

10. 发明授权

US5283876A Virtual memory unit utilizing set associative memory structure and state machine control sequencing with selective retry 失效
标题翻译：虚拟存储单元利用集合关联存储器结构和状态机控制排序与选择性重试
公开(公告)号：US5283876A
公开(公告)日：1994-02-01
申请号：US593825
申请日：1990-10-05
申请人： Steven A. Tague
发明人： Steven A. Tague
IPC分类号： G06F12/12 , G06F12/08 , G06F12/02
CPC分类号： G06F12/126 , G06F12/0864
摘要： A virtual memory unit has a plurality of directory and buffer store levels for storing page descriptor information. The memory directories and a least recently used (LRU) device constructed from the same type of standard cache address directory part include parity error detection circuits. The virtual memory unit further includes a state machine for defining sequential states used in generating control signals for directing the memory unit's operation in translating virtual addresses into physical addresses. Programmable control circuits which generate the required input data and control signals applied to the directories and LRU device for reading and updating their contents further include the retry facilities which, in response to certain types of error situations, alter state machine sequencing to again try the virtual to physical address translation with a fresh copy and the LRU replacement operations in a way to improve robustness.
摘要翻译：虚拟存储器单元具有用于存储页面描述符信息的多个目录和缓冲存储级别。由相同类型的标准高速缓存地址目录部分构建的存储器目录和最近最少使用的（LRU）设备包括奇偶校验错误检测电路。虚拟存储器单元还包括状态机，用于定义用于产生用于指示存储器单元将虚拟地址转换为物理地址的操作的控制信号中使用的顺序状态。生成应用于目录和LRU设备的读取和更新其内容的所需输入数据和控制信号的可编程控制电路进一步包括重试设施，响应于某些类型的错误情况，改变状态机排序以再次尝试虚拟通过新的副本和LRU替换操作来实现物理地址转换，以提高鲁棒性。

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