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4. 实用新型

JPS5496545U 失效
公开(公告)号：JPS5496545U
公开(公告)日：1979-07-07
申请号：JP17367078
申请日：1978-12-18
IPC分类号： G06F9/46 , G06F12/10 , G06F12/14 , G06F9/20 , G06F9/18 , G11C9/06
摘要： Apparatus for use within a virtual memory data processing system offering a way of protecting data used at one interrupt level state from unauthorized use at another interrupt level state. A virtual memory data processing system permits a computer program to specify relative (or virtual) addresses rather than physical (or real) addresses. Most practical virtual memory data processing systems utilize a Virtual Address Translator (VAT), often called a Directory Look-Aside Table (DLAT). The VAT contains a plurality of internal conversion tables which perform virtual address to real address translation. A binary code, called the Interrupt Level Code (ILC), is appended to the virtual address of entries within the plurality of internal conversion tables within the VAT to permit the VAT to translate virtual addresses to real addresses only if the present Central Processing Unit (CPU) interrupt level state corresponds to the interrupt level state denoted by the ILC within the VAT. This prohibits the VAT from translating virtual addresses to real addresses at one interrupt level state based upon entries within the plurality of internal conversion tables entered to translate virtual addresses to real addresses at a different interrupt level state.

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