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1. 发明申请

US20120208356A1 Device component forming method with a trim step prior to sidewall image transfer (SIT) processing 审中-公开
标题翻译：在侧壁图像转印（SIT）处理之前具有修整步骤的装置部件形成方法
公开(公告)号：US20120208356A1
公开(公告)日：2012-08-16
申请号：US13456282
申请日：2012-04-26
申请人： Toshiharu Furukawa , David V. Horak , Charles W. Koburger, III , Qiqing C. Ouyang
发明人： Toshiharu Furukawa , David V. Horak , Charles W. Koburger, III , Qiqing C. Ouyang
IPC分类号： H01L21/20 , H01L21/302
CPC分类号： H01L21/28132 , H01L21/0337 , H01L21/0338 , H01L29/66795
摘要： Disclosed is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.
摘要翻译：公开了一种用于将部件形状（例如散热片，栅电极等）图案化成基板的成像方法。通过在执行加法或减损侧壁图像转移处理之前进行修整步骤，该方法避免了在硬掩模中形成环形图案，并且因此避免了后SIT工艺修整步骤，需要修剪蒙版对准亚光刻特征以形成具有离散片段的硬掩模图案。在一个实施例中，在进行添加SIT处理之前修剪硬掩模，使得不形成环形图案。在另一个实施例中，用于形成心轴的氧化物层和记忆层在进行减法SIT处理之前被修整。然后在氧化层的回蚀刻期间使用掩模来保护心轴的部分，使得不形成环形图案。

2. 发明授权

US08110483B2 Forming an extremely thin semiconductor-on-insulator (ETSOI) layer 有权
标题翻译：形成极薄的绝缘体上半导体（ETSOI）层
公开(公告)号：US08110483B2
公开(公告)日：2012-02-07
申请号：US12603737
申请日：2009-10-22
申请人： Wagdi W. Abadeer , Lilian Kamal, legal representative , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：公开了用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

3. 发明申请

US20120018806A1 SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE WITH SELECTIVELY PLACED SUB-INSULATOR LAYER VOID(S) AND METHOD OF FORMING THE SOI STRUCTURE 有权
标题翻译：具有选择性的绝缘子层绝缘体的半导体绝缘体（SOI）结构和形成SOI结构的方法
公开(公告)号：US20120018806A1
公开(公告)日：2012-01-26
申请号：US12842146
申请日：2010-07-23
申请人： Toshiharu Furukawa , Robert R. Robison , Richard Q. Williams
发明人： Toshiharu Furukawa , Robert R. Robison , Richard Q. Williams
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/66477 , H01L21/02104 , H01L21/84 , H01L27/1203 , H01L29/78648 , H01L29/78654
摘要： Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure.
摘要翻译：公开了一种绝缘体半导体（SOI）结构，其具有选择性地放置在衬底中的次绝缘体层空穴，使得半导体层的第一部分与衬底之间的电容耦合将小于第二半导体层和衬底的截面。第一部分可以包含绝缘体层上的第一器件，第二部分可以在绝缘体层上包含第二器件。或者，第一和第二部分可以包括绝缘体层上相同器件的不同区域。例如，在SOI场效应晶体管（FET）中，可以将子绝缘体层空隙选择性地放置在源极，漏极和/或体接触扩散区域下方的衬底中，但不能在沟道区域下方，使得电容耦合这些各种扩散区域和衬底将小于沟道区域和衬底之间的电容耦合。此外，公开了形成这种SOI结构的相关方法。

4. 发明授权

US08039334B2 Shared gate for conventional planar device and horizontal CNT 有权
标题翻译：常规平面器件和水平CNT的共用门
公开(公告)号：US08039334B2
公开(公告)日：2011-10-18
申请号：US12902944
申请日：2010-10-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
IPC分类号： H01L21/8234
CPC分类号： H01L21/823412 , B01J23/74 , B01J37/0238 , B82Y10/00 , H01L21/7624 , H01L21/823437 , H01L27/286 , H01L51/0048 , H01L51/0545 , H01L51/055 , Y10S977/742 , Y10S977/762 , Y10S977/763
摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
摘要翻译：在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管晶体管位于至少一个平面半导体器件的栅极之上。

5. 发明授权

US08008696B2 Band gap modulated optical sensor 有权
标题翻译：带隙调制光传感器
公开(公告)号：US08008696B2
公开(公告)日：2011-08-30
申请号：US12146575
申请日：2008-06-26
申请人： Kangguo Cheng , Toshiharu Furukawa , Robert Robison , William R. Tonti
发明人： Kangguo Cheng , Toshiharu Furukawa , Robert Robison , William R. Tonti
IPC分类号： H01L29/72
CPC分类号： H01L27/14645 , H01L27/14627
摘要： A complementary metal-oxide-semiconductor (CMOS) optical sensor structure comprises a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data. Further, a design structure for the inventive complementary metal-oxide-semiconductor (CMOS) image sensor is also provided.
摘要翻译：互补金属氧化物半导体（CMOS）光学传感器结构包括含有与半导体衬底中的半导体层相同的半导体材料的电荷收集阱的像素，以及包含不同半导体材料的另一电荷收集阱的至少另一个像素半导体层的材料。电荷收集阱具有不同的带隙，因此响应于具有不同波长的光而产生电荷载流子。因此，CMOS传感器结构包括响应于不同波长的光的至少两个像素，使得能够对光学数据进行波长敏感或颜色敏感的捕获。此外，还提供了本发明的互补金属氧化物半导体（CMOS）图像传感器的设计结构。

6. 发明授权

US08004024B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08004024B2
公开(公告)日：2011-08-23
申请号：US12348404
申请日：2009-01-05
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L29/423 , H01L29/78
CPC分类号： H01L29/4983 , H01L29/4908 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78621 , Y10S977/742 , Y10S977/847
摘要： A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.
摘要翻译：晶体管。晶体管包括：衬底中的阱区; 在所述阱区的顶表面上的栅介质层; 栅极电介质层的顶表面上的多晶硅栅电极; 间隔物形成在多晶硅栅电极的相对侧壁上; 形成在阱区中的多晶硅栅电极的相对侧上的源/漏区; 所述多晶硅栅电极中的第一掺杂区域，所述第一掺杂区域从所述多晶硅栅电极的顶表面延伸到所述多晶硅栅电极; 以及多晶硅栅电极中的掩埋的第二掺杂区。

7. 发明授权

US07951657B2 Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor 有权
标题翻译：在绝缘体上硅（S0I）晶片上形成具有嵌入式和多面源极/漏极应力的平面场效应晶体管的方法，平面场效应晶体管结构和用于平面场效应晶体管的设计结构
公开(公告)号：US07951657B2
公开(公告)日：2011-05-31
申请号：US12470001
申请日：2009-05-21
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
IPC分类号： H01L21/84
CPC分类号： H01L29/66636 , H01L21/26506 , H01L29/1079 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.
摘要翻译：公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以便选择性地调节凹陷侧壁的形状（即，轮廓）而不增加凹槽随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。还公开了平面FET结构和平面FET的设计结构的实施例。

8. 发明授权

US07936017B2 Reduced floating body effect without impact on performance-enhancing stress 有权
标题翻译：降低浮体效应，而不影响性能增强应力
公开(公告)号：US07936017B2
公开(公告)日：2011-05-03
申请号：US12120836
申请日：2008-05-15
申请人： William F. Clark, Jr. , Toshiharu Furukawa , Xuefeng Hua , Charles W. Koburger, III , Robert R. Robison
发明人： William F. Clark, Jr. , Toshiharu Furukawa , Xuefeng Hua , Charles W. Koburger, III , Robert R. Robison
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/165 , H01L29/665 , H01L29/66772 , H01L29/7848 , H01L29/78612 , H01L29/78621
摘要： A method, gated device and design structure are presented for providing reduced floating body effect (FBE) while not impacting performance enhancing stress. One method includes forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another portion of the damaged portion at least adjacent to a channel region; and substantially filling the trench with a material to form a source/drain region.
摘要翻译：提出了一种方法，选通装置和设计结构，用于提供减少的浮体效应（FBE），同时不影响性能增强应力。一种方法包括在与栅极相邻的衬底的一部分中形成损伤; 去除损坏部分的一部分以形成沟槽，将损坏部分的另一部分至少邻近沟道区域; 并且用材料基本上填充沟槽以形成源极/漏极区域。

9. 发明申请

US20110097824A1 METHOD OF CREATING AN EXTREMELY THIN SEMICONDUCTOR-ON- INSULATOR (ETSOI) LAYER HAVING A UNIFORM THICKNESS 有权
标题翻译：创建具有均匀厚度的极细二极管绝缘体（ETSOI）层的方法
公开(公告)号：US20110097824A1
公开(公告)日：2011-04-28
申请号：US12603671
申请日：2009-10-22
申请人： Nathaniel C. BERLINER , Kangguo CHENG , Toshiharu FURUKAWA , William R. TONTI , Douglas C. La TULIPE, Jr.
发明人： Nathaniel C. BERLINER , Kangguo CHENG , Toshiharu FURUKAWA , William R. TONTI , Douglas C. La TULIPE, Jr.
IPC分类号： H01L21/302 , C23F1/08 , H01L21/66
CPC分类号： H01L22/20 , H01L21/302 , H01L21/30604 , H01L21/76254 , H01L22/12
摘要： A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.
摘要翻译：一种制造具有均匀厚度的非常薄的绝缘上绝缘体（ETSOI）层的方法包括：测量多个位置上绝缘体上半导体（SOI）层的厚度; 确定所述多个位置中的每一个处的去除厚度; 以及在所述多个位置处注入离子。基于多个位置中的每一个处的去除厚度动态地进行植入。该方法还包括氧化SOI层以形成氧化物层，并除去氧化物层。

10. 发明申请

US20110095393A1 CREATING EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) HAVING SUBSTANTIALLY UNIFORM THICKNESS 有权
标题翻译：创造出具有重大均匀厚度的极细半导体绝缘体（ETSOI）
公开(公告)号：US20110095393A1
公开(公告)日：2011-04-28
申请号：US12603668
申请日：2009-10-22
申请人： Nathaniel C. Berliner , Kangguo Cheng , Jason E. Cummings , Toshiharu Furukawa , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Nathaniel C. Berliner , Kangguo Cheng , Jason E. Cummings , Toshiharu Furukawa , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L29/06 , H01L21/66 , C23F1/08
CPC分类号： H01L21/7624 , H01L21/30625 , H01L22/12 , H01L22/20 , H01L2924/0002 , Y10S438/959 , H01L2924/00
摘要： An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.
摘要翻译：通过测量晶片上的多个选定点处的半导体层厚度，制造出具有基本上均匀的厚度的极薄的绝缘体上半导体（ETSOI）晶片; 确定在所述多个选择点中的每一个处要除去的去除厚度，使得所述去除厚度的去除导致基本上均匀的晶片内半导体层厚度; 基于各个点的去除厚度，以剂量水平和能量水平中的至少一个将多个选择点中的每一个植入种子到晶片; 并抛光半导体层以使半导体层变薄。

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