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1. 发明授权

US09219056B2 Passive devices for FinFET integrated circuit technologies 有权
标题翻译： FinFET集成电路技术的无源器件
公开(公告)号：US09219056B2
公开(公告)日：2015-12-22
申请号：US13431347
申请日：2012-03-27
申请人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Junjun Li
发明人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H01L27/06 , H01L21/20 , H01L21/33 , H01L27/02 , H01L21/8249 , H01L21/84 , H01L29/06 , H01L27/12
CPC分类号： H01L27/0262 , G06F17/5072 , H01L21/8249 , H01L21/845 , H01L27/0255 , H01L27/06 , H01L27/1211 , H01L29/06
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.
摘要翻译：无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。将绝缘体上半导体衬底的器件层的一部分图案化以形成器件区域。在外延层和器件区域中形成第一导电类型的阱。在阱中形成第二导电类型的掺杂区域并且限定与阱的一部分的结。外延层包括与器件区域的外侧壁间隔开的外侧壁。可以对器件层的另一部分进行构图以形成翅片型场效应晶体管的鳍片。

2. 发明授权

US09219055B2 Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers 有权
标题翻译：用于动态偏置的结构和方法，以改善电流模式逻辑（CML）驱动器的ESD稳健性
公开(公告)号：US09219055B2
公开(公告)日：2015-12-22
申请号：US13517849
申请日：2012-06-14
申请人： James P. Di Sarro , Robert J. Gauthier, Jr. , Nathan D. Jack , Jun Jun Li , Souvick Mitra
发明人： James P. Di Sarro , Robert J. Gauthier, Jr. , Nathan D. Jack , Jun Jun Li , Souvick Mitra
IPC分类号： H03K19/086 , H03K19/0175 , H01L27/02
CPC分类号： H02H9/005 , G06F17/5081 , H01L27/0251 , H01L27/0281 , H01L27/0285 , H02H9/04 , H02H9/046 , H03K17/687
摘要： An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.
摘要翻译：具有CML驱动器的集成电路，其包括驱动器偏置网络。第一输出焊盘和第二输出焊盘连接到电压焊盘。第一驱动器连接到第一输出焊盘和电压焊盘。第二驱动器连接到第二输出焊盘和电压焊盘。第一ESD电路连接到电压焊盘，第一输出焊盘和第一驱动器。第二ESD电路连接到电压焊盘，第二输出焊盘和第二驱动器。当在第一输出焊盘处发生ESD事件时，第一ESD电路将第一驱动器偏压到电压焊盘的电压，并且当在第二ESD处发生ESD事件时，第二ESD电路将第二驱动器偏压到电压焊盘的电压输出板。

3. 发明授权

US09058995B2 Self-protected drain-extended metal-oxide-semiconductor transistor 有权
标题翻译：自保护漏极扩展金属氧化物半导体晶体管
公开(公告)号：US09058995B2
公开(公告)日：2015-06-16
申请号：US13440514
申请日：2012-04-05
申请人： Robert J. Gauthier, Jr. , Junjun Li , Alain Loiseau
发明人： Robert J. Gauthier, Jr. , Junjun Li , Alain Loiseau
IPC分类号： H01L21/00 , H01L29/66 , H01L27/02 , H01L29/74 , H01L29/45 , H01L29/78 , H01L29/06
CPC分类号： H01L27/027 , H01L29/0692 , H01L29/456 , H01L29/7436 , H01L29/7824 , H01L29/7835
摘要： Device structures, design structures, and fabrication methods for a drain-extended metal-oxide-semiconductor (DEMOS) transistor. A first well of a first conductivity type and a second well of a second conductivity type are formed in a device region. The first and second wells are juxtaposed to define a p-n junction. A first doped region of the first conductivity type and a doped region of the second conductivity type are in the first well. The first doped region of the first conductivity type is separated from the second well by a first portion of the first well. The doped region of the second conductivity type is separated from the second well by a second portion of the first well. A second doped region of the first conductivity type, which is in the second well, is separated by a portion of the second well from the first and second portions of the first well.
摘要翻译：漏极延伸金属氧化物半导体（DEMOS）晶体管的器件结构，设计结构和制造方法。第一导电类型的第一阱和第二导电类型的第二阱形成在器件区域中。第一和第二井并列以定义p-n结。第一导电类型的第一掺杂区域和第二导电类型的掺杂区域位于第一阱中。第一导电类型的第一掺杂区域与第一阱的第一部分与第二阱分离。第二导电类型的掺杂区域与第一阱的第二部分与第二阱分离。在第二阱中的第一导电类型的第二掺杂区域由第一阱的第一和第二部分的第二阱的一部分分开。

4. 发明授权

US08815654B2 Vertical current controlled silicon on insulator (SOI) device such as a silicon controlled rectifier and method of forming vertical SOI current controlled devices 有权
标题翻译：垂直电流控制绝缘体上硅（SOI）器件，例如可控硅整流器，以及形成垂直SOI电流控制器件的方法
公开(公告)号：US08815654B2
公开(公告)日：2014-08-26
申请号：US11762811
申请日：2007-06-14
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Mahmoud A Mousa , Christopher S. Putnam
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Mahmoud A Mousa , Christopher S. Putnam
IPC分类号： H01L21/84 , H01L27/02
CPC分类号： H01L27/0262
摘要： A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.
摘要翻译：具有诸如垂直硅控制整流器（SCR），垂直双极晶体管，垂直电容器，电阻器和/或垂直钳位电阻器等器件的绝缘体硅（SOI）集成电路（IC）芯片及其制造方法 s）。器件通过SOI表面层和绝缘体层形成在晶种孔中。通过衬底中的种子孔形成例如N型的掩埋扩散。掺杂的外延层形成在掩埋扩散层上，并且可以包括多个掺杂层，例如P型层和N型层。可以在掺杂的外延层上形成多晶硅，例如P型。与埋入扩散部的接触形成在接触衬里中。

5. 发明授权

US08759194B2 Device structures compatible with fin-type field-effect transistor technologies 有权
标题翻译：器件结构与鳍式场效应晶体管技术相兼容
公开(公告)号：US08759194B2
公开(公告)日：2014-06-24
申请号：US13455732
申请日：2012-04-25
申请人： Robert J. Gauthier, Jr. , Jeffrey B. Johnson , Junjun Li
发明人： Robert J. Gauthier, Jr. , Jeffrey B. Johnson , Junjun Li
IPC分类号： H01L21/76
CPC分类号： H01L27/1211 , G06F17/5068 , H01L21/3086 , H01L21/845
摘要： Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.
摘要翻译：鳍式场效应晶体管集成电路技术的器件结构，设计结构和制造方法。构成器件结构的电极的第一和第二鳍片均由第一半导体材料构成。第二翅片邻近第一翅片形成以限定分隔第一和第二翅片的间隙。位于间隙中的是由第二半导体材料构成的层。

6. 发明授权

US08669146B2 Semiconductor structures with thinned junctions and methods of manufacture 有权
公开(公告)号：US08669146B2
公开(公告)日：2014-03-11
申请号：US13005560
申请日：2011-01-13
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L21/336
CPC分类号： H01L29/0688 , H01L27/0266 , H01L29/0615 , H01L29/66772 , H01L29/78621 , H01L29/78696
摘要： A method of forming a semiconductor structure, including forming a channel in a first portion of a semiconductor layer and forming a doped extension region in a second portion of the semiconductor layer abutting the channel on a first side and abutting an insulator material on a bottom side. The first portion of the semiconductor layer is thicker than the second portion of the semiconductor layer.

7. 发明申请

US20130141823A1 RC-Triggered ESD Clamp Device With Feedback for Time Constant Adjustment 有权
标题翻译： RC触发ESD钳位装置，具有时间常数调整反馈
公开(公告)号：US20130141823A1
公开(公告)日：2013-06-06
申请号：US13312047
申请日：2011-12-06
申请人： James P. Di Sarro , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra
发明人： James P. Di Sarro , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra
IPC分类号： H02H9/04 , G06F17/50
CPC分类号： H02H9/046
摘要： Methods for responding to an electrostatic discharge (ESD) event on a voltage rail, ESD protection circuits, and design structures for an ESD protection circuit. An RC network of the ESD protection circuit includes a capacitor coupled to a field effect transistor at a node. The node of the RC network is coupled with an input of the inverter. The field-effect transistor is coupled with an output of the inverter. In response to an ESD event, a trigger signal is supplied from the RC network to the input of the inverter, which drives a clamp device to discharge current from the ESD event from the voltage rail. An RC time constant of the RC network is increased in response to the ESD event to sustain the discharge of the current by the clamp device.
摘要翻译：用于响应电压轨上的静电放电（ESD）事件，ESD保护电路以及ESD保护电路的设计结构的方法。 ESD保护电路的RC网络包括耦合到节点处的场效应晶体管的电容器。 RC网络的节点与逆变器的输入端相连。场效应晶体管与反相器的输出端相连。响应于ESD事件，触发信号从RC网络提供给逆变器的输入，该驱动器驱动钳位装置以从ESD电压放电来自电压轨。响应于ESD事件，RC网络的RC时间常数增加以维持钳位装置的电流放电。

8. 发明授权

US08384125B2 Structure and method for a silicon controlled rectifier (SCR) structure for SOI technology 有权
标题翻译：用于SOI技术的可控硅整流器（SCR）结构的结构和方法
公开(公告)号：US08384125B2
公开(公告)日：2013-02-26
申请号：US13035549
申请日：2011-02-25
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra
IPC分类号： H01L29/66
CPC分类号： H01L29/7436 , H01L27/0259 , H01L29/861
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括一个P + -N体二极管和一个N + -P体二极管。 P + -N体二极管和N + -P体二极管横向集成。

9. 发明授权

US08373956B2 Low leakage electrostatic discharge protection circuit 失效
标题翻译：低泄漏静电放电保护电路
公开(公告)号：US08373956B2
公开(公告)日：2013-02-12
申请号：US12943980
申请日：2010-11-11
申请人： Michel J. Abou-Khalil , Kiran V. Chatty , Chee Kwang Quek , Robert J. Gauthier, Jr. , Nathaniel Peachey
发明人： Michel J. Abou-Khalil , Kiran V. Chatty , Chee Kwang Quek , Robert J. Gauthier, Jr. , Nathaniel Peachey
IPC分类号： H02H9/00 , H02H1/00 , H02H1/04 , H02H3/22 , H02H9/06
CPC分类号： H02H9/046
摘要： A circuit and method for electrostatic discharge (ESD) protection. The ESD protection circuit includes: a silicon control rectifier (SCR) connected between a first voltage rail and a second voltage rail; one or more diodes connected in series in a forward conduction direction between the first voltage rail and a source of a p-channel field effect transistor (PFET); a drain of the PFET connected to the SCR and connected to ground through a current trigger device; and a control circuit connected to the gate of the PFET.
摘要翻译：一种用于静电放电（ESD）保护的电路和方法。 ESD保护电路包括：连接在第一电压轨和第二电压轨之间的硅控制整流器（SCR）; 在第一电压轨和p沟道场效应晶体管（PFET）的源极之间沿正向传导方向串联连接的一个或多个二极管; 连接到SCR的PFET的漏极通过电流触发装置连接到地; 以及连接到PFET的栅极的控制电路。

10. 发明授权

US08363367B2 Electrical overstress protection circuit 有权
标题翻译：电气过载保护电路
公开(公告)号：US08363367B2
公开(公告)日：2013-01-29
申请号：US12632015
申请日：2009-12-07
申请人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
发明人： John B. Campi, Jr. , Shunhua T. Chang , Kiran V. Chatty , Robert J. Gauthier, Jr. , Junjun Li , Mujahid Muhammad
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , G06F17/5045
摘要： A semiconductor circuit for electric overstress (EOS) protection is provided. The semiconductor circuit employs an electrostatic discharge (ESD) protection circuit, which has a resistor-capacitor (RC) time-delay network connected to a discharge capacitor. An electronic component that has voltage snapback property or a diodic behavior is connected to alter the logic state of the gate of the discharge transistor under an EOS event. Particularly, the electronic component is configured to turn on the gate of the discharge capacitor throughout the duration of an electrical overstress (EOS) condition as well as throughout the duration of an ESD event. A design structure may be employed to design or manufacture a semiconductor circuit that provides protection against an EOS condition without time limitation, i.e., without being limited by the time constant of the RC time delay network for EOS events that last longer than 1 microsecond.
摘要翻译：提供了一种用于电力过应力（EOS）保护的半导体电路。半导体电路采用静电放电（ESD）保护电路，其具有连接到放电电容器的电阻 - 电容（RC）延时网络。连接具有电压骤回特性或二极管行为的电子部件，以改变在EOS事件下放电晶体管的栅极的逻辑状态。特别地，电子部件被配置成在电应力（EOS）条件以及ESD事件的整个持续时间期间打开放电电容器的栅极。可以采用设计结构来设计或制造半导体电路，该半导体电路在没有时间限制的情况下提供针对EOS状态的保护，即不受时间长度超过1微秒的EOS事件的RC时间延迟网络的时间常数的限制。

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