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1. 发明授权

US08039334B2 Shared gate for conventional planar device and horizontal CNT 有权
标题翻译：常规平面器件和水平CNT的共用门
公开(公告)号：US08039334B2
公开(公告)日：2011-10-18
申请号：US12902944
申请日：2010-10-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
IPC分类号： H01L21/8234
CPC分类号： H01L21/823412 , B01J23/74 , B01J37/0238 , B82Y10/00 , H01L21/7624 , H01L21/823437 , H01L27/286 , H01L51/0048 , H01L51/0545 , H01L51/055 , Y10S977/742 , Y10S977/762 , Y10S977/763
摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
摘要翻译：在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管晶体管位于至少一个平面半导体器件的栅极之上。

2. 发明授权

US07247877B2 Integrated carbon nanotube sensors 失效
标题翻译：集成碳纳米管传感器
公开(公告)号：US07247877B2
公开(公告)日：2007-07-24
申请号：US10711083
申请日：2004-08-20
申请人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
发明人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
IPC分类号： H01L31/072 , H01L23/48
CPC分类号： H01L29/0665 , B82Y10/00 , G01R31/2884 , H01L27/088 , H01L27/286 , H01L29/0673 , H01L29/78 , H01L51/0048 , H01L51/0512 , Y10S977/761 , Y10S977/762 , Y10S977/765
摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
摘要翻译：一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。此外，CNT FET适用于检测集成电路内的故障电路。

3. 发明授权

US07838943B2 Shared gate for conventional planar device and horizontal CNT 有权
标题翻译：常规平面器件和水平CNT的共用门
公开(公告)号：US07838943B2
公开(公告)日：2010-11-23
申请号：US11161146
申请日：2005-07-25
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
IPC分类号： H01L21/70
CPC分类号： H01L21/823412 , B01J23/74 , B01J37/0238 , B82Y10/00 , H01L21/7624 , H01L21/823437 , H01L27/286 , H01L51/0048 , H01L51/0545 , H01L51/055 , Y10S977/742 , Y10S977/762 , Y10S977/763
摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
摘要翻译：在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管晶体管位于至少一个平面半导体器件的栅极之上。

4. 发明授权

US07484423B2 Integrated carbon nanotube sensors 失效
标题翻译：集成碳纳米管传感器
公开(公告)号：US07484423B2
公开(公告)日：2009-02-03
申请号：US11696370
申请日：2007-04-04
申请人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
发明人： Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , David P. Vallett
IPC分类号： G01B7/16 , G01L1/00 , H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , G01R31/2884 , H01L27/088 , H01L27/286 , H01L29/0673 , H01L29/78 , H01L51/0048 , H01L51/0512 , Y10S977/761 , Y10S977/762 , Y10S977/765
摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
摘要翻译：一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。此外，CNT FET适用于检测集成电路内的故障电路。

5. 发明授权

US06627926B2 Method of designing and structure for visual and electrical test of semiconductor devices 有权
标题翻译：半导体器件视觉和电气测试的设计和结构方法
公开(公告)号：US06627926B2
公开(公告)日：2003-09-30
申请号：US09788631
申请日：2001-02-16
申请人： Thomas J. Hartswick , Mark E. Masters
发明人： Thomas J. Hartswick , Mark E. Masters
IPC分类号： H01L2710
CPC分类号： H01L22/32 , H01L23/522 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels for visual inspection. Also, in accordance with the invention, selected aligned fill shapes are interconnected with vias to form conductive stacks for contacting lower wiring level conductive wires from upper wiring levels in order to perform electrical test probing/diagnostics.
摘要翻译：在使用并入布线层的填充形状图形以增加布线层的平面度的半导体器件中，填充形状从一个布线级别对准到另一布线级别，以提供用于目视检查的较低布线级别的视线。此外，根据本发明，选定的对齐填充形状与通孔互连以形成导电叠层，用于接触来自上布线层的下布线层导电线，以便进行电测试探测/诊断。

6. 发明授权

US08536526B2 Methods of operating a nanoprober to electrically probe a device structure of an integrated circuit 失效
标题翻译：操作纳米光栅以电探测集成电路的器件结构的方法
公开(公告)号：US08536526B2
公开(公告)日：2013-09-17
申请号：US12344651
申请日：2008-12-29
申请人： Paul D. Bell , Mark E. Masters , David S. Patrick
发明人： Paul D. Bell , Mark E. Masters , David S. Patrick
IPC分类号： G01N23/00
CPC分类号： H01J37/268 , G01R31/307 , H01J37/265 , H01J2237/043 , H01J2237/24564 , H01J2237/24592
摘要： Methods for nanoprobing a device structure of an integrated circuit. The method may include scanning a primary charged particle beam across a first region of the device structure with at least one probe proximate to the first region and a second region of the device structure is masked from the primary charged particle beam. The method may further include collecting secondary electrons emitted from the first region of the device structure and the at least one probe to form a secondary electron image. The secondary electron image includes the first region and the at least one probe as imaged portions and the second region as a non-imaged portion. Alternatively, the second region may be scanned by the charged particle beam at a faster scan rate than the first region so that the second region is also an imaged portion of the secondary electron image.
摘要翻译：用于纳米结构的集成电路的器件结构的方法。该方法可以包括利用靠近第一区域的至少一个探针扫描穿过器件结构的第一区域的初级带电粒子束，并且器件结构的第二区域被从初级带电粒子束掩蔽。该方法还可以包括收集从器件结构的第一区域发射的二次电子和至少一个探针以形成二次电子图像。二次电子图像包括作为成像部分的第一区域和至少一个探针，以及作为非成像部分的第二区域。或者，第二区域可以以比第一区域更快的扫描速率被带电粒子束扫描，使得第二区域也是二次电子图像的成像部分。

7. 发明申请

US20100163727A1 METHODS OF OPERATING A NANOPROBER TO ELECTRICALLY PROBE A DEVICE STRUCTURE OF AN INTEGRATED CIRCUIT 失效
标题翻译：操作纳米电极的方法来电子地探测集成电路的器件结构
公开(公告)号：US20100163727A1
公开(公告)日：2010-07-01
申请号：US12344651
申请日：2008-12-29
申请人： Paul D. Bell , Mark E. Masters , David S. Patrick
发明人： Paul D. Bell , Mark E. Masters , David S. Patrick
IPC分类号： G01N23/00
CPC分类号： H01J37/268 , G01R31/307 , H01J37/265 , H01J2237/043 , H01J2237/24564 , H01J2237/24592
摘要： Methods for nanoprobing a device structure of an integrated circuit. The method may include scanning a primary charged particle beam across a first region of the device structure with at least one probe proximate to the first region and a second region of the device structure is masked from the primary charged particle beam. The method may further include collecting secondary electrons emitted from the first region of the device structure and the at least one probe to form a secondary electron image. The secondary electron image includes the first region and the at least one probe as imaged portions and the second region as a non-imaged portion. Alternatively, the second region may be scanned by the charged particle beam at a faster scan rate than the first region so that the second region is also an imaged portion of the secondary electron image.
摘要翻译：用于纳米结构的集成电路的器件结构的方法。该方法可以包括利用靠近第一区域的至少一个探针扫描穿过器件结构的第一区域的初级带电粒子束，并且器件结构的第二区域被从初级带电粒子束掩蔽。该方法还可以包括收集从器件结构的第一区域发射的二次电子和至少一个探针以形成二次电子图像。二次电子图像包括作为成像部分的第一区域和至少一个探针，以及作为非成像部分的第二区域。或者，第二区域可以以比第一区域更快的扫描速率被带电粒子束扫描，使得第二区域也是二次电子图像的成像部分。

8. 发明授权

US07535016B2 Vertical carbon nanotube transistor integration 有权
标题翻译：垂直碳纳米管晶体管集成
公开(公告)号：US07535016B2
公开(公告)日：2009-05-19
申请号：US10906016
申请日：2005-01-31
申请人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , Charles W. Koburger, III , Mark E. Masters , Peter H. Mitchell
发明人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , Charles W. Koburger, III , Mark E. Masters , Peter H. Mitchell
IPC分类号： H01L29/15 , H01L51/30
CPC分类号： H01L27/0688 , B82Y10/00 , H01L21/823412 , H01L21/823425 , H01L21/823487 , H01L27/0705 , H01L27/286 , H01L51/0048 , H01L51/057 , Y10S977/938
摘要： A hybrid semiconductor structure which includes a horizontal semiconductor device and a vertical carbon nanotube transistor, where the vertical carbon nanotube transistor and the horizontal semiconductor device have at least one shared node is provided. The at least one shared node can include, for example, a drain, source or gate electrode of a FET, or an emitter, collector, or base of a bipolar transistor.
摘要翻译：提供一种混合半导体结构，其包括水平半导体器件和垂直碳纳米管晶体管，其中垂直碳纳米管晶体管和水平半导体器件具有至少一个共享节点。至少一个共享节点可以包括例如FET的漏极，源极或栅极电极，或双极晶体管的发射极，集电极或基极。

9. 发明申请

US20110027951A1 SHARED GATE FOR CONVENTIONAL PLANAR DEVICE AND HORIZONTAL CNT 有权
标题翻译：常规平面设备和水平CNT的共享门
公开(公告)号：US20110027951A1
公开(公告)日：2011-02-03
申请号：US12902944
申请日：2010-10-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
IPC分类号： H01L21/8234
CPC分类号： H01L21/823412 , B01J23/74 , B01J37/0238 , B82Y10/00 , H01L21/7624 , H01L21/823437 , H01L27/286 , H01L51/0048 , H01L51/0545 , H01L51/055 , Y10S977/742 , Y10S977/762 , Y10S977/763
摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
摘要翻译：在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管晶体管位于至少一个平面半导体器件的栅极之上。

10. 发明授权

US07089138B1 Canary device for failure analysis 失效
标题翻译：金丝雀装置进行故障分析
公开(公告)号：US07089138B1
公开(公告)日：2006-08-08
申请号：US10906590
申请日：2005-02-25
申请人： Pierre J. Bouchard , Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , James A. Slinkman , David P. Vallett
发明人： Pierre J. Bouchard , Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , James A. Slinkman , David P. Vallett
IPC分类号： G06F11/00
CPC分类号： G01R31/2856 , G01R31/2831 , G01R31/318511 , G01R31/3187
摘要： A diagnostic system and method for testing an integrated circuit during fabrication thereof. The diagnostic system has at least one integrated circuit chip that has an electrical signature associated with it; a sacrificial circuit that is adjacent to the integrated circuit chip and has a known electrical signature associated with it and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit indicates that the integrated circuit chip is mis-designed. The diagnostic system further includes a semiconductor wafer that has a plurality of integrated circuit chips and a kerf area separating one integrated circuit chip from another integrated circuit chip. A mis-designed integrated circuit chip has abnormally functioning circuitry.
摘要翻译：一种在其制造期间测试集成电路的诊断系统和方法。诊断系统具有至少一个具有与其相关联的电特征的集成电路芯片; 牺牲电路，其与集成电路芯片相邻并且具有与其相关联的已知电气签名和故意错误设计的电路; 以及比较器，用于将集成电路芯片的电特征与牺牲电路的已知电特征进行比较，其中集成电路芯片的电特征中与牺牲电路的已知电气签名的匹配指示集成电路芯片设计错误。诊断系统还包括具有多个集成电路芯片的半导体晶片和将一个集成电路芯片与另一个集成电路芯片分离的切口区域。错误设计的集成电路芯片具有异常功能的电路。

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