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1. 发明授权

US07977201B2 Methods for forming back-end-of-line resistive semiconductor structures 有权
标题翻译：形成后端电阻半导体结构的方法
公开(公告)号：US07977201B2
公开(公告)日：2011-07-12
申请号：US12191633
申请日：2008-08-14
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
IPC分类号： H01L21/20
CPC分类号： H01L23/5228 , H01L21/76816 , H01L23/5226 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.
摘要翻译：在一个实施例中，嵌入在第二介电层中的第二金属线覆盖在嵌入第一介电层中的第一金属线上。覆盖第一金属线的第二电介质层的一部分是使用光致抗蚀剂凹陷的，而第二金属线作为蚀刻掩模。在凹槽内形成掺杂半导体衬垫，以在第一金属线和第二金属线之间提供电阻连接。在另一个实施例中，第一金属线和第二金属线嵌入在电介质层中。使用光致抗蚀剂和第一和第二金属线作为蚀刻掩模来凹入与第一和第二金属线横向邻接的电介质层的区域。掺杂半导体衬垫形成在第一和第二金属线的侧壁上，提供第一和第二金属线之间的电阻连接。

2. 发明申请

US20090325337A1 Band Gap Modulated Optical Sensor 有权
标题翻译：带间隙调制光学传感器
公开(公告)号：US20090325337A1
公开(公告)日：2009-12-31
申请号：US12146560
申请日：2008-06-26
申请人： Kangguo Cheng , Toshiharu Furukawa , Robert Robison , William R. Tonti
发明人： Kangguo Cheng , Toshiharu Furukawa , Robert Robison , William R. Tonti
IPC分类号： H01L31/0336 , H01L31/0232
CPC分类号： H01L27/1461 , H01L27/14645 , H01L27/14689
摘要： A complementary metal-oxide-semiconductor (CMOS) optical sensor structure comprises a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data.
摘要翻译：互补金属氧化物半导体（CMOS）光学传感器结构包括含有与半导体衬底中的半导体层相同的半导体材料的电荷收集阱的像素，以及包含不同半导体材料的另一电荷收集阱的至少另一个像素半导体层的材料。电荷收集阱具有不同的带隙，因此响应于具有不同波长的光而产生电荷载流子。因此，CMOS传感器结构包括响应于不同波长的光的至少两个像素，使得能够对光学数据进行波长敏感或颜色敏感的捕获。

3. 发明申请

US20090321786A1 Band Gap Modulated Optical Sensor 有权
标题翻译：带间隙调制光学传感器
公开(公告)号：US20090321786A1
公开(公告)日：2009-12-31
申请号：US12146575
申请日：2008-06-26
申请人： Kangguo Cheng , Toshiharu Furukawa , Robert Robison , William R. Tonti
发明人： Kangguo Cheng , Toshiharu Furukawa , Robert Robison , William R. Tonti
IPC分类号： H01L27/146
CPC分类号： H01L27/14645 , H01L27/14627
摘要： A complementary metal-oxide-semiconductor (CMOS) optical sensor structure comprises a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data. Further, a design structure for the inventive complementary metal-oxide-semiconductor (CMOS) image sensor is also provided.
摘要翻译：互补金属氧化物半导体（CMOS）光学传感器结构包括含有与半导体衬底中的半导体层相同的半导体材料的电荷收集阱的像素，以及包含不同半导体材料的另一电荷收集阱的至少另一个像素半导体层的材料。电荷收集阱具有不同的带隙，因此响应于具有不同波长的光而产生电荷载流子。因此，CMOS传感器结构包括响应于不同波长的光的至少两个像素，使得能够对光学数据进行波长敏感或颜色敏感的捕获。此外，还提供了本发明的互补金属氧化物半导体（CMOS）图像传感器的设计结构。

4. 发明申请

US20110161896A1 BACK-END-OF-LINE RESISTIVE SEMICONDUCTOR STRUCTURES 审中-公开
标题翻译：后端电阻半导体结构
公开(公告)号：US20110161896A1
公开(公告)日：2011-06-30
申请号：US13042947
申请日：2011-03-08
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
IPC分类号： G06F17/50
CPC分类号： H01L27/115 , H01L23/5256 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.
摘要翻译：在一个实施例中，后端行（BEOL）电阻结构包括嵌入在第二电介质层中的第二金属线，并且覆盖嵌入在第一介电层中的第一金属线。横向邻接第二金属线的侧壁并垂直邻接第一金属线的顶表面的掺杂半导体间隔物或插塞提供第一和第二金属线之间的电阻连接。在另一个实施例中，另一个BEOL电阻结构包括第一金属线，第二金属线嵌入电介质层。横向邻接第一和第二金属线的侧壁的掺杂半导体间隔件或插塞提供第一和第二金属线之间的电阻连接。

5. 发明授权

US07939911B2 Back-end-of-line resistive semiconductor structures 有权
标题翻译：后端电阻半导体结构
公开(公告)号：US07939911B2
公开(公告)日：2011-05-10
申请号：US12191683
申请日：2008-08-14
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L27/115 , H01L23/5256 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.
摘要翻译：在一个实施例中，后端行（BEOL）电阻结构包括嵌入在第二电介质层中的第二金属线，并且覆盖嵌入在第一介电层中的第一金属线。横向邻接第二金属线的侧壁并垂直邻接第一金属线的顶表面的掺杂半导体间隔物或插塞提供第一和第二金属线之间的电阻连接。在另一个实施例中，另一个BEOL电阻结构包括第一金属线，第二金属线嵌入电介质层。横向邻接第一和第二金属线的侧壁的掺杂半导体间隔件或插塞提供第一和第二金属线之间的电阻连接。

6. 发明授权

US08686508B2 Structures, methods and applications for electrical pulse anneal processes 失效
标题翻译：电脉冲退火工艺的结构，方法和应用
公开(公告)号：US08686508B2
公开(公告)日：2014-04-01
申请号：US12553523
申请日：2009-09-03
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , Robert Robison
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , Robert Robison
IPC分类号： H01L23/62
CPC分类号： H01L21/324 , H01L27/0255 , H01L29/8611 , H01L29/866
摘要： Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.
摘要翻译：为纳秒电脉冲退火工艺提供了结构和方法。形成静电放电（ESD）N + / P +结构的方法包括在衬底上形成N +扩散，并在衬底上形成P +扩散。 P +扩散与N +扩散电接触。该方法还包括在N +扩散和P +扩散之间形成器件。退火结构或材料的方法包括跨多个纳秒的静电放电（ESD）N + / P +结构施加电脉冲。

7. 发明授权

US08482075B2 Structure and method for manufacturing asymmetric devices 有权
标题翻译：用于制造不对称装置的结构和方法
公开(公告)号：US08482075B2
公开(公告)日：2013-07-09
申请号：US13468270
申请日：2012-05-10
申请人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert Robison
发明人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert Robison
IPC分类号： H01L21/70
CPC分类号： H01L21/26586 , H01L29/1083 , H01L29/66492 , H01L29/66545 , H01L29/66659
摘要： A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.
摘要翻译：在基板上形成多个栅极结构。每个栅极结构包括第一栅极电极和源极和漏极区域。从每个栅极结构去除第一栅电极。施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。去除第一光致抗蚀剂。施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。去除第二光致抗蚀剂。在每个栅极结构中形成替代栅电极。

8. 发明授权

US07888266B2 Band gap modulated optical sensor 有权
标题翻译：带隙调制光传感器
公开(公告)号：US07888266B2
公开(公告)日：2011-02-15
申请号：US12146560
申请日：2008-06-26
申请人： Kangguo Cheng , Toshiharu Furukawa , Robert Robison , William R. Tonti
发明人： Kangguo Cheng , Toshiharu Furukawa , Robert Robison , William R. Tonti
IPC分类号： H01L21/311
CPC分类号： H01L27/1461 , H01L27/14645 , H01L27/14689
摘要： A complementary metal-oxide-semiconductor (CMOS) optical sensor structure includes a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data.
摘要翻译：互补金属氧化物半导体（CMOS）光学传感器结构包括含有与半导体衬底中的半导体层相同的半导体材料的电荷收集阱的像素，以及包含不同半导体材料的另一电荷收集阱的至少另一个像素半导体层的材料。电荷收集阱具有不同的带隙，因此响应于具有不同波长的光而产生电荷载流子。因此，CMOS传感器结构包括响应于不同波长的光的至少两个像素，使得能够对光学数据进行波长敏感或颜色敏感的捕获。

9. 发明申请

US20100038754A1 Back-End-of-Line Resistive Semiconductor Structures 有权
标题翻译：后端电阻半导体结构
公开(公告)号：US20100038754A1
公开(公告)日：2010-02-18
申请号：US12191683
申请日：2008-08-14
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert Robison , Yun Shi , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L27/115 , H01L23/5256 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.
摘要翻译：在一个实施例中，后端行（BEOL）电阻结构包括嵌入在第二电介质层中的第二金属线，并且覆盖嵌入在第一介电层中的第一金属线。横向邻接第二金属线的侧壁并垂直邻接第一金属线的顶表面的掺杂半导体间隔物或插塞提供第一和第二金属线之间的电阻连接。在另一个实施例中，另一个BEOL电阻结构包括第一金属线，第二金属线嵌入电介质层。横向邻接第一和第二金属线的侧壁的掺杂半导体间隔件或插塞提供第一和第二金属线之间的电阻连接。

10. 发明授权

US07855110B2 Field effect transistor and method of fabricating same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US07855110B2
公开(公告)日：2010-12-21
申请号：US12169118
申请日：2008-07-08
申请人： Viorel Ontalus , Robert Robison
发明人： Viorel Ontalus , Robert Robison
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L29/1083 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An FET and method of fabricating an FET. The method includes forming a gate dielectric layer on a top surface of a silicon region of a substrate and forming a gate electrode on a top surface of the gate dielectric layer; forming a source and a drain in the silicon region and separated by a channel region under the gate electrode, the source having a source extension extending under the gate electrode and the drain having a drain extension extending under the gate electrode, the source, source extension, drain and drain extension doped a first type; and forming a source delta region contained entirely within the source and forming a drain delta region contained entirely within the drain, the delta source region and the delta drain region doped a second dopant type, the second dopant type opposite from the first dopant type.
摘要翻译：一种FET及其制造方法。该方法包括在衬底的硅区的顶表面上形成栅电介质层，并在栅电介质层的顶表面上形成栅电极; 在硅区域中形成源极和漏极，并由栅电极下方的沟道区分隔开，源极具有在栅极下延伸的源极延伸，漏极具有在栅电极下延伸的漏极延伸，源极，源极延伸，漏极和漏极延伸掺杂第一类型; 以及形成完全在所述源内包含的源极三角洲区域，并且形成完全在所述漏极内包含的漏极三角洲区域，所述δ源极区域和所述δ漏极区域掺杂第二掺杂剂类型，所述第二掺杂剂类型与所述第一掺杂剂类型相反。

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