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1. 发明授权

US07936017B2 Reduced floating body effect without impact on performance-enhancing stress 有权
标题翻译：降低浮体效应，而不影响性能增强应力
公开(公告)号：US07936017B2
公开(公告)日：2011-05-03
申请号：US12120836
申请日：2008-05-15
申请人： William F. Clark, Jr. , Toshiharu Furukawa , Xuefeng Hua , Charles W. Koburger, III , Robert R. Robison
发明人： William F. Clark, Jr. , Toshiharu Furukawa , Xuefeng Hua , Charles W. Koburger, III , Robert R. Robison
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/165 , H01L29/665 , H01L29/66772 , H01L29/7848 , H01L29/78612 , H01L29/78621
摘要： A method, gated device and design structure are presented for providing reduced floating body effect (FBE) while not impacting performance enhancing stress. One method includes forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another portion of the damaged portion at least adjacent to a channel region; and substantially filling the trench with a material to form a source/drain region.
摘要翻译：提出了一种方法，选通装置和设计结构，用于提供减少的浮体效应（FBE），同时不影响性能增强应力。一种方法包括在与栅极相邻的衬底的一部分中形成损伤; 去除损坏部分的一部分以形成沟槽，将损坏部分的另一部分至少邻近沟道区域; 并且用材料基本上填充沟槽以形成源极/漏极区域。

2. 发明申请

US20090283828A1 Reduced Floating Body Effect Without Impact on Performance-Enhancing Stress 有权
标题翻译：减少浮体效应，而不影响性能增强应力
公开(公告)号：US20090283828A1
公开(公告)日：2009-11-19
申请号：US12120836
申请日：2008-05-15
申请人： William F. Clark, JR. , Toshiharu Furukawa , Xuefeng Hua , Charles W. Koburger, III , Robert R. Robison
发明人： William F. Clark, JR. , Toshiharu Furukawa , Xuefeng Hua , Charles W. Koburger, III , Robert R. Robison
IPC分类号： H01L29/786 , H01L21/425 , G06F17/50
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/165 , H01L29/665 , H01L29/66772 , H01L29/7848 , H01L29/78612 , H01L29/78621
摘要： A method, gated device and design structure are presented for providing reduced floating body effect (FBE) while not impacting performance enhancing stress. One method includes forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another portion of the damaged portion at least adjacent to a channel region; and substantially filling the trench with a material to form a source/drain region.
摘要翻译：提出了一种方法，选通装置和设计结构，用于提供减少的浮体效应（FBE），同时不影响性能增强应力。一种方法包括在与栅极相邻的衬底的一部分中形成损伤; 去除损坏部分的一部分以形成沟槽，将损坏部分的另一部分至少邻近沟道区域; 并且用材料基本上填充沟槽以形成源极/漏极区域。

3. 发明申请

US20120098087A1 FORMING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER 审中-公开
标题翻译：形成极薄的半导体绝缘体（ETSOI）层
公开(公告)号：US20120098087A1
公开(公告)日：2012-04-26
申请号：US13342423
申请日：2012-01-03
申请人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L27/12 , H01L21/306 , H01L21/3065 , H01L21/265
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

4. 发明申请

US20110095366A1 FORMING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER 有权
标题翻译：形成极薄的半导体绝缘体（ETSOI）层
公开(公告)号：US20110095366A1
公开(公告)日：2011-04-28
申请号：US12603737
申请日：2009-10-22
申请人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L29/786 , H01L21/762 , H01L29/02
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：公开了用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

5. 发明授权

US08610211B2 Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structure 有权
标题翻译：绝缘体上半导体（SOI）结构，具有选择性放置的亚绝缘体层空穴和形成SOI结构的方法
公开(公告)号：US08610211B2
公开(公告)日：2013-12-17
申请号：US12842146
申请日：2010-07-23
申请人： Toshiharu Furukawa , Robert R. Robison , Richard Q. Williams
发明人： Toshiharu Furukawa , Robert R. Robison , Richard Q. Williams
IPC分类号： H01L27/12
CPC分类号： H01L29/66477 , H01L21/02104 , H01L21/84 , H01L27/1203 , H01L29/78648 , H01L29/78654
摘要： Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure.
摘要翻译：公开了一种绝缘体半导体（SOI）结构，其具有选择性地放置在衬底中的次绝缘体层空穴，使得半导体层的第一部分与衬底之间的电容耦合将小于第二半导体层和衬底的截面。第一部分可以包含绝缘体层上的第一器件，第二部分可以在绝缘体层上包含第二器件。或者，第一和第二部分可以包括绝缘体层上相同器件的不同区域。例如，在SOI场效应晶体管（FET）中，可以将子绝缘体层空隙选择性地放置在源极，漏极和/或体接触扩散区域下方的衬底中，但不能在沟道区域下方，使得电容耦合这些各种扩散区域和衬底将小于沟道区域和衬底之间的电容耦合。此外，公开了形成这种SOI结构的相关方法。

6. 发明申请

US20110115054A1 SEMISPHERICAL INTEGRATED CIRCUIT STRUCTURES 有权
标题翻译：半导体集成电路结构
公开(公告)号：US20110115054A1
公开(公告)日：2011-05-19
申请号：US12621956
申请日：2009-11-19
申请人： Kangguo Cheng , Toshiharu Furukawa , Robert R. Robison , William R. Tonti , Richard Q. Williams
发明人： Kangguo Cheng , Toshiharu Furukawa , Robert R. Robison , William R. Tonti , Richard Q. Williams
IPC分类号： H01L29/73 , H01L29/06 , H01L21/331
CPC分类号： H01L31/03529 , H01L27/14643 , H01L29/0657 , H01L29/6609 , H01L29/66136 , H01L29/66234 , H01L29/732 , H01L29/8611 , H01L29/868 , H01L31/0352 , H01L31/103 , Y02E10/50
摘要： A diode comprises a substrate formed of a first material having a first doping polarity. The substrate has a planar surface and at least one semispherical structure extending from the planar surface. The semispherical structure is formed of the first material. A layer of second material is over the semispherical structure. The second material comprises a second doping polarity opposite the first doping polarity. The layer of second material conforms to the shape of the semispherical structure. A first electrical contact is connected to the substrate, and a second electrical contact is connected to the layer of second material. Additional semiconductor structures are formed by fabricating additional layers over the original layers.
摘要翻译：二极管包括由具有第一掺杂极性的第一材料形成的衬底。衬底具有平坦表面和从平面表面延伸的至少一个半球形结构。半球形结构由第一材料形成。第二材料层在半球形结构之上。第二材料包括与第一掺杂极性相反的第二掺杂极性。第二材料层符合半球形结构的形状。第一电触头连接到基板，第二电触点连接到第二材料层。通过在原始层上制造附加层来形成附加的半导体结构。

7. 发明授权

US08110483B2 Forming an extremely thin semiconductor-on-insulator (ETSOI) layer 有权
标题翻译：形成极薄的绝缘体上半导体（ETSOI）层
公开(公告)号：US08110483B2
公开(公告)日：2012-02-07
申请号：US12603737
申请日：2009-10-22
申请人： Wagdi W. Abadeer , Lilian Kamal, legal representative , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：公开了用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

8. 发明申请

US20120018806A1 SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE WITH SELECTIVELY PLACED SUB-INSULATOR LAYER VOID(S) AND METHOD OF FORMING THE SOI STRUCTURE 有权
标题翻译：具有选择性的绝缘子层绝缘体的半导体绝缘体（SOI）结构和形成SOI结构的方法
公开(公告)号：US20120018806A1
公开(公告)日：2012-01-26
申请号：US12842146
申请日：2010-07-23
申请人： Toshiharu Furukawa , Robert R. Robison , Richard Q. Williams
发明人： Toshiharu Furukawa , Robert R. Robison , Richard Q. Williams
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/66477 , H01L21/02104 , H01L21/84 , H01L27/1203 , H01L29/78648 , H01L29/78654
摘要： Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure.
摘要翻译：公开了一种绝缘体半导体（SOI）结构，其具有选择性地放置在衬底中的次绝缘体层空穴，使得半导体层的第一部分与衬底之间的电容耦合将小于第二半导体层和衬底的截面。第一部分可以包含绝缘体层上的第一器件，第二部分可以在绝缘体层上包含第二器件。或者，第一和第二部分可以包括绝缘体层上相同器件的不同区域。例如，在SOI场效应晶体管（FET）中，可以将子绝缘体层空隙选择性地放置在源极，漏极和/或体接触扩散区域下方的衬底中，但不能在沟道区域下方，使得电容耦合这些各种扩散区域和衬底将小于沟道区域和衬底之间的电容耦合。此外，公开了形成这种SOI结构的相关方法。

9. 发明申请

US20110095393A1 CREATING EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) HAVING SUBSTANTIALLY UNIFORM THICKNESS 有权
标题翻译：创造出具有重大均匀厚度的极细半导体绝缘体（ETSOI）
公开(公告)号：US20110095393A1
公开(公告)日：2011-04-28
申请号：US12603668
申请日：2009-10-22
申请人： Nathaniel C. Berliner , Kangguo Cheng , Jason E. Cummings , Toshiharu Furukawa , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Nathaniel C. Berliner , Kangguo Cheng , Jason E. Cummings , Toshiharu Furukawa , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L29/06 , H01L21/66 , C23F1/08
CPC分类号： H01L21/7624 , H01L21/30625 , H01L22/12 , H01L22/20 , H01L2924/0002 , Y10S438/959 , H01L2924/00
摘要： An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.
摘要翻译：通过测量晶片上的多个选定点处的半导体层厚度，制造出具有基本上均匀的厚度的极薄的绝缘体上半导体（ETSOI）晶片; 确定在所述多个选择点中的每一个处要除去的去除厚度，使得所述去除厚度的去除导致基本上均匀的晶片内半导体层厚度; 基于各个点的去除厚度，以剂量水平和能量水平中的至少一个将多个选择点中的每一个植入种子到晶片; 并抛光半导体层以使半导体层变薄。

10. 发明授权

US09018024B2 Creating extremely thin semiconductor-on-insulator (ETSOI) having substantially uniform thickness 有权
标题翻译：制造具有基本上均匀厚度的非常薄的绝缘体上绝缘体（ETSOI）
公开(公告)号：US09018024B2
公开(公告)日：2015-04-28
申请号：US12603668
申请日：2009-10-22
申请人： Nathaniel C. Berliner , Kangguo Cheng , Jason E. Cummings , Toshiharu Furukawa , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Nathaniel C. Berliner , Kangguo Cheng , Jason E. Cummings , Toshiharu Furukawa , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L21/66 , H01L21/762 , H01L21/306
CPC分类号： H01L21/7624 , H01L21/30625 , H01L22/12 , H01L22/20 , H01L2924/0002 , Y10S438/959 , H01L2924/00
摘要： An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.
摘要翻译：通过测量晶片上的多个选定点处的半导体层厚度，制造出具有基本上均匀的厚度的极薄的绝缘体上半导体（ETSOI）晶片; 确定在所述多个选择点中的每一个处要除去的去除厚度，使得所述去除厚度的去除导致基本上均匀的晶片内半导体层厚度; 基于各个点的去除厚度，以剂量水平和能量水平中的至少一个将多个选择点中的每一个植入种子到晶片; 并抛光半导体层以使半导体层变薄。

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