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1. 发明授权

US07360187B2 Mixed mode verifier 失效
标题翻译：混合模式验证器
公开(公告)号：US07360187B2
公开(公告)日：2008-04-15
申请号：US11242599
申请日：2005-09-30
申请人： Kevin D. Jones , Thomas J. Sheffler , Kathryn M. Mossawir , Qiang Hong , Paul Wong , Jing Jiang
发明人： Kevin D. Jones , Thomas J. Sheffler , Kathryn M. Mossawir , Qiang Hong , Paul Wong , Jing Jiang
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method and system for formally verifying designs having elements from more than a single design domain is described. An example system allows formal verification of a design containing mixed analog and digital subparts. The system may use different proof engines to solve an appropriate sub-partition of the entire design, and may provide a framework for translating between the different domains to create a unified result. For example, a digital proof engine may be used for a digital only subpart, while an analog proof engine may be used for an analog only subpart. The system may use the partitioning results to determine translators between the various domains, and an order in which the proof engines are applied.
摘要翻译：描述了用于正式验证来自多于单个设计域的元件的设计的方法和系统。示例系统允许对包含混合模拟和数字子部件的设计进行形式验证。系统可以使用不同的证明引擎来解决整个设计的适当子分区，并且可以提供用于在不同域之间进行翻译以创建统一结果的框架。例如，数字证明引擎可以用于仅数字的子部件，而模拟证明引擎可以用于仅模拟子部件。系统可以使用分区结果来确定各个域之间的翻译器以及应用证明引擎的顺序。

2. 发明授权

US07039782B2 Memory system with channel multiplexing of multiple memory devices 失效
标题翻译：具有多个存储器件通道复用的存储器系统
公开(公告)号：US07039782B2
公开(公告)日：2006-05-02
申请号：US10690402
申请日：2003-10-20
申请人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Donald C. Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
发明人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Donald C. Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1684 , Y02D10/14
摘要： A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.
摘要翻译：公开了一种高速存储器系统，其中单个命令根据当前的操作模式对单个存储器件或多个存储器件进行控制。这种控制可以影响一个或多个存储器件与存储器控制器之间的数据传输，以及存储器件的操作状态转换或功率模式转换。类似地，相对低带宽的存储器件的各种配置作为有选择地控制的组进行响应以发送或接收高带宽数据。

3. 发明授权

US06839266B1 Memory module with offset data lines and bit line swizzle configuration 失效
标题翻译：具有偏移数据线和位线交错配置的内存模块
公开(公告)号：US06839266B1
公开(公告)日：2005-01-04
申请号：US10101243
申请日：2002-03-20
申请人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Don Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
发明人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Don Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
IPC分类号： G06F11/10 , G11C7/10 , G11C29/00 , G06F13/40
CPC分类号： G06F11/1028 , G06F11/1044 , G11C7/1072
摘要： A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.

4. 发明授权

US08473681B2 Atomic-operation coalescing technique in multi-chip systems 有权
标题翻译：原子操作合并技术在多芯片系统中的应用
公开(公告)号：US08473681B2
公开(公告)日：2013-06-25
申请号：US13143993
申请日：2010-02-02
申请人： Qi Lin , Liang Peng , Craig E. Hampel , Thomas J. Sheffler , Steven C. Woo , Bohuslav Rychlik
发明人： Qi Lin , Liang Peng , Craig E. Hampel , Thomas J. Sheffler , Steven C. Woo , Bohuslav Rychlik
IPC分类号： G06F13/00
CPC分类号： G06F12/00 , G06F9/3004 , G06F9/3834 , G06F12/0815
摘要： A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.
摘要翻译：缓存相干协议在共享内存空间的多个处理器（或处理器核心）之间分配原子操作。当包括修改存储在共享存储器空间中的数据的指令的原子操作被引导到不具有与数据相关联的地址的控制的第一处理器时，第一处理器发送包括指令的请求修改数据到第二个处理器。然后，已经具有对地址的控制的第二处理器修改数据。此外，第一处理器可以立即进行另一个指令，而不是等待地址变得可用。

5. 发明申请

US20080263487A1 Multi-Format Consistency Checking Tool 审中-公开
标题翻译：多格式一致性检查工具
公开(公告)号：US20080263487A1
公开(公告)日：2008-10-23
申请号：US12144457
申请日：2008-06-23
申请人： Qiang Hong , JIng Jiang , Kevin D. Jones , Kathryn M. Mossawir , Thomas J. Sheffler , Paul Wong
发明人： Qiang Hong , JIng Jiang , Kevin D. Jones , Kathryn M. Mossawir , Thomas J. Sheffler , Paul Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method and system for performing consistency checking of one or more design representations having different design types. A translator for each design type obtains information from each design needed to evaluate rules that are design type-neutral. The described examples also allow a user to add rules using predefined rule terms. In addition, certain examples allow the user to add terms to the rule set and to make new rules with the added terms. Each new term added to a rule set has a corresponding abstraction function in a translator for each design type. Thus, the abstraction functions are not design type-neutral.
摘要翻译：一种用于对具有不同设计类型的一个或多个设计表示进行一致性检查的方法和系统。每个设计类型的翻译器都可以从设计类型中立的规则中获取每个设计所需的信息。所描述的示例还允许用户使用预定义的规则术语来添加规则。此外，某些示例允许用户向规则集添加条款，并使用添加的条款创建新规则。添加到规则集中的每个新术语在每个设计类型的翻译器中都具有相应的抽象功能。因此，抽象函数不是设计类型中立的。

6. 发明申请

US20170085936A1 Network-Loss Tolerant Mobile Broadcast Systems and Algorithms 审中-公开
公开(公告)号：US20170085936A1
公开(公告)日：2017-03-23
申请号：US15271223
申请日：2016-09-20
申请人： Thomas J. Sheffler
发明人： Thomas J. Sheffler
IPC分类号： H04N21/262 , H04L12/861 , H04N21/414 , H04L29/08
CPC分类号： H04N21/26258 , H04L47/34 , H04L65/00 , H04L65/4076 , H04L65/608 , H04L67/02 , H04L67/2804 , H04N21/23406 , H04N21/41407 , H04N21/4223 , H04N21/64322 , H04N21/8456
摘要： Systems and Algorithms for a network-loss tolerant, mobile broadcasting system that reliably and efficiently address unreliable or untimely transmission of segments. By associating a unique metadata to each segment (an Upload ID), segments are identified by the order in which they were captured at their source. Upload IDs allow for methods to proactively address lost or out-of-order segments without disturbing a broadcast. Late arriving segments are preserved for broadcast in the correct sequence by the invention's novel uses of Upload IDs.

7. 发明授权

US06370668B1 High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes 失效
标题翻译：高速存储器系统能够以非芯片杀死和芯片杀死模式选择性地运行
公开(公告)号：US06370668B1
公开(公告)日：2002-04-09
申请号：US09395160
申请日：1999-09-14
申请人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Don Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
发明人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Don Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
IPC分类号： G11C2900
CPC分类号： G06F11/1028 , G06F11/1044 , G11C7/1072
摘要： The present invention provides a high data bandwidth memory system capable of operating in non-chip-kill and chip-kill modes. In chip-kill mode, cycle multiplexing, bit multiplexing, and time and space multiplexing are used to read/write data and syndrome across a group of memory devices. Current command packet formats are adapted to communicate with the group of memory devices in chip-kill mode.
摘要翻译：本发明提供能够以非芯片杀死和芯片杀死模式操作的高数据带宽存储系统。在芯片杀死模式中，循环复用，位复用和时间和空间复用用于跨一组存储器件读/写数据和校正。当前命令分组格式适于以芯片杀死模式与该组存储器件进行通信。

8. 发明授权

US09813746B2 Network-loss tolerant mobile broadcast systems and algorithms 有权
公开(公告)号：US09813746B2
公开(公告)日：2017-11-07
申请号：US15271223
申请日：2016-09-20
申请人： Thomas J. Sheffler
发明人： Thomas J. Sheffler
IPC分类号： H04N21/262 , H04L29/08 , H04N21/414 , H04N21/234 , H04N21/4223 , H04N21/643 , H04N21/845 , H04L12/801
CPC分类号： H04N21/26258 , H04L47/34 , H04L65/00 , H04L65/4076 , H04L65/608 , H04L67/02 , H04L67/2804 , H04N21/23406 , H04N21/41407 , H04N21/4223 , H04N21/64322 , H04N21/8456
摘要： Systems and Algorithms for a network-loss tolerant, mobile broadcasting system that reliably and efficiently address unreliable or untimely transmission of segments. By associating a unique metadata to each segment (an Upload ID), segments are identified by the order in which they were captured at their source. Upload IDs allow for methods to proactively address lost or out-of-order segments without disturbing a broadcast. Late arriving segments are preserved for broadcast in the correct sequence by the invention's novel uses of Upload IDs.

9. 发明申请

US20110289510A1 ATOMIC-OPERATION COALESCING TECHNIQUE IN MULTI-CHIP SYSTEMS 有权
标题翻译：多芯片系统中的原理操作技术
公开(公告)号：US20110289510A1
公开(公告)日：2011-11-24
申请号：US13143993
申请日：2010-02-02
申请人： Qi Lin , Liang Peng , Craig E. Hampel , Thomas J. Sheffler , Steven C. Woo , Bohuslav Rychlik
发明人： Qi Lin , Liang Peng , Craig E. Hampel , Thomas J. Sheffler , Steven C. Woo , Bohuslav Rychlik
IPC分类号： G06F9/46
CPC分类号： G06F12/00 , G06F9/3004 , G06F9/3834 , G06F12/0815
摘要： A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.
摘要翻译：缓存相干协议在共享内存空间的多个处理器（或处理器核心）之间分配原子操作。当包括修改存储在共享存储器空间中的数据的指令的原子操作被引导到不具有与数据相关联的地址的控制的第一处理器时，第一处理器发送包括指令的请求修改数据到第二个处理器。然后，已经具有对地址的控制的第二处理器修改数据。此外，第一处理器可以立即进行另一个指令，而不是等待地址变得可用。

10. 发明授权

US07392492B2 Multi-format consistency checking tool 失效
标题翻译：多格式一致性检查工具
公开(公告)号：US07392492B2
公开(公告)日：2008-06-24
申请号：US11242598
申请日：2005-09-30
申请人： Qiang Hong , Jing Jiang , Kevin D. Jones , Kathryn M. Mossawir , Thomas J. Sheffler , Paul Wong
发明人： Qiang Hong , Jing Jiang , Kevin D. Jones , Kathryn M. Mossawir , Thomas J. Sheffler , Paul Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method and system for performing consistency checking of one or more design representations having different design types. A translator for each design type obtains information from each design needed to evaluate rules that are design type-neutral. The described examples also allow a user to add rules using predefined rule terms. In addition, certain examples allow the user to add terms to the rule set and to make new rules with the added terms. Each new term added to a rule set has a corresponding abstraction function in a translator for each design type. Thus, the abstraction functions are not design type-neutral.
摘要翻译：一种用于对具有不同设计类型的一个或多个设计表示进行一致性检查的方法和系统。每个设计类型的翻译器都可以从设计类型中立的规则中获取每个设计所需的信息。所描述的示例还允许用户使用预定义的规则术语来添加规则。此外，某些示例允许用户向规则集添加条款，并使用添加的条款创建新规则。添加到规则集中的每个新术语在每个设计类型的翻译器中都具有相应的抽象功能。因此，抽象函数不是设计类型中立的。

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