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1. 发明授权

US06708248B1 Memory system with channel multiplexing of multiple memory devices 失效
公开(公告)号：US06708248B1
公开(公告)日：2004-03-16
申请号：US09457155
申请日：1999-12-08
申请人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Donald C. Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
发明人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Donald C. Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
IPC分类号： G06F1200
CPC分类号： G06F13/1657 , G06F13/1684 , Y02D10/14
摘要： A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.

2. 发明授权

US07039782B2 Memory system with channel multiplexing of multiple memory devices 失效
标题翻译：具有多个存储器件通道复用的存储器系统
公开(公告)号：US07039782B2
公开(公告)日：2006-05-02
申请号：US10690402
申请日：2003-10-20
申请人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Donald C. Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
发明人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Donald C. Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1684 , Y02D10/14
摘要： A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.
摘要翻译：公开了一种高速存储器系统，其中单个命令根据当前的操作模式对单个存储器件或多个存储器件进行控制。这种控制可以影响一个或多个存储器件与存储器控制器之间的数据传输，以及存储器件的操作状态转换或功率模式转换。类似地，相对低带宽的存储器件的各种配置作为有选择地控制的组进行响应以发送或接收高带宽数据。

3. 发明授权

US06370668B1 High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes 失效
标题翻译：高速存储器系统能够以非芯片杀死和芯片杀死模式选择性地运行
公开(公告)号：US06370668B1
公开(公告)日：2002-04-09
申请号：US09395160
申请日：1999-09-14
申请人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Don Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
发明人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Don Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
IPC分类号： G11C2900
CPC分类号： G06F11/1028 , G06F11/1044 , G11C7/1072
摘要： The present invention provides a high data bandwidth memory system capable of operating in non-chip-kill and chip-kill modes. In chip-kill mode, cycle multiplexing, bit multiplexing, and time and space multiplexing are used to read/write data and syndrome across a group of memory devices. Current command packet formats are adapted to communicate with the group of memory devices in chip-kill mode.
摘要翻译：本发明提供能够以非芯片杀死和芯片杀死模式操作的高数据带宽存储系统。在芯片杀死模式中，循环复用，位复用和时间和空间复用用于跨一组存储器件读/写数据和校正。当前命令分组格式适于以芯片杀死模式与该组存储器件进行通信。

4. 发明授权

US06839266B1 Memory module with offset data lines and bit line swizzle configuration 失效
标题翻译：具有偏移数据线和位线交错配置的内存模块
公开(公告)号：US06839266B1
公开(公告)日：2005-01-04
申请号：US10101243
申请日：2002-03-20
申请人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Don Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
发明人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Don Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
IPC分类号： G06F11/10 , G11C7/10 , G11C29/00 , G06F13/40
CPC分类号： G06F11/1028 , G06F11/1044 , G11C7/1072
摘要： A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.

5. 发明授权

US06263448B1 Power control system for synchronous memory device 有权
公开(公告)号：US06263448B1
公开(公告)日：2001-07-17
申请号：US09169378
申请日：1998-10-09
申请人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
发明人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
IPC分类号： G06F104
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases.

6. 发明授权

US06226754B1 Apparatus and method for device timing compensation 有权
标题翻译：器件定时补偿的装置和方法
公开(公告)号：US06226754B1
公开(公告)日：2001-05-01
申请号：US09169687
申请日：1998-10-09
申请人： Frederick A. Ware , Richard M. Barth , Donald C. Stark , Craig E. Hampel , Ely K. Tsern , Abhijit M. Abhyankar
发明人： Frederick A. Ware , Richard M. Barth , Donald C. Stark , Craig E. Hampel , Ely K. Tsern , Abhijit M. Abhyankar
IPC分类号： G06F104
CPC分类号： G11C7/1072 , G11C7/22
摘要： An electronic device with device timing constraints includes a set of connections coupled to an interconnect structure that carries row and column commands. A memory core stores data. A memory interface is connect to the set of connections and the memory core. The memory interface includes circuitry for generating memory core timing signals in accordance with the row commands and the column commands. The memory core timing signals have timing constraints to insure correct memory core operation. The memory interface circuitry includes individual delay components for adjusting the timing of selected timing signals of the memory core timing signals.
摘要翻译：具有设备定时约束的电子设备包括耦合到承载行和列命令的互连结构的一组连接。内存核心存储数据。存储器接口连接到一组连接和存储器核心。存储器接口包括用于根据行命令和列命令产生存储器核心定时信号的电路。存储器核心定时信号具有时序约束，以确保正确的存储器核心操作。存储器接口电路包括用于调整存储器核心定时信号的选定定时信号的定时的各个延迟部件。

7. 发明授权

US08305839B2 Memory device having multiple power modes 有权
标题翻译：具有多种功率模式的存储器件
公开(公告)号：US08305839B2
公开(公告)日：2012-11-06
申请号：US13352177
申请日：2012-01-17
申请人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
发明人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.
摘要翻译：描述了具有存储器核心的存储器件。存储器件包括时钟接收器电路，用于接收读取命令的第一接口，数据接口和用于接收功率模式信息的第二接口。数据接口与第一个接口分开。第二个接口与第一个接口和数据接口分开。存储器件具有多个功率模式，包括时钟接收器电路，第一接口和数据接口关闭的第一模式; 时钟接收器被接通并且第一接口和数据接口被关闭的第二模式; 以及其中时钟接收器和第一接口被接通的第三模式。在第三种模式下，当第一个接口接收到命令时，数据接口被打开，以响应命令输出数据。

8. 发明申请

US20110090755A1 Memory Device Having Multiple Power Modes 有权
标题翻译：具有多种功率模式的存储器件
公开(公告)号：US20110090755A1
公开(公告)日：2011-04-21
申请号：US12975322
申请日：2010-12-21
申请人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
发明人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.
摘要翻译：描述了具有存储器核心的存储器件。存储器件包括时钟接收器电路，用于接收读取命令的第一接口，数据接口和用于接收功率模式信息的第二接口。数据接口与第一个接口分开。第二个接口与第一个接口和数据接口分开。存储器件具有多个功率模式，包括时钟接收器电路，第一接口和数据接口关闭的第一模式; 时钟接收器被接通并且第一接口和数据接口被关闭的第二模式; 以及其中时钟接收器和第一接口被接通的第三模式。在第三种模式下，当第一个接口接收到命令时，数据接口被打开，以响应命令输出数据。

9. 发明申请

US20100046314A1 Memory Device Having a Read Pipeline and a Delay Locked Loop 有权
标题翻译：具有读取流水线和延迟锁定环路的存储器件
公开(公告)号：US20100046314A1
公开(公告)日：2010-02-25
申请号：US12608209
申请日：2009-10-29
申请人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
发明人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an external clock signal. The control interface receives a command that specifies a read operation to the memory device. The data interface transfers data between the memory device and an external set of signal lines. The delay locked loop circuit, coupled to the clock receiver circuit, to generate the internal clock signal using the external clock signal. The read pipeline circuit provides read data accessed from the memory core to the data interface. The circuit provides the internal clock signal to the read pipeline circuit in response to receipt of the command that specifies the read operation.
摘要翻译：描述了具有存储器核心的存储器件。存储器件包括时钟接收器电路，控制接口，数据接口，延迟锁定环电路，读取流水线电路和用于提供内部时钟信号的电路。时钟接收器电路接收外部时钟信号。控制接口接收指定对存储器件的读取操作的命令。数据接口在存储器件和外部信号线组之间传送数据。延迟锁定环路电路，耦合到时钟接收器电路，以使用外部时钟信号产生内部时钟信号。读取管线电路将从存储器核心访问的读取数据提供给数据接口。响应于接收到指定读取操作的命令，该电路将内部时钟信号提供给读取管线电路。

10. 发明授权

US06378018B1 Memory device and system including a low power interface 有权
标题翻译：存储器件和系统包括低功率接口
公开(公告)号：US06378018B1
公开(公告)日：2002-04-23
申请号：US09169506
申请日：1998-10-09
申请人： Ely K. Tsern , Thomas J. Holman , Richard M. Barth , Andrew V. Anderson , Paul G. Davis , Craig E. Hampel , Donald C. Stark , Abhijit M. Abhyankar
发明人： Ely K. Tsern , Thomas J. Holman , Richard M. Barth , Andrew V. Anderson , Paul G. Davis , Craig E. Hampel , Donald C. Stark , Abhijit M. Abhyankar
IPC分类号： G06F1300
CPC分类号： G06F13/4243 , G06F13/1694 , Y02D10/14 , Y02D10/151
摘要： A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power interface for coupling to the low speed channel. The memory device is operative in a low power mode and a high power mode. A memory controller is coupled to the high speed channel and the low speed channel of the interconnect structure. The memory controller is configured to transmit control information over the low speed channel to set the power mode of the memory device. The memory device is operative in a low power mode during which high power receiver circuits are turned off. The memory device is also operative in a nap mode during which an internal clock compensation circuit is left on to preserve phase information. The memory system may include multiple memory devices coupled to a daisy chained lead of the interconnect structure. The memory controller may be configured to apply control information to the interconnect structure as an encoded device identification word. The memory devices may each include a decoder for interpreting the encoded device identification word. The memory controller may be configured to apply a memory device selection signal to the interconnect structure to selectively enable the memory devices.
摘要翻译：存储器系统包括具有高速通道和低速通道的互连结构。具有接口电路的存储器件耦合到互连结构。接口电路包括用于耦合到高速通道的高功率接口和用于耦合到低速通道的低功率接口。存储器件在低功率模式和高功率模式下工作。存储器控制器耦合到互连结构的高速通道和低速通道。存储器控制器被配置为通过低速信道发送控制信息以设置存储器件的功率模式。存储器件在低功率模式下工作，在此期间高功率接收器电路被关闭。存储器装置还可以在休眠模式下工作，在此模式期间内部时钟补偿电路被保留以保持相位信息。存储器系统可以包括耦合到互连结构的菊花链引导件的多个存储器件。存储器控制器可以被配置为将控制信息作为编码设备标识字应用于互连结构。存储器件可以各自包括用于解释编码器件识别字的解码器。存储器控制器可以被配置为将存储器件选择信号施加到互连结构以选择性地启用存储器件。

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