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1. 发明申请

WO2006008689A1 BIPOLAR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：双极晶体管及其制造方法
公开(公告)号：WO2006008689A1
公开(公告)日：2006-01-26
申请号：PCT/IB2005/052260
申请日：2005-07-07
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MONTREE, Andreas, H. , SLOTBOOM, Jan, W. , AGARWAL, Prabhat , MEUNIER-BEILLARD, Philippe
发明人： MONTREE, Andreas, H. , SLOTBOOM, Jan, W. , AGARWAL, Prabhat , MEUNIER-BEILLARD, Philippe
IPC分类号： H01L29/73
CPC分类号： H01L29/7317 , H01L29/1004 , H01L29/365 , H01L29/66265 , H01L29/735 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications. The doping concentration lies preferably between about 10 19 and about 10 20 at/cm 3 , and the thickness of the sub-region (2A) lies between 1 and 15 nm and preferably between 1 and 10 nm. The invention also comprises a method of manufacturing such a device (10).
摘要翻译：本发明涉及具有半导体本体（12）的半导体器件（10），该半导体器件（12）包括分别具有第一导电类型的发射极区域（1），基极区域（2）和集电极区域（3），与第一导电类型相反的第二导电类型和第一导电类型，其中从投影中看，发射极区域（1）位于基极区域（2）的上方或下方，并且集电极区域（3）横向地邻接基部区域（2）。根据本发明，基极区域（2）包括其掺杂浓度在厚度方向上具有δ形轮廓的高掺杂子区域（2A），并且所述高度掺杂子区域（2A）横向延伸至收集器区域（3）。这种横向双极晶体管在基极和集电极区域（2,3）之间具有优异的高频特性和较高的击穿电压，这意味着该器件适用于高功率应用。掺杂浓度优选在约10

2. 发明申请

WO2010089675A1 IC AND IC MANUFACTURING METHOD 审中-公开
标题翻译： IC和IC制造方法
公开(公告)号：WO2010089675A1
公开(公告)日：2010-08-12
申请号：PCT/IB2010/050187
申请日：2010-01-15
申请人： NXP B.V. , VANHOUCKE, Tony , HERINGA, Anco , DONKERS, Johan , SLOTBOOM, Jan
发明人： VANHOUCKE, Tony , HERINGA, Anco , DONKERS, Johan , SLOTBOOM, Jan
IPC分类号： H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/732
CPC分类号： H01L21/8249 , H01L27/0623 , H01L29/0821 , H01L29/7322
摘要： Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate (100) to form a buried region (150, 260) therein; forming a halo implant (134) using an impurity of a second type and a shallow implant (132) using an impurity of the first type, said halo implant enveloping the shallow implant in the substrate and being located over said buried region (150, 250); forming, adjacent to the halo implant (134), a further implant (136) using an impurity of the second type for providing a conductive connection to the halo implant; and providing respective connections (170, 160, 270) to the further implant (136), the shallow implant (132) and the buried region (150, 260) allowing the shallow implant, halo implant and buried region to be respectively operable as emitter, base and collector of the vertical bipolar transistor. Hence, an IC may be provided that comprises vertical bipolar transistors manufactured using CMOS processing steps only.
摘要翻译：公开了一种在CMOS工艺中制造垂直双极晶体管的方法，包括将第一类型的杂质注入到衬底（100）中以在其中形成掩埋区域（150,260）; 使用第二类型的杂质和使用第一类型的杂质的浅植入物（132）形成晕轮植入物（134），所述晕轮植入物将衬底中的浅植入物包围并位于所述掩埋区域（150,250））; 与所述晕轮植入物（134）相邻地形成使用所述第二类型的杂质的另外的植入物（136），用于提供与所述晕轮植入物的导电连接; 以及向所述另外的植入物（136）提供相应的连接（170,160,270），所述浅植入物（132）和所述掩埋区域（150,260）允许所述浅植入物，晕圈植入物和掩埋区域分别可作为发射体，垂直双极晶体管的基极和集电极。因此，可以提供包括仅使用CMOS处理步骤制造的垂直双极晶体管的IC。

3. 发明申请

WO2006040720A3 CONTROLLING PARASITIC BIPOLAR GAIN IN A CMOS DEVICE 审中-公开
标题翻译：在CMOS器件中控制PARASITIC BIPOLAR GAIN
公开(公告)号：WO2006040720A3
公开(公告)日：2006-07-06
申请号：PCT/IB2005053308
申请日：2005-10-10
申请人： KONINKL PHILIPS ELECTRONICS NV , AGARWAL PRABHAT , SLOTBOOM JAN W
发明人： AGARWAL PRABHAT , SLOTBOOM JAN W
IPC分类号： H01L27/092 , H01L29/08
CPC分类号： H01L27/0921
摘要： A CMOS device comprising an n-channel MOS transistor (102) and a pchannel MOS transistor (100), defining a pair of parasitic bipolar transitors (110a, 110b) therebetween, wherein a layer (120) of doped SiGe is provided over the source region (106a) of at least one of the MOS transistors (100, 102), between the source region (106a) and the source contact (122). The layer (120) of material acts as a sink for minority carriers (holes in an N-type device) at the source, which has the effect of increasing surface recombination velocity (because the landgap of SiGe is lower than that of the Si substrate (104)), which, in turn, lowers the current gain of the respective parasitic bipolar device. As a result, the effects and/or occurrence of latch-up, and other breakdown instabilities associated with parasitic bipolar devices, can be limited.
摘要翻译：一种CMOS器件，包括n沟道MOS晶体管（102）和沟道MOS晶体管（100），其间限定了一对寄生双极性交变器（110a，110b），其中掺杂的SiGe层（120）设置在源极在所述源极区域（106a）和所述源极触点（122）之间的至少一个所述MOS晶体管（100,102）的区域（106a）。材料层（120）作为源极上的少数载流子（N型器件中的空穴）的吸收器，具有增加表面复合速度的作用（因为SiGe的边界低于Si衬底的边界（104）），这又降低了相应寄生双极器件的电流增益。结果，可以限制与寄生双极器件相关联的闩锁和其他击穿不稳定性的效果和/或发生。

4. 发明申请

WO2005117104A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2005117104A1
公开(公告)日：2005-12-08
申请号：PCT/IB2005/051636
申请日：2005-05-19
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , AGARWAL, Prabhat , SLOTBOOM, Jan, W. , DOORNBOS, Gerben
发明人： AGARWAL, Prabhat , SLOTBOOM, Jan, W. , DOORNBOS, Gerben
IPC分类号： H01L21/8249
CPC分类号： H01L21/8249
摘要： The invention relates to a semiconductor device (10) comprising a substrate (11) and a semiconductor body (1) of silicon having a semiconductor layer structure comprising, in succession, a first and a second semiconductor layer (2, 3), and having a surface region of a first conductivity type which is provided with a field effect transistor (M) with a channel of a second conductivity type, opposite to the first conductivity type, wherein the surface region is provided with source and drain regions (4A, 4B) of the second conductivity type for the field effect transistor (M) and with - interposed between said source and drain regions- a channel region (3A) with a lower doping concentration which forms part of the second semiconductor layer (3) and with a buried first-conductivity-type semiconductor region (2A), buried below the channel region (3A), with a doping concentration that is much higher than that of the channel region (3A) and which forms part of the first semiconductor layer (2). According to the invention, the semiconductor body (1) is provided not only with the field effect transistor (M) but also with a bipolar transistor (B) with emitter, base and collector regions (5A, 5B, 5C) of respectively the second, the first and the second conductivity type, and the emitter region (5A) is formed in the second semiconductor layer (3) and the base region (5B) is formed in the first semiconductor layer (2). In this way a Bi(C)MOS IC (10) is obtained which is very suitable for high-frequency applications and which is easy to manufacture using a method according to the invention. Preferably the first semiconductor layer (2) comprises Si-Ge and is delta-doped, whereas the second semiconductor layer (3) comprises strained Si.
摘要翻译：本发明涉及一种半导体器件（10），它包括具有半导体层结构的硅衬底（12）和半导体本体（1），半导体层结构依次包括第一和第二半导体层（2,3），并且具有具有与第一导电类型相反的具有第二导电类型的沟道的场效应晶体管（M）的第一导电类型的表面区域，其中所述表面区域设置有源极和漏极区域（4A，4B））和用于场效应晶体管（M）的第二导电类型，并且插入在所述源极和漏极区之间 - 具有较低掺杂浓度的沟道区（3A），其形成第二半导体层（3）的一部分，并且具有埋入第一导电型半导体区域（2A），其掺杂在沟道区域（3A）的下方，掺杂浓度比沟道区域（3A）的掺杂浓度高得多，并且形成第一半导体层（2）的一部分，。根据本发明，半导体本体（1）不仅具有场效应晶体管（M），而且还具有双极晶体管（B），发射极，基极和集电极区域（5A，5B，5C）分别为第二第一和第二导电类型和发射极区域（5A）形成在第二半导体层（3）中，并且基极区域（5B）形成在第一半导体层（2）中。以这种方式获得了非常适合于高频应用并且易于使用根据本发明的方法制造的Bi（C）MOS IC（10）。优选地，第一半导体层（2）包括Si-Ge并且是δ掺杂的，而第二半导体层（3）包括应变Si。

5. 发明申请

WO2004047181A1 RADIATION-EMITTING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：辐射发射半导体器件及其制造方法
公开(公告)号：WO2004047181A1
公开(公告)日：2004-06-03
申请号：PCT/IB2003/004810
申请日：2003-10-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , KLOOTWIJK, Johan, H. , SLOTBOOM, Jan, W.
发明人： KLOOTWIJK, Johan, H. , SLOTBOOM, Jan, W.
IPC分类号： H01L29/73
CPC分类号： H01L29/7313 , H01L33/0004
摘要： The invention relates to a radiation-emitting semiconductor device (10) with a semiconductor body (1) and a substrate (2), wherein the semiconductor body (1) comprises a vertical bipolar transistor with an emitter region (3), a base region (4) and a collector region (5), which regions are each provided with a connection region (6, 7, 8), and the border between the base region (4) and the collector region (5) forms a pn-junction and, in operation, at a reverse bias of the pn-junction or at a sufficiently large collector current, avalanche multiplication of charge carriers occurs whereby radiation is generated in the collector region (5). According to the invention, the collector region (5) has a thickness through which transmission of the generated radiation occurs, and the collector region (5) borders on a free surface of the semiconductor body (1). In this way, less of the generated radiation is lost by absorption and the radiation generated is more readily available to serve as an optical signal for, for example, another part of the device (10) or for another device (10). A second sub-region (5B) in the collector region (5) may be made for example with the aid of a gate electrode (11) with which a conducting channel can be induced in the semiconductor body (1). Preferably, a radiation conductor (14) is present on the surface of the latter. The invention further comprises a method of manufacturing a device (10) according to the invention.
摘要翻译：本发明涉及具有半导体本体（1）和衬底（2）的辐射发射半导体器件（10），其中半导体本体（1）包括具有发射极区（3）的垂直双极晶体管，基极区（4）和集电极区域（5），这些区域各自设置有连接区域（6,7,8），并且基极区域（4）和集电极区域（5）之间的边界形成pn结并且在操作中，在pn结的反向偏压或集电极电流充足的情况下，发生电荷载流子的雪崩倍增，从而在集电极区域（5）中产生辐射。根据本发明，集电区（5）具有产生辐射的透射的厚度，并且集电区（5）与半导体本体（1）的自由表面接合。以这种方式，所产生的辐射的少量通过吸收而损失，并且所产生的辐射更容易用作用作例如装置（10）的另一部分或另一装置（10）的光信号。集电极区域（5）中的第二子区域（5B）可以例如借助于在半导体本体（1）中可以被引导导电沟道的栅电极（11）制成。优选地，辐射导体（14）存在于其上的辐射导体（14）的表面上。本发明还包括一种制造根据本发明的装置（10）的方法。

6. 发明申请

WO2003044861A1 HETEROJUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH DEVICE 审中-公开
标题翻译：异质半导体器件及其制造方法
公开(公告)号：WO2003044861A1
公开(公告)日：2003-05-30
申请号：PCT/IB2002/004852
申请日：2002-11-21
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUETING, Raymond, J., E. , SLOTBOOM, Jan, W. , VAN DEN OEVER, Leon, C., M.
发明人： HUETING, Raymond, J., E. , SLOTBOOM, Jan, W. , VAN DEN OEVER, Leon, C., M.
IPC分类号： H01L27/07
CPC分类号： H01L29/47 , H01L29/41708 , H01L29/42304 , H01L29/7378
摘要： The invention relates to a semiconductor device with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2), and a collector region (3), which are provided with respectively a first, a second, and a third connection conductor (4, 5, 6), while the bandgap of the base region (2) is lower than that of the collector region (3) or of the emitter region (1), for example owing to the use of a silicon-germanium alloy instead of pure silicon. Such a device is very fast, but its transistor shows a relatively low BVceo. In a device according to the invention, the emitter region (1) or the base region (2) comprises a sub-region (1B, 2B) with a reduced doping concentration, which sub-region (1B, 2B) is provided with a further connection conductor (4B, 5B) which forms a Schottky junction with the sub-region (1B, 2B). Such a device results in a transistor with a particularly high cut-off frequency fT but with no or hardly any reduction of the BVceo. In a preferred embodiment, the emitter region (1) and its sub-region (1B), or the base region (2) and its sub-region (2B) both border the surface of the semiconductor body (10) and the further connection conductor (4B, 5B) forms part of the first or the second connection conductor (4, 5), as applicable. The invention also comprises a method of manufacturing a device according to the invention.
摘要翻译：本发明涉及具有异质结双极的半导体器件，特别是具有发射极区域（1），基极区域（2）和集电极区域（3）的npn晶体管，它们分别设置有第一，第二和第三连接导体（4,5,6），而基极区域（2）的带隙比集电极区域（3）或发射极区域（1）的带隙低，例如由于使用的硅 - 锗合金代替纯硅。这样的器件非常快，但其晶体管显示出相对较低的BVceo。在根据本发明的装置中，发射极区域（1）或基极区域（2）包括具有降低的掺杂浓度的子区域（1B，2B），该子区域（1B，2B）设置有与所述子区域（1B，2B）形成肖特基结的另外的连接导体（4B，5B）。这种器件导致具有特别高的截止频率fT的晶体管，但是没有或几乎不减少BVceo。在优选实施例中，发射极区域（1）及其子区域（1B）或基极区域（2）及其子区域（2B）都与半导体本体（10）的表面相接触，并且另外的连接导体（4B，5B）形成第一或第二连接导体（4,5）的一部分。本发明还包括一种制造根据本发明的装置的方法。

7. 发明申请

WO2009066204A1 CHARGE CARRIER STREAM GENERATING ELECTRONIC DEVICE AND METHOD 审中-公开
标题翻译：充电载体流产生电子装置和方法
公开(公告)号：WO2009066204A1
公开(公告)日：2009-05-28
申请号：PCT/IB2008/054737
申请日：2008-11-12
申请人： NXP B.V. , VANHOUCKE, Tony , HURKX, Godefridus, A., M. , SLOTBOOM, Jan, W.
发明人： VANHOUCKE, Tony , HURKX, Godefridus, A., M. , SLOTBOOM, Jan, W.
IPC分类号： G11C16/02
CPC分类号： G11C13/0004
摘要： The present invention discloses an electronic device comprising a generator for generating a stream (125) of charge carriers. The generator comprises a bipolar transistor (100) having an emitter region (120), a collector region (160) and a base region (140) oriented between the emitter region (120) and the collector region (160), and a controller for controlling exposure of the bipolar transistor (100) to a voltage in excess of its open base breakdown voltage (BV CEO ) such that the emitter region (120) generates the stream (125) of charge carriers from a first area being smaller than the emitter region surface area. The electronic device may further comprise a material (410) arranged to receive the stream of charge carriers for triggering a change in a property of said material, the emitter region (120) being arranged between the base region (140) and the material (410). In operation, the bipolar transistor (100) is subjected to a voltage in excess of its open base breakdown voltage (BV CEO ) such that the emitter region (120) generates the electron stream of charge carriers, e.g. electrons, from a first area being smaller than the emitter region surface area. Consequently, an electron stream having sub-lithographic dimensions is utilized without requiring complex lithographic processing steps. The invention is particularly suitable for use in phase-change memories.
摘要翻译：本发明公开了一种电子设备，其包括用于产生电荷载流子流（125）的发生器。发生器包括具有发射极区域（120），定向在发射极区域（120）和收集极区域（160）之间的集电极区域（160）和基极区域（140））的双极晶体管（100），以及控制器将所述双极晶体管（100）的曝光控制为超过其开路基极击穿电压（BVCEO）的电压，使得所述发射极区域（120）从小于所述发射极区域的第一区域产生电荷载流子流（125）表面积。电子设备还可以包括布置成接收用于触发所述材料的性质变化的电荷载流流的材料（410），所述发射极区域（120）布置在基极区域（140）和材料（410）之间）。在操作中，双极晶体管（100）经受超过其开路基极击穿电压（BVCEO）的电压，使得发射极区域（120）产生电荷载流子的电子流，例如，电子从第一区域小于发射极区域表面积。因此，使用具有亚光刻尺寸的电子流，而不需要复杂的光刻处理步骤。本发明特别适用于相变存储器。

8. 发明申请

WO2008041188A1 TUNNEL FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：隧道场效应晶体管
公开(公告)号：WO2008041188A1
公开(公告)日：2008-04-10
申请号：PCT/IB2007/054020
申请日：2007-10-03
申请人： NXP B.V. , CURATOLA, Gilberto , AGARWAL, Prabhat , SLOTBOOM, Jan, W. , HURKX, Godefridus, A., M. , SURDEANU, Radu , DOORNBOS, Gerben
发明人： CURATOLA, Gilberto , AGARWAL, Prabhat , SLOTBOOM, Jan, W. , HURKX, Godefridus, A., M. , SURDEANU, Radu , DOORNBOS, Gerben
IPC分类号： H01L29/739 , H01L29/165 , H01L29/201
CPC分类号： H01L29/161 , H01L29/165 , H01L29/7391
摘要： A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).
摘要翻译：隧道晶体管包括与漏极扩散（6）相反的导电类型的源扩散（4），使得在较低掺杂区域（8）中的源极和漏极扩散之间形成耗尽层。绝缘栅极（16）控制耗尽层的位置和厚度。该装置包括形成在由下层（2）和盖层（22）的不同材料制成的聚集层（20）中的量子阱。

9. 发明申请

WO2006040735A1 BICMOS COMPATIBLE JFET DEVICE AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译： BICMOS兼容JFET器件及其制造方法
公开(公告)号：WO2006040735A1
公开(公告)日：2006-04-20
申请号：PCT/IB2005/053366
申请日：2005-10-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , AGARWAL, Prabhat , SLOTBOOM, Jan, W. , VAN NOORT, Wibo, D.
发明人： AGARWAL, Prabhat , SLOTBOOM, Jan, W. , VAN NOORT, Wibo, D.
IPC分类号： H01L21/8248 , H01L27/098 , H01L27/06
CPC分类号： H01L27/098 , H01L21/8248 , H01L27/0623
摘要： A BiCMOS-compatible JFET device comprising source and drain regions (17, 18) which are formed in the same process as that used to form the emitter out-diffusion or a vertical bipolar device, wherein the semiconductor layer which forms the emitter cap in the bipolar device forms the channel (16) of the JFET device and the layer of material (i.e. the base epi-stack) which forms the intrinsic base region of the bipolar device forms the intrinsic gate region (14) of the JFET device. As a result, the integration of the JFET device into a standard BiCMOS process can be achieved without the need for any additional masking or other processing steps.
摘要翻译：一种BiCMOS兼容的JFET器件，包括以与用于形成发射极外扩散的相同的工艺形成的源极和漏极区域（17,18），或者垂直双极器件，其中形成发光极帽的半导体层双极器件形成JFET器件的沟道（16），并且形成双极器件的本征基极区域的材料层（即，基极外延堆叠）形成JFET器件的本征栅极区域（14）。结果，可以实现JFET器件到标准BiCMOS工艺的集成，而不需要任何额外的掩模或其他处理步骤。

10. 发明申请

WO2004102670A3 SEMICONDUCTOR DEVICE WITH A FIELD SHAPING REGION 审中-公开
标题翻译：具有场形成区域的半导体器件
公开(公告)号：WO2004102670A3
公开(公告)日：2005-01-20
申请号：PCT/IB2004001527
申请日：2004-05-06
申请人： KONINKL PHILIPS ELECTRONICS NV , HERINGA ANCO , HUETING RAYMOND J E , SLOTBOOM JAN W
发明人： HERINGA ANCO , HUETING RAYMOND J E , SLOTBOOM JAN W
IPC分类号： H01L29/06 , H01L29/40 , H01L29/73 , H01L29/732 , H01L29/78 , H01L29/861 , H01L29/41
CPC分类号： H01L29/402 , H01L29/0649 , H01L29/0653 , H01L29/408 , H01L29/73 , H01L29/732 , H01L29/7802 , H01L29/7813 , H01L29/7824 , H01L29/861
摘要： A semiconductor device, for example a diode (200), having a pn junction (101) has an insulating material field shaping region (201) adjacent, and possibly bridging, the pn junction. The field shaping region (201) preferably has a high dielectric constant and is coupled via capacitive voltage coupling regions (204,205) to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction (101) and the device is non-conducting, a capacitive electric field, is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region (201), the electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region (208,209) and an increased reverse breakdown voltage of the device.
摘要翻译：具有pn结（101）的半导体器件（例如二极管（200））具有与pn结相邻且可能桥接的绝缘材料场整形区域（201）。场成形区域（201）优选地具有高介电常数，并且经由电容性电压耦合区域（204,205）耦合到与施加到pn结的基本相同的电压。当在pn结（101）上施加反向电压并且器件不导通时，电容电场存在于场成形区域的一部分中，其延伸超过将存在的pn结耗尽区的极限在不存在场整形区域（201）的情况下，场成形区域中的电场引起限制到相应延伸的pn结耗尽区域（208,209）的拉伸电场和该器件的反向击穿电压的增加。

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