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1. 发明申请

WO2005117104A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2005117104A1
公开(公告)日：2005-12-08
申请号：PCT/IB2005/051636
申请日：2005-05-19
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , AGARWAL, Prabhat , SLOTBOOM, Jan, W. , DOORNBOS, Gerben
发明人： AGARWAL, Prabhat , SLOTBOOM, Jan, W. , DOORNBOS, Gerben
IPC分类号： H01L21/8249
CPC分类号： H01L21/8249
摘要： The invention relates to a semiconductor device (10) comprising a substrate (11) and a semiconductor body (1) of silicon having a semiconductor layer structure comprising, in succession, a first and a second semiconductor layer (2, 3), and having a surface region of a first conductivity type which is provided with a field effect transistor (M) with a channel of a second conductivity type, opposite to the first conductivity type, wherein the surface region is provided with source and drain regions (4A, 4B) of the second conductivity type for the field effect transistor (M) and with - interposed between said source and drain regions- a channel region (3A) with a lower doping concentration which forms part of the second semiconductor layer (3) and with a buried first-conductivity-type semiconductor region (2A), buried below the channel region (3A), with a doping concentration that is much higher than that of the channel region (3A) and which forms part of the first semiconductor layer (2). According to the invention, the semiconductor body (1) is provided not only with the field effect transistor (M) but also with a bipolar transistor (B) with emitter, base and collector regions (5A, 5B, 5C) of respectively the second, the first and the second conductivity type, and the emitter region (5A) is formed in the second semiconductor layer (3) and the base region (5B) is formed in the first semiconductor layer (2). In this way a Bi(C)MOS IC (10) is obtained which is very suitable for high-frequency applications and which is easy to manufacture using a method according to the invention. Preferably the first semiconductor layer (2) comprises Si-Ge and is delta-doped, whereas the second semiconductor layer (3) comprises strained Si.
摘要翻译：本发明涉及一种半导体器件（10），它包括具有半导体层结构的硅衬底（12）和半导体本体（1），半导体层结构依次包括第一和第二半导体层（2,3），并且具有具有与第一导电类型相反的具有第二导电类型的沟道的场效应晶体管（M）的第一导电类型的表面区域，其中所述表面区域设置有源极和漏极区域（4A，4B））和用于场效应晶体管（M）的第二导电类型，并且插入在所述源极和漏极区之间 - 具有较低掺杂浓度的沟道区（3A），其形成第二半导体层（3）的一部分，并且具有埋入第一导电型半导体区域（2A），其掺杂在沟道区域（3A）的下方，掺杂浓度比沟道区域（3A）的掺杂浓度高得多，并且形成第一半导体层（2）的一部分，。根据本发明，半导体本体（1）不仅具有场效应晶体管（M），而且还具有双极晶体管（B），发射极，基极和集电极区域（5A，5B，5C）分别为第二第一和第二导电类型和发射极区域（5A）形成在第二半导体层（3）中，并且基极区域（5B）形成在第一半导体层（2）中。以这种方式获得了非常适合于高频应用并且易于使用根据本发明的方法制造的Bi（C）MOS IC（10）。优选地，第一半导体层（2）包括Si-Ge并且是δ掺杂的，而第二半导体层（3）包括应变Si。

2. 发明申请

WO2008041188A1 TUNNEL FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：隧道场效应晶体管
公开(公告)号：WO2008041188A1
公开(公告)日：2008-04-10
申请号：PCT/IB2007/054020
申请日：2007-10-03
申请人： NXP B.V. , CURATOLA, Gilberto , AGARWAL, Prabhat , SLOTBOOM, Jan, W. , HURKX, Godefridus, A., M. , SURDEANU, Radu , DOORNBOS, Gerben
发明人： CURATOLA, Gilberto , AGARWAL, Prabhat , SLOTBOOM, Jan, W. , HURKX, Godefridus, A., M. , SURDEANU, Radu , DOORNBOS, Gerben
IPC分类号： H01L29/739 , H01L29/165 , H01L29/201
CPC分类号： H01L29/161 , H01L29/165 , H01L29/7391
摘要： A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).
摘要翻译：隧道晶体管包括与漏极扩散（6）相反的导电类型的源扩散（4），使得在较低掺杂区域（8）中的源极和漏极扩散之间形成耗尽层。绝缘栅极（16）控制耗尽层的位置和厚度。该装置包括形成在由下层（2）和盖层（22）的不同材料制成的聚集层（20）中的量子阱。

3. 发明申请

WO2007036876A1 DOUBLE GATE NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING 审中-公开
标题翻译：双门非易失性存储器件及其制造方法
公开(公告)号：WO2007036876A1
公开(公告)日：2007-04-05
申请号：PCT/IB2006/053491
申请日：2006-09-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DOORNBOS, Gerben , GOARIN, Pierre
发明人： DOORNBOS, Gerben , GOARIN, Pierre
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/792 , H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/66825 , H01L29/66833 , H01L29/785
摘要： The present invention relates to a non- volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin- shaped channel; the control gate being in contact with the charge storage stack, wherein - an access gate is provided adjacent to one sidewall portion and separated therefrom by an intermediate gate oxide layer, and - the charge storage stack contacts the fin-shaped channel on the other sidewall portion and is separated from the channel by the intermediate gate oxide layer.
摘要翻译：本发明涉及包括半导体源极和漏极区域的衬底层上的非易失性存储器件，半导体沟道区域，电荷存储堆叠和控制栅极; 所述通道区域是翅片状的，具有两个侧壁部分和顶部部分，并且在所述源极区域和所述漏极区域之间延伸; 所述电荷存储堆置于所述源区和漏区之间并且在所述鳍状沟道上延伸，基本上垂直于所述鳍状通道的长度方向; 所述控制栅极与所述电荷存储堆叠接触，其中，接近栅极邻近一个侧壁部分设置并且由中间栅极氧化物层与其隔开，并且所述电荷存储堆叠接触所述另一个侧壁上的所述鳍状沟道并且通过中间栅极氧化物层与沟道分离。

4. 发明申请

WO2005122275A3 SEMICONDUCTOR ON INSULATOR SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE 审中-公开
公开(公告)号：WO2005122275A3
公开(公告)日：2005-12-22
申请号：PCT/IB2005/051832
申请日：2005-06-06
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SURDEANU, Radu , DOORNBOS, Gerben , PONOMAREV, Youri , LOO, Josine
发明人： SURDEANU, Radu , DOORNBOS, Gerben , PONOMAREV, Youri , LOO, Josine
IPC分类号： H01L29/786
摘要： A semiconductor on insulator semiconductor device has metal or silicide source and drain contact regions (38, 40), activated source and drain regions (30, 32) and a body region (34). The structure may be a double gated SOI structure or a fully depleted (FD) SOI structure. A sharp intergace and low resistance are achieved with a process that uses spacers (28) and which fully replaces the full thickness of a semiconductor layer with the contact regions.

5. 发明申请

WO2007122565A3 STATIC RANDOM ACCESS MEMORY CELL 审中-公开
公开(公告)号：WO2007122565A3
公开(公告)日：2007-11-01
申请号：PCT/IB2007/051415
申请日：2007-04-19
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , NG, Ranick, K., M. , DOORNBOS, Gerben , SURDEANU, Radu
发明人： NG, Ranick, K., M. , DOORNBOS, Gerben , SURDEANU, Radu
IPC分类号： G11C11/412
摘要： A static random access memory means is provided. The SRAM memory means comprises a first pass-gate FET (T6) which is coupled between a first node (A) and a bitline-bar (BLB). A second pass-gate FET (T1) is coupled between a second node (B) and a bitline (BL). The second node (B) is coupled to the first pass-gate FET (T6) and the first pass- gate FET (T6) is switched according to the voltage (V B ) at the second node (B). The first node (A) is coupled to the second pass-gate FET (T1). The second pass-gate FET (T1) is switched according to the voltage (V A ) on the first node (A).

6. 发明申请

WO2005083769A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：WO2005083769A1
公开(公告)日：2005-09-09
申请号：PCT/IB2005/050527
申请日：2005-02-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SURDEANU, Radu, C. , DOORNBOS, Gerben , VAN DAL, Marcus, J., H.
发明人： SURDEANU, Radu, C. , DOORNBOS, Gerben , VAN DAL, Marcus, J., H.
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/7624 , H01L29/458 , H01L29/66507 , H01L29/66598 , H01L29/78621
摘要： This invention relates to a semiconductor device (105) and a method of manufacturing this device. A preferred embodiment of the invention is a semiconductor device (105) comprising a silicon semiconductor substrate (110), an oxide layer (115) and an active layer (120). In the active layer, insulating areas (125) and an active area (127) have been formed. The active area (127) comprises a source (180), a drain (182) and a body (168). The source (180) and drain (182) also comprise source and drain extensions (184, 186). The active layer (120) is provided with a gate (170). On both sides of the gate (170), L-shaped side wall spacers are located. The source (180) and drain (182) also comprise silicide regions (190, 192). A characteristic of these regions is that they have extensions (194, 196) located under the side wall spacers (136, 138). These extensions (194, 196) strongly reduce the series resistance of the source (194) and drain (196), which significantly improves the performance of the semiconductor device (105).
摘要翻译：本发明涉及一种半导体器件（105）及其制造方法。本发明的优选实施例是包括硅半导体衬底（110），氧化物层（115）和有源层（120）的半导体器件（105）。在有源层中，形成了绝缘区域（125）和有源区域（127）。有源区域（127）包括源（180），漏极（182）和主体（168）。源极（180）和漏极（182）还包括源极和漏极延伸部分（184,186）。有源层（120）设有栅极（170）。在门（170）的两侧设有L形侧壁隔片。源极（180）和漏极（182）还包括硅化物区域（190,192）。这些区域的特征是它们具有位于侧壁间隔物（136,138）下方的延伸部（194,196）。这些扩展（194,196）强烈地降低了源极（194）和漏极（196）的串联电阻，这显着地改善了半导体器件（105）的性能。

7. 发明申请

WO2008007331A3 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF 审中-公开
公开(公告)号：WO2008007331A3
公开(公告)日：2008-01-17
申请号：PCT/IB2007/052698
申请日：2007-07-09
申请人： NXP B.V. , SONSKY, Jan , DOORNBOS, Gerben
发明人： SONSKY, Jan , DOORNBOS, Gerben
IPC分类号： H01L21/336 , H01L29/786 , H01L21/84 , H01L27/12
摘要： A FinFET and methods for its manufacture are provided. The method of the invention provides an elegant process for manufacturing FinFETs with separated gates. It is compatible with a wide range of dielectric materials and gate electrode materials, providing that the gate electrode material(s) can be deposited conformally. Provision of at least one upstanding structure (or "dummy fin") (40) on each side of the fin (4) serves to locally increase the thickness of the gate electrode material layer (70). In particular, as the shortest distance between each upstanding structure (40) and the respective side of the fin (4) is arranged in accordance with the invention to be less than twice the thickness of the conformal layer, the thickness of the gate electrode material layer (70) all the way across this distance between each upstanding structure (40) and the fin (4) is increased relative to that over planar regions of the substrate (2). Thus, following an anisotropic etch to remove gate electrode material (70) overlying the fin (4), some material nevertheless remains between the upstanding structures and the fin. Thus, an enlarged area of gate electrode material is formed for use as a gate contact pad.

8. 发明申请

WO2009122353A1 SRAM CELL COMPRISING FINFETS 审中-公开
标题翻译：包含FINFET的SRAM单元
公开(公告)号：WO2009122353A1
公开(公告)日：2009-10-08
申请号：PCT/IB2009/051338
申请日：2009-03-31
申请人： NXP B.V. , DOORNBOS, Gerben
发明人： DOORNBOS, Gerben
IPC分类号： H01L21/8244 , H01L27/02 , H01L27/11
CPC分类号： H01L27/0207 , H01L27/11 , H01L27/1104
摘要： An SRAM finFET cell includes fins (30..40) and respective insulated gates (62..72) forming finFET transistors, together with interconnects (86... 92) connecting the fins and gates. The regions of the fins not covered by the insulated gates are doped. Each of the fins (30.. 40) extends in the same longitudinal direction; and each of the fins (30.. 40) is arranged laterally adjacent to another fin of the same conductivity type. The cell design reduces the effects of process spread.
摘要翻译： SRAM finFET单元包括形成finFET晶体管的翅片（30..40）和各自的绝缘栅极（62..72），以及连接鳍片和栅极的互连（86 ... 92）。未被绝缘栅极覆盖的鳍片的区域被掺杂。每个翅片（30 ... 40）在相同的纵向方向上延伸; 并且每个翅片（30 ... 40）被布置成与相同导电类型的另一个翅片横向相邻。电池设计减少了工艺扩散的影响。

9. 发明申请

WO2008059440A2 DOUBLE PATTERNING FOR LITHOGRAPHY TO INCREASE FEATURE SPATIAL DENSITY 审中-公开
标题翻译：用于提升特征空间密度的双重图案
公开(公告)号：WO2008059440A2
公开(公告)日：2008-05-22
申请号：PCT/IB2007/054604
申请日：2007-11-13
申请人： NXP B.V. , VANLEENHOVE, Anja Monique , DIRKSEN, Peter , VAN STEENWINCKEL, David , VAN DAL, Mark , DOORNBOS, Gerben , JUFFERMANS, Casper
发明人： VANLEENHOVE, Anja Monique , DIRKSEN, Peter , VAN STEENWINCKEL, David , VAN DAL, Mark , DOORNBOS, Gerben , JUFFERMANS, Casper
IPC分类号： G03F7/00
CPC分类号： G03F7/0035 , G03F7/11 , H01L21/0271 , H01L21/0273 , H01L21/823821 , H01L29/66795 , H01L29/6681 , H01L29/785
摘要： A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and / or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spatial frequency greater than that of the features defined in each of the first and second patterns separately. The process has particular utility in defining source, drain and fin features of finFET devices with a smaller feature size than otherwise achievable with the prevailing lithography tools.
摘要翻译：在衬底中或衬底上的至少一个器件层中形成图案的方法包括：用第一光致抗蚀剂层涂覆器件层; 使用第一掩模曝光第一光致抗蚀剂; 显影第一光致抗蚀剂层以在基底上形成第一图案; 用保护层涂覆基板; 处理保护层以在其中与第一光致抗蚀剂接触的位置引起其变化，使得改变的保护层基本上不受随后的曝光和/或显影步骤的影响; 用第二光致抗蚀剂层涂覆基板; 使用第二掩模曝光所述第二光致抗蚀剂层; 并且显影所述第二光致抗蚀剂层以在所述基板上形成第二图案，而不会显着影响所述第一光致抗蚀剂层中的所述第一图案，其中所述第一和第二图案一起限定散布特征，其空间频率大于第一和第二模式分开。该方法在定义具有较小的特征尺寸的finFET器件的源极，漏极和鳍片特征方面具有特别的用途，而与主要的光刻工具不同。

10. 发明申请

WO2010032174A1 FIN FIELD EFFECT TRANSISTOR (FINFET) 审中-公开
标题翻译： FIN场效应晶体管（FINFET）
公开(公告)号：WO2010032174A1
公开(公告)日：2010-03-25
申请号：PCT/IB2009/053963
申请日：2009-09-10
申请人： NXP B.V. , DOORNBOS, Gerben , LANDER, Robert
发明人： DOORNBOS, Gerben , LANDER, Robert
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7856 , H01L21/76224 , H01L27/10826 , H01L27/10879 , H01L29/0649 , H01L29/105 , H01L29/66795 , H01L29/7851 , H01L29/7853 , H01L29/7854
摘要： A Fin FET whose fin (12) has an upper portion (30) doped with a first conductivity type and a lower portion (32) doped with a second conductivity type, wherein the junction (34) between the upper portion (30) and the lower portion (32) acts as a diode; and the FinFET further comprises: at least one layer (26, 28) of high-k dielectric material (for example Si 3 N 4 ) adjacent at least one side of the fin (12) for redistributing a potential drop more evenly over the diode, compared to if the at least one layer of high-k dielectric material were not present, when the upper portion (30) is connected to a first potential and the lower portion (32) is connected to a second potential thereby providing the potential drop across the junction (34). Examples of the k value for the high-k dielectric material are k ≥ 5, k ≥ 7.5, and k ≥ 20.
摘要翻译：翅片（12）具有掺杂有第一导电类型的上部（30）和掺杂有第二导电类型的下部（32）的翅片（FET），其中，所述上部（30）和下部（32）用作二极管; 并且所述FinFET还包括：与所述鳍片（12）的至少一侧相邻的高k电介质材料（例如Si 3 N 4）的至少一个层（26,28），用于将二极管上的电压降更均匀地重新分配，如果所述至少一层高k电介质材料不存在，则当所述上部（30）连接到第一电位并且所述下部（32）连接到第二电位时，从而提供所述电位降交界处（34）。高k介电材料的k值的例子是k = 5，k = 7.5，k = 20。

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