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1. 发明申请

US20080213496A1 Method of coating semiconductor processing apparatus with protective yttrium-containing coatings 审中-公开
标题翻译：用保护性钇涂层涂覆半导体处理装置的方法
公开(公告)号：US20080213496A1
公开(公告)日：2008-09-04
申请号：US11890221
申请日：2007-08-02
申请人： Jennifer Y. Sun , Shun Jackson Wu , Senh Thach , Ananda Kumar , Robert W. Wu , Hong Wang , Yixing Lin , Clifford C. Stow , Jim Dempster , Li Xu , Kenneth S. Collins , Ren-Guan Duan , Thomas Graves , Xiaoming He , Jie Yuan
发明人： Jennifer Y. Sun , Shun Jackson Wu , Senh Thach , Ananda Kumar , Robert W. Wu , Hong Wang , Yixing Lin , Clifford C. Stow , Jim Dempster , Li Xu , Kenneth S. Collins , Ren-Guan Duan , Thomas Graves , Xiaoming He , Jie Yuan
IPC分类号： C23C4/10 , C23C14/34
CPC分类号： C23C28/042 , C23C4/11 , C23C4/18 , C23C16/4404
摘要： Methods of applying specialty ceramic materials to semiconductor processing apparatus, where the specialty ceramic materials are resistant to halogen-comprising plasmas. The specialty ceramic materials contain at least one yttrium oxide-comprising solid solution. Some embodiments of the specialty ceramic materials have been modified to provide a resistivity which reduces the possibility of arcing within a semiconductor processing chamber.
摘要翻译：将特种陶瓷材料应用于半导体加工设备的方法，其中特种陶瓷材料耐卤素等离子体。特种陶瓷材料含有至少一种含氧化钇的固溶体。已经修改了特种陶瓷材料的一些实施例以提供降低半导体处理室内的电弧的可能性的电阻率。

2. 发明授权

US06513452B2 Adjusting DC bias voltage in plasma chamber 失效
标题翻译：调整等离子体室内的直流偏置电压
公开(公告)号：US06513452B2
公开(公告)日：2003-02-04
申请号：US09841804
申请日：2001-04-24
申请人： Hongching Shan , Evans Y. Lee , Michael D. Welch , Robert W. Wu , Bryan Y. Pu , Paul E. Luscher , James D. Carducci , Richard Blume
发明人： Hongching Shan , Evans Y. Lee , Michael D. Welch , Robert W. Wu , Bryan Y. Pu , Paul E. Luscher , James D. Carducci , Richard Blume
IPC分类号： C23C1600
CPC分类号： H01J37/32834 , H01J37/32477 , H01J37/32623 , H01J37/32706
摘要： A method of adjusting the cathode DC bias in a plasma chamber for fabricating semiconductor devices. A dielectric shield is positioned between the plasma and a selected portion of the electrically grounded components of the chamber, such as the electrically grounded chamber wall. The cathode DC bias is adjusted by controlling one or more of the following parameters: (1) the surface area of the chamber wall or other grounded components which is blocked by the dielectric shield; (2) the thickness of the dielectric; (3) the gap between the shield and the chamber wall; and (4) the dielectric constant of the dielectric material. In an apparatus aspect, the invention is a plasma chamber for fabricating semiconductor devices having an exhaust baffle with a number of sinuous passages. Each passage is sufficiently long and sinuous that no portion of the plasma within the chamber can extend beyond the outlet of the passage. By blocking the plasma from reaching the exhaust pump, the exhaust baffle reduces the deposition of unwanted particles on exhaust pump components. The exhaust baffle also reduces the cathode DC bias by reducing the effective surface area of the electrically grounded chamber wall which couples RF power to the plasma.
摘要翻译：一种调整用于制造半导体器件的等离子体室中的阴极直流偏压的方法。电介质屏蔽件位于等离子体和室的电接地部件的选定部分之间，例如电接地室壁。通过控制一个或多个以下参数来调节阴极直流偏压：（1）腔室壁的表面积或由介电屏蔽件阻挡的其它接地部件; （2）电介质的厚度; （3）屏蔽和室壁之间的间隙; 和（4）介电材料的介电常数。在装置方面，本发明是用于制造半导体器件的等离子体室，其具有带有多个弯曲通道的排气挡板。每个通道足够长和弯曲，使得室内的等离子体的任何部分不能延伸超过通道的出口。通过阻止等离子体到达排气泵，排气挡板减少排气泵部件上不想要的颗粒的沉积。排气挡板还通过减少将RF功率耦合到等离子体的电接地室壁的有效表面积来减小阴极DC偏压。

3. 发明授权

US06432318B1 Dielectric etch process reducing striations and maintaining critical dimensions 失效
标题翻译：电介质蚀刻工艺减少条纹并维持临界尺寸
公开(公告)号：US06432318B1
公开(公告)日：2002-08-13
申请号：US09506112
申请日：2000-02-17
申请人： Ji Ding , Hidehiro Kojiri , Yoshio Ishikawa , Keiji Horioka , Ruiping Wang , Robert W. Wu , Hoiman Hung
发明人： Ji Ding , Hidehiro Kojiri , Yoshio Ishikawa , Keiji Horioka , Ruiping Wang , Robert W. Wu , Hoiman Hung
IPC分类号： H01L213065
CPC分类号： H01L21/31116
摘要： An oxide etching recipe including a heavy hydrogen-free fluorocarbon having F/C ratios less than 2 such as C4F6 or C5F8, an oxygen-containing gas such as O2, CO or CO2, a lighter fluorocarbon or hydrofluorocarbon, and a noble diluent gas such as Ar or Xe. The amounts of the first three gases are chosen such that the ratio (F—H)/(C—O) is at least 1.5 and no more than 2. Alternatively, the gas mixture may include the heavy fluorocarbon, carbon tetrafluoride, and the diluent with the ratio of the first two chosen such the ratio F/C is between 1.5 and 2.
摘要翻译：氧化物蚀刻配方包括F / C比小于2的重氢无碳氟化合物，例如C 4 F 6或C 5 F 8，含氧气体如O 2，CO或CO 2，较轻碳氟化合物或氢氟烃，以及稀有稀释气体作为Ar或Xe。选择前三种气体的量，使得比值（FH）/（CO）至少为1.5且不大于2.或者，气体混合物可以包括重碳氟化合物，四氟化碳和稀释剂，其比例的前两个被选择的比例F / C在1.5和2之间。

4. 发明授权

US5986875A Puncture resistant electrostatic chuck 失效
标题翻译：耐刺穿静电卡盘
公开(公告)号：US5986875A
公开(公告)日：1999-11-16
申请号：US015802
申请日：1998-01-29
申请人： Arik Donde , Hyman J. Levinstein , Robert W. Wu , Andreas Hegedus , Edwin C. Weldon , Shamouil Shamouilian , Jon T. Clinton , Surinder S. Bedi
发明人： Arik Donde , Hyman J. Levinstein , Robert W. Wu , Andreas Hegedus , Edwin C. Weldon , Shamouil Shamouilian , Jon T. Clinton , Surinder S. Bedi
IPC分类号： B23Q3/15 , H01L21/683 , H02N13/00
CPC分类号： H01L21/6831 , H01L21/6833 , H02N13/00 , Y10T279/23
摘要： A puncture resistant electrostatic chuck (20) is described. The chuck (20) comprises at least one electrode (25); and a composite insulator (30) covering the electrode. The composite insulator comprises a matrix material having a conformal holding surface (50) capable of conforming to the substrate (35) under application of an electrostatic force generated by the electrode to reduce leakage of heat transfer fluid held between the substrate and the holding surface. A hard puncture resistant layer, such a layer of fibers or an aromatic polyamide layer, is positioned below the holding surface (50) and is sufficiently hard to increase the puncture resistance of the composite insulator.
摘要翻译：描述了一种抗穿刺静电卡盘（20）。卡盘（20）包括至少一个电极（25）; 和覆盖电极的复合绝缘体（30）。复合绝缘体包括具有能够在施加电极产生的静电力的同时保持基板（35）的共形保持表面（50）的基体材料，以减少保持在基板和保持表面之间的传热流体的泄漏。这种纤维层或芳香族聚酰胺层的耐穿刺层位于保持面（50）的下方，并且足够难以提高复合绝缘子的抗穿刺性。

5. 发明授权

US5729423A Puncture resistant electrostatic chuck 失效
公开(公告)号：US5729423A
公开(公告)日：1998-03-17
申请号：US755716
申请日：1996-11-25
申请人： Arik Donde , Hyman J. Levinstein , Robert W. Wu , Andreas Hegedus , Edwin C. Weldon , Shamouil Shamouilian , Jon T. Clinton , Surinder S. Bedi
发明人： Arik Donde , Hyman J. Levinstein , Robert W. Wu , Andreas Hegedus , Edwin C. Weldon , Shamouil Shamouilian , Jon T. Clinton , Surinder S. Bedi
IPC分类号： B23Q3/15 , H01L21/683 , H02N13/00
CPC分类号： H01L21/6831 , H01L21/6833 , H02N13/00 , Y10T279/23
摘要： A puncture resistant electrostatic chuck (20) is described. The chuck (20) comprises at least one electrode (25); and a composite insulator (30) covering the electrode. The composite insulator comprises a matrix material having a conformal holding surface (50) capable of conforming to the substrate (35) under application of an electrostatic force generated by the electrode to reduce leakage of heat transfer fluid held between the substrate and the holding surface. A hard puncture resistant layer, such a layer of fibers or an aromatic polyamide layer, is positioned below the holding surface (50) and is sufficiently hard to increase the puncture resistance of the composite insulator.

6. 发明授权

US5110712A Incorporation of dielectric layers in a semiconductor 失效
标题翻译：在半导体中引入电介质层
公开(公告)号：US5110712A
公开(公告)日：1992-05-05
申请号：US547093
申请日：1990-04-25
申请人： Daniel D. Kessler , Robert W. Wu , Christopher C. Beatty , Mark D. Crook
发明人： Daniel D. Kessler , Robert W. Wu , Christopher C. Beatty , Mark D. Crook
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/31138
摘要： A system for integrating a composite dielectric layer in an integrated circuit to facilitate fabrication of a high density multi-level interconnect with external contacts. The composite dielectric layer comprises of a polymer layer which normally comprises a polyimide that is deposited using conventional spin-deposit techniques to form a planarized surface for deposition of an inorganic layer typically comprising silicon dioxide or silicon nitride. The inorganic layer is etched using standard photoresist techniques to form an inorganic mask for etching the polymer layer. A previously deposited inorganic layer functions as an etch stop to allow long over etches to achieve full external contacts which, in turn, allows high density interconnect systems on multiple levels.
摘要翻译：一种用于将集成电路中的复合介电层集成以便于制造具有外部触点的高密度多级互连的系统。复合介电层包括聚合物层，其通常包含使用常规自旋沉积技术沉积的聚酰亚胺，以形成通常包含二氧化硅或氮化硅的无机层的平坦化表面。使用标准光刻胶技术蚀刻无机层以形成用于蚀刻聚合物层的无机掩模。先前沉积的无机层用作蚀刻停止件，以允许长时间的蚀刻以实现完全的外部触点，这反过来允许在多个等级上的高密度互连系统。

7. 发明授权

US06776873B1 Yttrium oxide based surface coating for semiconductor IC processing vacuum chambers 有权
标题翻译：用于半导体IC处理真空室的氧化钇基表面涂层
公开(公告)号：US06776873B1
公开(公告)日：2004-08-17
申请号：US10075967
申请日：2002-02-14
申请人： Jennifer Y Sun , Shun Jackson Wu , Senh Thach , Ananda H Kumar , Robert W Wu , Hong Wang , Yixing Lin , Clifford C Stow
发明人： Jennifer Y Sun , Shun Jackson Wu , Senh Thach , Ananda H Kumar , Robert W Wu , Hong Wang , Yixing Lin , Clifford C Stow
IPC分类号： C23F100
CPC分类号： C23C28/00 , C23C16/4404
摘要： To further enhance the chamber material performance of anodized aluminum alloy materials against fluorine and oxygen plasma attack, a ceramic-based surface coating, high purity yttrium oxide coating, is provided on the anodized aluminum alloy parts.
摘要翻译：为了进一步提高阳极氧化铝合金材料对氟和氧等离子体侵蚀的室内材料性能，在阳极氧化铝合金部件上提供陶瓷基表面涂层，高纯度氧化钇涂层。

8. 发明授权

US06379574B1 Integrated post-etch treatment for a dielectric etch process 失效
标题翻译：用于电介质蚀刻工艺的集成后蚀刻处理
公开(公告)号：US06379574B1
公开(公告)日：2002-04-30
申请号：US09320251
申请日：1999-05-26
申请人： Hui Ou-Yang , Chih-Ping Yang , Lin Ye , Robert W. Wu , Chih-Pang Chen , You-Neng Cheng , Yang Chan-Lon , Tong-Yu Chen
发明人： Hui Ou-Yang , Chih-Ping Yang , Lin Ye , Robert W. Wu , Chih-Pang Chen , You-Neng Cheng , Yang Chan-Lon , Tong-Yu Chen
IPC分类号： B44C122
CPC分类号： H01L21/02063 , H01L21/31116
摘要： The present disclosure pertains to an integrated post-etch treatment method which is performed after a dielectric etch process. Using the method of the invention, byproducts formed on the sidewalls of contact vias during the dielectric etch process can be removed efficiently. The method of the invention also reduces or eliminates the problem of polymer accumulation on process chamber surfaces. An overlying photoresist layer and anti-reflection layer are removed during the performance of the post-etch treatment method. Typically, after the etch of a dielectric material to define pattern or interconnect filling spaces, a series of post-etch treatment steps is performed to remove residues remaining on the wafer after the dielectric etch process. According to the method of the present invention, a post-etch treatment method including one or more steps is performed after the dielectric etch process, preferably within the same processing chamber in which the dielectric etch process was performed. The post-etch treatment method comprises exposing a semiconductor structure to a plasma generated from a source gas comprising oxygen, a nitrogen-comprising gas, and a reactive gas comprising hydrogen, carbon, and fluorine. Two optional steps, a flushing step prior to the post-etch treatment and a cleaning step subsequent to the post-etch treatment, can be performed for the purpose of enhancing the fluorine and byproduct removal and post-etch chamber cleaning.
摘要翻译：本公开涉及在电介质蚀刻工艺之后执行的集成后蚀刻处理方法。使用本发明的方法，可以有效地去除在电介质蚀刻工艺期间在接触通孔的侧壁上形成的副产物。本发明的方法还减少或消除了聚合物在处理室表面上积聚的问题。在蚀刻后处理方法的执行期间，去除覆盖的光致抗蚀剂层和抗反射层。通常，在蚀刻电介质材料以限定图案或互连填充空间之后，执行一系列后蚀刻处理步骤以在电介质蚀刻工艺之后去除残留在晶片上的残留物。根据本发明的方法，在电介质蚀刻工艺之后，优选在进行电介质蚀刻工艺的相同处理室内执行包括一个或多个步骤的后蚀刻处理方法。蚀刻后处理方法包括将半导体结构暴露于由包含氧，含氮气体和包含氢，碳和氟的反应性气体的源气体产生的等离子体。可以执行两个可选步骤，即在蚀刻后处理之前的冲洗步骤和在蚀刻后处理之后的清洁步骤，以便增强氟和副产物去除以及蚀刻后清洁。

9. 发明授权

US06361705B1 Plasma process for selectively etching oxide using fluoropropane or fluoropropylene 有权
标题翻译：使用氟丙烷或氟丙烯选择性蚀刻氧化物的等离子体方法
公开(公告)号：US06361705B1
公开(公告)日：2002-03-26
申请号：US09259536
申请日：1999-03-01
申请人： Ruiping Wang , Gerald Z. Yin , Hao A. Lu , Robert W. Wu , Jian Ding
发明人： Ruiping Wang , Gerald Z. Yin , Hao A. Lu , Robert W. Wu , Jian Ding
IPC分类号： H01L21316
CPC分类号： H01L21/31116
摘要： A plasma etch process, particularly applicable to an self-aligned contact etch in a high-density plasma for selectively etching oxide over nitride, although selectivity to silicon is also achieved. In the process, a fluoropropane or a fluoropropylene is a principal etching gas in the presence of a substantial amount of an inactive gas such as argon. Good nitride selectivity has been achieved with hexafluoropropylene (C3F6), octafluoropropane (C3F8), heptafluoropropane (C3HF7), hexafluoropropane (C3H2F6). The process may use one or more of the these gases in proportions to optimize selectivity and a wide process window. Difluoromethane (CH2F2) or other fluorocarbons may be combined with the above gases, particularly with C3F6 for optimum selectivity over other materials without the occurrence of etch stop in narrow contact holes and with a wide process window.
摘要翻译：等离子体蚀刻工艺，特别适用于高密度等离子体中的自对准接触蚀刻，用于选择性地蚀刻氮化物上的氧化物，尽管也可以实现对硅的选择性。在此过程中，氟丙烷或氟丙烯是在大量惰性气体如氩气存在下的主要蚀刻气体。使用六氟丙烯（C 3 F 6），八氟丙烷（C 3 F 8），七氟丙烷（C 3 H F 7），六氟丙烷（C 3 H 2 F 6）已经实现了良好的氮化物选择性。该方法可以使用一种或多种这些气体的比例来优化选择性和宽的工艺窗口。二氟甲烷（CH 2 F 2）或其它碳氟化合物可以与上述气体，特别是与C3F6组合，以优于其他材料的选择性，而不会在狭窄的接触孔和宽的工艺窗口中发生蚀刻停止。

10. 发明授权

US06221782B1 Adjusting DC bias voltage in plasma chamber 失效
公开(公告)号：US06221782B1
公开(公告)日：2001-04-24
申请号：US09287701
申请日：1999-04-06
申请人： Hongching Shan , Evans Y. Lee , Michael D. Welch , Robert W. Wu , Bryan Y. Pu , Paul E. Luscher , James D. Carducci , Richard Blume
发明人： Hongching Shan , Evans Y. Lee , Michael D. Welch , Robert W. Wu , Bryan Y. Pu , Paul E. Luscher , James D. Carducci , Richard Blume
IPC分类号： H01L213065
CPC分类号： H01J37/32834 , H01J37/32477 , H01J37/32623 , H01J37/32706
摘要： A method of adjusting the cathode DC bias in a plasma chamber for fabricating semiconductor devices. A dielectric shield is positioned between the plasma and a selected portion of the electrically grounded components of the chamber, such as the electrically grounded chamber wall. The cathode DC bias is adjusted by controlling one or more of the following parameters: (1) the surface area of the chamber wall or other grounded components which is blocked by the dielectric shield; (2) the thickness of the dielectric; (3) the gap between the shield and the chamber wall; and (4) the dielectric constant of the dielectric material. In an apparatus aspect, the invention is a plasma chamber for fabricating semiconductor devices having an exhaust baffle with a number of sinuous passages. Each passage is sufficiently long and sinuous that no portion of the plasma within the chamber can extend beyond the outlet of the passage. By blocking the plasma from reaching the exhaust pump, the exhaust baffle reduces the deposition of unwanted particles on exhaust pump components. The exhaust baffle also reduces the cathode DC bias by reducing the effective surface area of the electrically grounded chamber wall which couples RF power to the plasma.

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