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1. 发明授权

US08447957B1 Coprocessor interface architecture and methods of operating the same 有权
标题翻译：协处理器接口架构和操作方法相同
公开(公告)号：US08447957B1
公开(公告)日：2013-05-21
申请号：US11598990
申请日：2006-11-14
申请人： Jorge Ernesto Carrillo , Navaneethan Sundaramoorthy , Sivakumar Velusamy , Ralph D. Wittig , Vasanth Asokan
发明人： Jorge Ernesto Carrillo , Navaneethan Sundaramoorthy , Sivakumar Velusamy , Ralph D. Wittig , Vasanth Asokan
IPC分类号： G06F9/345
CPC分类号： G06F13/1684 , G06F9/3455 , G06F9/3881
摘要： A novel coprocessor interface providing memory access without traversing the main processor, and methods of operating the same. A system includes a bus, a processor circuit, a memory circuit, a multi-channel memory controller, and at least one coprocessor. The processor circuit is coupled to the bus, the multi-channel memory controller is coupled between the bus and the memory circuit, and the coprocessors are coupled to both the processor circuit and the multi-channel memory controller. This circuit arrangement provides dedicated high speed channels for data access between the coprocessors and the memory circuit, without traversing the processor circuit or the bus. Thus, non-standard (e.g., non-sequential) data transfer protocols can be supported. In some embodiments, the system is implemented in a programmable logic device (PLD). The processor circuit can be, for example, a microprocessor included as hard-coded logic in the PLD, or can be implemented using programmable logic elements of the PLD.
摘要翻译：一种新颖的协处理器接口，无需遍历主处理器即可提供存储器访问，以及操作该处理器的方法。系统包括总线，处理器电路，存储器电路，多通道存储器控制器和至少一个协处理器。处理器电路耦合到总线，多通道存储器控制器耦合在总线和存储器电路之间，并且协处理器耦合到处理器电路和多通道存储器控制器两者。该电路装置为协处理器和存储器电路之间的数据访问提供了专用的高速通道，而不用遍历处理器电路或总线。因此，可以支持非标准（例如非顺序）数据传输协议。在一些实施例中，系统在可编程逻辑器件（PLD）中实现。处理器电路可以是例如包括在PLD中作为硬编码逻辑的微处理器，或者可以使用PLD的可编程逻辑元件来实现。

2. 发明授权

US08296557B1 Providing multiple selectable configuration sources for programmable integrated circuits with fail safe mechanism 有权
标题翻译：为具有故障安全机制的可编程集成电路提供多种可选配置源
公开(公告)号：US08296557B1
公开(公告)日：2012-10-23
申请号：US12609174
申请日：2009-10-30
申请人： Richard S. Ballantyne , Mark Paluszkiewicz , Henry E. Styles , Ralph D. Wittig
发明人： Richard S. Ballantyne , Mark Paluszkiewicz , Henry E. Styles , Ralph D. Wittig
IPC分类号： G06F1/24 , G06F9/00
CPC分类号： G06F15/7871 , H03K19/1776 , H03K19/17768
摘要： Within a system comprising a programmable integrated circuit (IC), a method can include storing a first configuration within the system in a read-only memory that is independent of the programmable IC. The programmable IC, being loaded with the first configuration, comprises a circuit that accesses a data source external to the system over a communication link. A second configuration can be downloaded by the programmable IC from the data source. The second configuration can be stored within a random access memory within the system that is independent of the programmable IC. Responsive to a reconfiguration event, the programmable IC can be loaded with the second configuration from the random access memory.
摘要翻译：在包括可编程集成电路（IC）的系统中，一种方法可以包括将系统内的第一配置存储在独立于可编程IC的只读存储器中。被加载了第一配置的可编程IC包括通过通信链路访问系统外部的数据源的电路。可由可编程IC从数据源下载第二配置。第二配置可以存储在系统内的与可编程IC无关的随机存取存储器中。响应于重新配置事件，可编程IC可以从随机存取存储器加载第二配置。

3. 发明授权

US07248073B2 Configurable logic element with expander structures 有权
标题翻译：具有扩展器结构的可配置逻辑元件
公开(公告)号：US07248073B2
公开(公告)日：2007-07-24
申请号：US11585534
申请日：2006-10-24
申请人： Bernard J. New , Ralph D. Wittig , Sundararajarao Mohan
发明人： Bernard J. New , Ralph D. Wittig , Sundararajarao Mohan
IPC分类号： H01L25/00 , H03K19/77
CPC分类号： H03K19/17748 , H03K19/1731 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.
摘要翻译：用于现场可编程门阵列（FPGA）的可配置逻辑元件（CLE）包括“扩展器”，即允许逻辑块之间的快速信号通信的连接器。扩展器允许多个逻辑块或其部分的可配置互连形成可以实现诸如PAL，查找表，多路复用器，三态缓冲器和存储器之类的大型用户电路的单个逻辑实体。一个实施例包括可配置逻辑块。在第一模式中，逻辑块提供具有N个共享输入和两个单独输出的两个N输入LUT。然后使用扩展器组合输出以产生（N + 1） - 输入功能。在第二模式中，逻辑块提供具有M个非共享输入的两个N输入LUT。可选的第三模式基于N个输入信号的值提供多个产品项输出信号。

4. 发明授权

US06208163B1 FPGA configurable logic block with multi-purpose logic/memory circuit 有权
标题翻译：具有多用途逻辑/存储器电路的FPGA可配置逻辑块
公开(公告)号：US06208163B1
公开(公告)日：2001-03-27
申请号：US09333822
申请日：1999-06-15
申请人： Ralph D. Wittig , Sundararajarao Mohan , Richard A. Carberry
发明人： Ralph D. Wittig , Sundararajarao Mohan , Richard A. Carberry
IPC分类号： G06F738
CPC分类号： H03K19/1776 , H03K19/1737 , H03K19/17728 , H03K19/17792
摘要： A logic/memory circuit (LMC) utilized in a configurable logic block (CLB) of a programmable logic device (PLD) that implements an eight-input lookup table (LUT) using an array of programmable elements arranged in rows and columns. A decoder is used to read bit values from one column (e.g., sixteen programmable elements) of the array. In one embodiment, a separate read bit line is provided to facilitate faster read operations. A sixteen-to-one multiplexer/demultiplexer circuit is used to pass selected bit values to an output terminal. The array of programmable elements is programmable both from configuration lines during a configuration mode, and by data transmitted on the interconnect resources through the multiplexer/demultiplexer circuit. In one embodiment, the programmable elements of the array are connected in pairs to product term generation circuitry, and input signals to the array are routed onto bit lines that are also connected to the product term generation circuitry. Product terms generated by the product term circuitry are passed to a macrocell circuit to perform programmable array logic (PAL) logic operations.
摘要翻译：在可编程逻辑器件（PLD）的可配置逻辑块（CLB）中使用的逻辑/存储器电路（LMC），其使用以行和列布置的可编程元件阵列来实现八输入查找表（LUT）。解码器用于读取阵列的一列（例如十六个可编程元件）的位值。在一个实施例中，提供单独的读取位线以便于更快的读取操作。使用十六对一多路复用器/解复用器电路将所选择的比特值传送到输出端。可编程元件的阵列可以在配置模式期间由配置线以及通过多路复用器/解复用器电路在互连资源上传输的数据进行编程。在一个实施例中，阵列的可编程元件成对连接到产品项产生电路，并且到阵列的输入信号被路由到也连接到产品项产生电路的位线上。由产品术语电路生成的产品术语被传递到宏单元电路以执行可编程阵列逻辑（PAL）逻辑运算。

5. 发明授权

US6150838A FPGA configurable logic block with multi-purpose logic/memory circuit 有权
标题翻译：具有多用途逻辑/存储器电路的FPGA可配置逻辑块
公开(公告)号：US6150838A
公开(公告)日：2000-11-21
申请号：US258024
申请日：1999-02-25
申请人： Ralph D. Wittig , Sundararajarao Mohan , Richard A. Carberry
发明人： Ralph D. Wittig , Sundararajarao Mohan , Richard A. Carberry
IPC分类号： H03K19/173 , H03K19/177 , G06F7/38
CPC分类号： H03K19/1776 , H03K19/1737 , H03K19/17728 , H03K19/17792
摘要： A logic/memory circuit (LMC) utilized in a configurable logic block (CLB) of a programmable logic device (PLD) that implements an eight-input lookup table (LUT) using an array of programmable elements arranged in rows and columns. A decoder is used to read bit values from one column (e.g., sixteen programmable elements) of the array. In one embodiment, a separate read bit line is provided to facilitate faster read operations. A sixteen-to-one multiplexer/demultiplexer circuit is used to pass selected bit values to an output terminal. The array of programmable elements is programmable both from configuration lines during a configuration mode, and by data transmitted on the interconnect resources through the multiplexer/demultiplexer circuit. In one embodiment, the programmable elements of the array are connected in pairs to product term generation circuitry. Product terms generated by the product term circuitry are passed to a macrocell circuit to perform programmable array logic (PAL) logic operations. In another embodiment, a CLB includes four LMCs and a multiplier circuit such that large amounts of logic are locally implemented, thereby avoiding signal delays associated with transmission over general purpose interconnect resources within a PLD.
摘要翻译：在可编程逻辑器件（PLD）的可配置逻辑块（CLB）中使用的逻辑/存储器电路（LMC），其使用以行和列布置的可编程元件阵列来实现八输入查找表（LUT）。解码器用于读取阵列的一列（例如十六个可编程元件）的位值。在一个实施例中，提供单独的读取位线以便于更快的读取操作。使用十六对一多路复用器/解复用器电路将所选择的比特值传送到输出端。可编程元件的阵列可以在配置模式期间由配置线以及通过多路复用器/解复用器电路在互连资源上传输的数据进行编程。在一个实施例中，阵列的可编程元件成对连接到产品项产生电路。由产品术语电路生成的产品术语被传递到宏单元电路以执行可编程阵列逻辑（PAL）逻辑运算。在另一个实施例中，CLB包括四个LMC和乘法器电路，使得大量逻辑被本地实现，从而避免与PLD内的通用互连资源上的传输相关联的信号延迟。

6. 发明申请

US20100183081A1 GENERIC BUFFER CIRCUITS AND METHODS FOR OUT OF BAND SIGNALING 有权
标题翻译：一般缓冲电路和带状信号的方法
公开(公告)号：US20100183081A1
公开(公告)日：2010-07-22
申请号：US12357369
申请日：2009-01-21
申请人： Richard S. Ballantyne , Catalin Baetoniu , Mark Paluszkiewicz , Henry E. Styles , Ralph D. Wittig
发明人： Richard S. Ballantyne , Catalin Baetoniu , Mark Paluszkiewicz , Henry E. Styles , Ralph D. Wittig
IPC分类号： H04B3/00
CPC分类号： G06F13/4072
摘要： Circuits and methods for a differential signal interface for coupling differential signals at a first frequency on a pair of opposite polarity signals to a multiple gigabit transceiver with generic buffers for receiving, transmitting or transceiving out of band signals at a second frequency lower than the first frequency are disclosed. Termination networks are provided coupling generic input buffers to respective ones of the pair of opposite polarity signals for receiving out of band signals where the opposite polarity signals are placed at voltages so that the differential voltage between them is below a threshold voltage. Methods for providing generic buffers with multiple gigabit transceivers for receiving and transmitting out of band signals on a differential signal interface are provided. Out of band signals are received when the out of band signaling protocol is not known.
摘要翻译：差分信号接口的电路和方法，用于将一对相反极性信号上的第一频率的差分信号耦合到具有用于以比第一频率低的第二频率接收，发射或收发带外信号的多吉比特收发器被披露。提供了端接网络，其将通用输入缓冲器耦合到一对相反极性信号中的相应极性信号，用于接收带外信号，其中相反极性信号被置于电压处，使得它们之间的差分电压低于阈值电压。提供了用于向通用缓冲器提供用于在差分信号接口上接收和发送带外信号的多个千兆位收发器的方法。当带外信令协议不知道时，接收带外信号。

7. 发明授权

US07721090B1 Event-driven simulation of IP using third party event-driven simulators 有权
标题翻译：使用第三方事件驱动模拟器进行事件驱动的IP仿真
公开(公告)号：US07721090B1
公开(公告)日：2010-05-18
申请号：US11370116
申请日：2006-03-07
申请人： Kumar Deepak , Satish R. Ganesan , Jimmy Zhenming Wang , Sundararajarao Mohan , Ralph D. Wittig , Hem C. Neema
发明人： Kumar Deepak , Satish R. Ganesan , Jimmy Zhenming Wang , Sundararajarao Mohan , Ralph D. Wittig , Hem C. Neema
IPC分类号： H04L29/06 , G06F21/00 , G06F12/14 , G06F17/50
CPC分类号： G06F21/12 , G06F17/5022 , G06F21/10 , G06F21/76 , G06F2217/66
摘要： A method of creating a secure intellectual property (IP) representation of a circuit design for use with a software-based simulator can include translating a hardware description language representation of the circuit design into an encrypted intermediate form and compiling the intermediate form of the circuit design to produce encrypted object code. The method further can include linking the encrypted object code with a simulation kernel library thereby creating the secure IP representation of the circuit design. The secure IP can include an encrypted simulation model of the circuit design and a simulation kernel configured to execute the encrypted simulation model.
摘要翻译：创建用于与基于软件的模拟器一起使用的电路设计的安全知识产权（IP）表示的方法可以包括将电路设计的硬件描述语言表示转换为加密的中间形式并编译电路设计的中间形式以产生加密的对象代码。该方法还可以包括将加密的对象代码与仿真内核库链接，从而创建电路设计的安全IP表示。安全IP可以包括电路设计的加密仿真模型和被配置为执行加密仿真模型的仿真内核。

8. 发明授权

US07310594B1 Method and system for designing a multiprocessor 有权
标题翻译：用于设计多处理器的方法和系统
公开(公告)号：US07310594B1
公开(公告)日：2007-12-18
申请号：US10295687
申请日：2002-11-15
申请人： Satish R. Ganesan , Usha Prabhu , Sundararajarao Mohan , Ralph D. Wittig , David W. Bennett
发明人： Satish R. Ganesan , Usha Prabhu , Sundararajarao Mohan , Ralph D. Wittig , David W. Bennett
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/86
摘要： A multiprocessor system (10) includes a plurality of processing engines (14, 16, 18, 20, 22, 32, 33 and 35) including a software processing engine and a hardware processing engine implemented on a single silicon device defined by a single programming language and the single programming language tagged with at least one macro. The multiprocessor system further includes connectivity (37 and 40) between the plurality of processing engines defined by the single programming language and by the single programming language tagged with at least one macro.
摘要翻译：多处理器系统（10）包括多个处理引擎（14,16,18,20,22,32,33和35），其包括软件处理引擎和在由单个编程定义的单个硅器件上实现的硬件处理引擎语言和使用至少一个宏标记的单一编程语言。多处理器系统还包括由单个编程语言定义的多个处理引擎与由至少一个宏标记的单个编程语言之间的连接（37和40）。

9. 发明授权

US06803786B1 Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks 有权
标题翻译：在逻辑块阵列中提供紧密耦合的处理器和RAM块列的结构和方法
公开(公告)号：US06803786B1
公开(公告)日：2004-10-12
申请号：US10386955
申请日：2003-03-11
申请人： Goran Bilski , Ralph D. Wittig , Jennifer Wong , David B. Squires
发明人： Goran Bilski , Ralph D. Wittig , Jennifer Wong , David B. Squires
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , G06F15/7867 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.
摘要翻译：在现有PLD架构中包含处理器能力的结构和方法，对现有的一般互连结构的影响最小。在包括块RAM（BRAM）块列的PLD中，BRAM块被修改以创建专用的逻辑块，包括RAM，处理器和耦合在RAM，处理器和通用互连结构之间的专用接口 PLD。通过增加BRAM块的列的宽度来获得附加区域。因为互连结构几乎保持不变，所以专用逻辑块和相邻的瓦片之间的互连已经就位，并且修改不影响PLD路由软件。在一些实施例中，处理器可以可选地被禁用，对于用户变得透明。其他实施例提供了修改PLD以包括结构并提供上述能力的方法。

10. 发明授权

US06630841B2 Configurable logic element with expander structures 有权
公开(公告)号：US06630841B2
公开(公告)日：2003-10-07
申请号：US10097522
申请日：2002-03-12
申请人： Bernard J. New , Ralph D. Wittig , Sundararajarao Mohan
发明人： Bernard J. New , Ralph D. Wittig , Sundararajarao Mohan
IPC分类号： H01L2500
CPC分类号： H03K19/17748 , H03K19/1731 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

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