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    • 3. 发明授权
    • Synchronization of parallel memory accesses in a dataflow circuit
    • 数据流电路中并行存储器访问的同步
    • US08473880B1
    • 2013-06-25
    • US12791256
    • 2010-06-01
    • David W. BennettPrasanna Sundararajan
    • David W. BennettPrasanna Sundararajan
    • G06F17/50
    • G06F17/505G06F2217/74
    • Approaches for creating a pipelined circuit design from a high level language (HLL) specification. In one embodiment, the HLL specification is translated into an intermediate level language specification of operations of the pipelined circuit design, and a data dependency graph of the operations is created. A sequence of operations that is bounded by two write operations and that has no intervening write operations between the two write operations is identified, along with two or more read operations within the sequence. A pipelined design specification is generated from the dependency graph and hardware components associated with the operations in the intermediate level language specification. At least two of the components corresponding to the two or more read operations access a memory in parallel, and each component corresponding to the two or more read and the two write operations requires a synchronization token as input and outputs a synchronization token upon completion of the operation.
    • 从高级语言(HLL)规范创建流水线电路设计的方法。 在一个实施例中,HLL规范被转换成流水线电路设计的操作的中间级语言规范,并且创建操作的数据依赖图。 识别由两个写入操作限定并且在两个写入操作之间没有中间写入操作的操作序列以及序列内的两个或更多个读取操作。 从与中级语言规范中的操作相关联的依赖图和硬件组件生成流水线设计规范。 对应于两个或多个读取操作的组件中的至少两个组件并行访问存储器,并且对应于两个或多个读取和两个写入操作的每个组件需要同步令牌作为输入,并且在完成时输出同步令牌 操作。
    • 7. 发明授权
    • Pipeline expansion joint having a smooth bore
    • 管道膨胀节具有光滑的孔
    • US3936080A
    • 1976-02-03
    • US474768
    • 1974-05-30
    • David W. Bennett
    • David W. Bennett
    • F16L51/00F16L55/00
    • F16L51/00F16L55/00
    • A pipeline expansion joint having a smooth bore, for use with pipelines into which flow slurries containing solids in suspension, comprises a first sleeve open at both ends and having a tapered portion formed in the inner wall of one of its ends extending at a small angle with the axis of the first sleeve and over a substantial portion of the length of the first sleeve from its inside diameter to substantially its outside diameter, and a second sleeve also open at both ends and having a first portion of substantially the same inner diameter as the outer diameter of the first sleeve and telescopically mounted on the above-mentioned one end of the first sleeve, a second portion of the same diameter as the first sleeve, and an intermediate portion expanded at a small angle with the axis of the second sleeve over a substantial portion of its length from the second to the first portion of such second sleeve. The above expansion joint has a smooth bore throughout with no area of abrupt changes in order to prevent turbulence and the resulting wear due to the solids in suspension in the slurries.
    • 一种具有光滑孔的管道膨胀接头,用于与其中含有悬浮物中的固体的流动浆料的管道一起使用,其包括在两端开口的第一套筒,并且具有形成在其一端的内壁中的锥形部分,其以小角度延伸 第一套筒的轴线和第一套筒的长度的大部分从其内径到其大致的外径,并且第二套筒也在两端开口,并且具有与第一套筒基本上相同的内径的第一部分 第一套筒的外径和可伸缩地安装在第一套筒的上述一端上,与第一套筒直径相同的第二部分,以及与第二套筒的轴线成小角度膨胀的中间部分 在其长度的大部分上从第二套筒的第二部分到第一部分。 上述膨胀接头在没有突然变化的区域中具有光滑的孔,以防止由于浆料中的悬浮液中的固体而产生的湍流和由此产生的磨损。
    • 8. 发明申请
    • METHOD FOR SELECTIVE DEPOSITION OF DIELECTRIC LAYERS ON SEMICONDUCTOR STRUCTURES
    • 在半导体结构上选择性沉积介质层的方法
    • US20110053336A1
    • 2011-03-03
    • US12553261
    • 2009-09-03
    • Kiuchul HwangDavid W. BennettHuy Q. Nguyen
    • Kiuchul HwangDavid W. BennettHuy Q. Nguyen
    • H01L21/02
    • H01L27/0629H01L21/8252H01L27/0605H01L28/40
    • A method for forming a capacitor and a transistor device on different surface portions of a semiconductor structure includes forming a passivation dielectric layer for the device; forming a bottom electrode for the capacitor; forming a removable layer extending over the bottom electrode and over the passivation dielectric layer with a window therein, such window exposing said bottom electrode; depositing a capacitor dielectric layer of the same or different material as the passivation dielectric layer over the removable layer with first portions passing through the window onto the exposed bottom electrode and second portions being over the removable layer, the thickness of the deposited layer being different from the thickness of the passivation layer; removing the removable layer with the second portions thereon while leaving said first portions on the bottom electrode; and forming a top electrode for the capacitor on the second portions remaining on the bottom electrode.
    • 一种用于在半导体结构的不同表面部分上形成电容器和晶体管器件的方法包括形成用于器件的钝化介质层; 形成电容器的底部电极; 形成在所述底部电极上延伸并且在所述钝化介电层上方具有窗口的可移除层,所述窗口暴露所述底部电极; 在可移除层上沉积与钝化介电层相同或不同的材料的电容器电介质层,其中第一部分通过窗口穿过暴露的底部电极,第二部分在可移除层之上,沉积层的厚度不同于 钝化层的厚度; 在其上留下所述第一部分在底部电极上去除其上的第二部分的可移除层; 并且在残留在底部电极上的第二部分上形成用于电容器的顶部电极。
    • 9. 发明授权
    • Modular design method and system for programmable logic devices
    • 可编程逻辑器件的模块化设计方法和系统
    • US06817005B2
    • 2004-11-09
    • US09839464
    • 2001-04-20
    • Jeffrey M. MasonSteve E. LassBruce E. TalleyDavid W. Bennett
    • Jeffrey M. MasonSteve E. LassBruce E. TalleyDavid W. Bennett
    • G06F1750
    • G06F17/5054G06F17/5072
    • In modular design flow, logic designers are able to partition a top-level logic design for a PLD into modules and implement any module independently from other modules. Modules are mapped, placed, and routed using selected information derived at the time the top-level logic design is partitioned. Finally, the modules are integrated into the top-level logic design using a guided process. Specifically, the information generated during the partitioning of the top-level design and the implementation of each module is used to guide the implementation of the associated logic in the top-level design. In this manner, the implementation of all modules can proceed in any order or in parallel and the integration of the modules into the top-level design can be done quickly and in any order.
    • 在模块化设计流程中,逻辑设计人员可以将PLD的顶级逻辑设计分为模块,并独立于其他模块实现任何模块。 使用在顶层逻辑设计分区时导出的所选信息对模块进行映射,放置和布线。 最后,使用引导过程将模块集成到顶级逻辑设计中。 具体来说,在顶层设计分区和每个模块的实现过程中生成的信息用于指导顶层设计中相关逻辑的实现。 以这种方式,所有模块的实现可以以任何顺序或并行进行,并且将模块集成到顶层设计中可以以任何顺序快速完成。