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1. 发明授权

US07310594B1 Method and system for designing a multiprocessor 有权
标题翻译：用于设计多处理器的方法和系统
公开(公告)号：US07310594B1
公开(公告)日：2007-12-18
申请号：US10295687
申请日：2002-11-15
申请人： Satish R. Ganesan , Usha Prabhu , Sundararajarao Mohan , Ralph D. Wittig , David W. Bennett
发明人： Satish R. Ganesan , Usha Prabhu , Sundararajarao Mohan , Ralph D. Wittig , David W. Bennett
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/86
摘要： A multiprocessor system (10) includes a plurality of processing engines (14, 16, 18, 20, 22, 32, 33 and 35) including a software processing engine and a hardware processing engine implemented on a single silicon device defined by a single programming language and the single programming language tagged with at least one macro. The multiprocessor system further includes connectivity (37 and 40) between the plurality of processing engines defined by the single programming language and by the single programming language tagged with at least one macro.
摘要翻译：多处理器系统（10）包括多个处理引擎（14,16,18,20,22,32,33和35），其包括软件处理引擎和在由单个编程定义的单个硅器件上实现的硬件处理引擎语言和使用至少一个宏标记的单一编程语言。多处理器系统还包括由单个编程语言定义的多个处理引擎与由至少一个宏标记的单个编程语言之间的连接（37和40）。

2. 发明授权

US07243330B1 Method and apparatus for providing self-implementing hardware-software libraries 有权
标题翻译：提供自我执行硬件 - 软件库的方法和装置
公开(公告)号：US07243330B1
公开(公告)日：2007-07-10
申请号：US11111339
申请日：2005-04-21
申请人： Satish R. Ganesan , Amit Kasat , Sathyanarayanan Thammanur , Sundararajarao Mohan , Usha Prabhu , Ralph D. Wittig
发明人： Satish R. Ganesan , Amit Kasat , Sathyanarayanan Thammanur , Sundararajarao Mohan , Usha Prabhu , Ralph D. Wittig
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Method and apparatus for providing self-implementing hardware-software libraries is described. One aspect of the invention relates to designing an embedded system for an integrated circuit. A hardware platform is defined. A software platform is defined having a plurality of software components, including a library. Hardware component dependency data associated with the library is identified. At least one hardware component is added to the hardware platform in response to the hardware component dependency data.
摘要翻译：描述了用于提供自实施硬件 - 软件库的方法和装置。本发明的一个方面涉及设计用于集成电路的嵌入式系统。定义了一个硬件平台。定义了一个包含多个软件组件（包括一个库）的软件平台。识别与库关联的硬件组件依赖性数据。响应于硬件组件依赖性数据，至少一个硬件组件被添加到硬件平台。

3. 发明授权

US07340585B1 Method and system for fast linked processor in a system on a chip (SoC) 有权
标题翻译：芯片系统中快速链接处理器的方法与系统（SoC）
公开(公告)号：US07340585B1
公开(公告)日：2008-03-04
申请号：US10229543
申请日：2002-08-27
申请人： Satish R. Ganesan , Goran Bilski , Usha Prabhu , Ralph D. Wittig
发明人： Satish R. Ganesan , Goran Bilski , Usha Prabhu , Ralph D. Wittig
IPC分类号： G06F15/17 , G06F15/80
CPC分类号： G06F15/7867
摘要： A fast linked multiprocessor network (22) including a plurality of processing modules (24, 26, 28, 30, 32, and 34) implemented on a field programmable gate array (10) and a plurality of configurable uni-directional links (21, 23, 25, 27, 29, 31) coupled among at least two of the plurality processing modules providing a streaming communication channel between at least two of the plurality of processing modules.
摘要翻译：一种快速链接多处理器网络（22），包括在现场可编程门阵列（10）上实现的多个处理模块（24,26,28,30,32,34）和多个可配置单向链路（21， 23,25,27,29,31），其耦合到所述多个处理模块中的至少两个处理模块中，以提供所述多个处理模块中的至少两个之间的流传输通信信道。

4. 发明授权

US07131091B1 Generating fast logic simulation models for a PLD design description 有权
标题翻译：为PLD设计描述生成快速逻辑仿真模型
公开(公告)号：US07131091B1
公开(公告)日：2006-10-31
申请号：US10930430
申请日：2004-08-31
申请人： Satish R. Ganesan , Goran Bilski , Usha Prabhu , Paulo L. Dutra
发明人： Satish R. Ganesan , Goran Bilski , Usha Prabhu , Paulo L. Dutra
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Various approaches for generating a clock accurate simulation model from a circuit design description are disclosed. In one approach, a graph representation of the circuit design description is created. The graph representation includes nodes and edges. From the nodes in the graph representation, a plurality of register nodes are generated to correspond to respective register functions. Logic optimization is performed on nodes that represent combinational logic functions. For each register node and each output node, an evaluation equation is generated after performing logic optimization. For each clock cycle of a logic simulation, each evaluation equation is evaluated and produces an output value for the next clock cycle.
摘要翻译：公开了从电路设计描述产生时钟精确仿真模型的各种方法。在一种方法中，创建电路设计描述的图形表示。图形表示包括节点和边。从图形表示中的节点，生成多个寄存器节点以对应于相应的寄存器功能。在表示组合逻辑功能的节点上执行逻辑优化。对于每个寄存器节点和每个输出节点，在执行逻辑优化之后生成评估方程。对于逻辑仿真的每个时钟周期，评估每个评估方程，并产生下一个时钟周期的输出值。

5. 发明授权

US07490227B1 Method and system to recreate instruction and data traces in an embedded processor 有权
标题翻译：在嵌入式处理器中重新创建指令和数据跟踪的方法和系统
公开(公告)号：US07490227B1
公开(公告)日：2009-02-10
申请号：US10930437
申请日：2004-08-31
申请人： Goran Bilski , Jorge Ernesto Carrillo , Usha Prabhu , Navaneethan Sundaramoorthy
发明人： Goran Bilski , Jorge Ernesto Carrillo , Usha Prabhu , Navaneethan Sundaramoorthy
IPC分类号： G06F11/25
CPC分类号： G06F11/3476
摘要： A method of recreating instructions and data traces in a processor can include the step of fetching an instruction from an executable program in an order corresponding to sequential program counter (PC) values, obtaining a destination register from the fetched instruction and updating the destination register in a data structure with a value from a collected destination register corresponding to the PC value. The steps above can be repeated until all desired PC values and destination values are obtained.
摘要翻译：在处理器中重建指令和数据迹线的方法可以包括以与顺序程序计数器（PC）值相对应的顺序从可执行程序获取指令的步骤，从获取的指令获取目的地寄存器并且更新目的地寄存器具有来自与PC值相对应的收集的目的地寄存器的值的数据结构。可以重复上述步骤，直到获得所有期望的PC值和目标值。

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