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1. 发明授权

US06693291B2 Device and system for improved imaging in nuclear medicine and mammography 失效
标题翻译：用于改善核医学和乳腺摄影术成像的装置和系统
公开(公告)号：US06693291B2
公开(公告)日：2004-02-17
申请号：US10461242
申请日：2003-06-13
申请人： Robert Sigurd Nelson , William Bert Nelson
发明人： Robert Sigurd Nelson , William Bert Nelson
IPC分类号： H01L2500
CPC分类号： A61B6/502 , A61B6/037 , A61B6/4028 , A61B6/4233 , A61B6/4258 , A61B6/4291 , A61B6/4488 , A61B6/548 , G01T1/1644 , G01T1/243 , G01T1/244 , G01T1/2928
摘要： A method and apparatus for detecting radiation including x-ray, gamma ray, and particle radiation for radiographic imaging, and nuclear medicine and x-ray mammography in particular, and material composition analysis are described. A detection system employs fixed or configurable arrays of one or more detector modules comprising detector arrays which may be electronically manipulated through a computer system. The detection system, by providing the ability for electronic manipulation, permits adaptive imaging. Detector array configurations include familiar geometries, including slit, slot, plane, open box, and ring configurations, and customized configurations, including wearable detector arrays, that are customized to the shape of the patient. Conventional, such as attenuating, rigid geometry, and unconventional collimators, such as x-ray optic, configurable, Compton scatter modules, can be selectively employed with detector modules and radiation sources. The components of the imaging chain can be calibrated or corrected using processes of the invention. X-ray mammography and scintimammography are enhanced by utilizing sectional compression and related imaging techniques.
摘要翻译：描述了用于检测放射线成像的X射线，γ射线和粒子辐射以及核医学和X射线乳腺摄影的辐射的方法和装置，以及材料成分分析。检测系统采用一个或多个检测器模块的固定或可配置阵列，其包括可以通过计算机系统电子操作的检测器阵列。检测系统通过提供电子操纵的能力，允许自适应成像。检测器阵列配置包括熟悉的几何形状，包括狭缝，槽，平面，开箱和环形配置，以及根据患者形状定制的定制配置，包括可穿戴式检测器阵列。常规的，例如衰减，刚性几何形状和非常规准直器，例如x射线光学器件，可配置的康普顿散射模块，可以选择性地与检测器模块和辐射源一起使用。可以使用本发明的方法校准或校正成像链的部件。通过利用截面压缩和相关成像技术增强X射线乳腺摄影和闪烁扫描。

2. 发明授权

US06671202B1 Programmable circuit structures with reduced susceptibility to single event upsets 有权
标题翻译：可编程电路结构，降低了对单次事件的影响
公开(公告)号：US06671202B1
公开(公告)日：2003-12-30
申请号：US10172835
申请日：2002-06-13
申请人： Trevor J. Bauer
发明人： Trevor J. Bauer
IPC分类号： H01L2500
CPC分类号： G11C7/24 , G11C7/20 , H01L27/105 , H03K19/00338
摘要： Programmable circuit structures having reduced susceptibility to single event upsets. A circuit structure includes a programmable circuit controlled by a group of memory cells, of which at most one has an enable value. The memory cells are coupled together such that if any one memory cell in the group is at the enable value, then all other memory cells in the group are forced to a disable value. If a single event upset occurs at any of the disabling memory cells the value in the memory cell does not change, because the memory cell is being held disabling by the one enabling memory cell. However, if a single event upset occurs at the enabling memory cell, causing it to become disabling, a circuit error occurs. Thus, the susceptibility of the circuit structure has been reduced by a factor of (N−1)/N, where N is the number of memory cells.
摘要翻译：可编程电路结构具有降低的对单个事件扰乱的敏感性。电路结构包括由一组存储器单元控制的可编程电路，其中最多一个具有使能值。存储器单元耦合在一起，使得如果组中的任何一个存储器单元处于使能值，则该组中的所有其他存储器单元被强制为禁用值。如果在任何禁用存储器单元中发生单个事件不适，则存储器单元中的值不改变，因为存储器单元被一个使能存储器单元禁止。但是，如果在使能存储单元发生单个事件不正常，导致其变为禁止，则会发生电路错误。因此，电路结构的敏感性已经降低了（N-1）/ N的因子，其中N是存储器单元的数量。

3. 发明授权

US06600364B1 Active interposer technology for high performance CMOS packaging application 有权
标题翻译：高性能CMOS封装应用的主动插入式技术
公开(公告)号：US06600364B1
公开(公告)日：2003-07-29
申请号：US09225418
申请日：1999-01-05
申请人： Chunlin Liang , Xiao-Chun Mu
发明人： Chunlin Liang , Xiao-Chun Mu
IPC分类号： H01L2500
CPC分类号： H01L23/50 , G11C7/02 , H01L23/49827 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2924/00014 , H01L2924/15311 , H01L2924/3025 , H01L2924/00 , H01L2224/05599
摘要： An integrated circuit assembly that includes an integrated circuit which is connected to an interposer. The integrated circuit may include a logic circuit which generates an output signal. The interposer may include a driver circuit that regenerates the output signal. The interposer may also contain a clock signal that is connected to the logic circuit. Separating the driver circuit from the integrated circuit may provide an assembly which reduces the amount of noise in the logic circuit created by the driver circuit switching states. Additionally, providing the clock circuit on the interposer allows the clock to be fabricated with a more robust process than the logic circuit of the integrated circuit.
摘要翻译：一种集成电路组件，其包括连接到插入器的集成电路。集成电路可以包括产生输出信号的逻辑电路。插入器可以包括再生输出信号的驱动器电路。插入器还可以包含连接到逻辑电路的时钟信号。将驱动器电路与集成电路分离可以提供一种组件，其减少由驱动器电路切换状态产生的逻辑电路中的噪声量。此外，在插入器上提供时钟电路允许使用比集成电路的逻辑电路更稳健的处理来制造时钟。

4. 发明授权

US06573620B1 Method and apparatus for automatically identifying a central processing unit 失效
标题翻译：用于自动识别中央处理单元的方法和装置
公开(公告)号：US06573620B1
公开(公告)日：2003-06-03
申请号：US09001774
申请日：1997-12-31
申请人： Dennis Craig , James Noble
发明人： Dennis Craig , James Noble
IPC分类号： H01L2500
CPC分类号： H05K1/141 , H05K1/0268 , H05K2201/09954 , H05K2201/10189 , Y10T307/858
摘要： A microprocessor assembly is located on a daughterboard, which is configured to be physically and electrically coupled to a motherboard. One of the electrical terminals in an electrical connector between the daughterboard/motherboard is coupled to either a ground or a voltage supply Vdd on the daughterboard, depending on the type of microprocessor used. The electrical connector passes either the ground or Vdd signal to a semiconductor device on the motherboard to automatically identify the type of microprocessor on the daughterboard.
摘要翻译：微处理器组件位于子板上，其被配置为物理地和电耦合到主板。取决于所使用的微处理器的类型，子板/母板之间的电连接器中的一个电端子被耦合到子板上的接地或电压源Vdd。电连接器将接地或Vdd信号传递到主板上的半导体器件，以自动识别子板上的微处理器类型。

5. 发明授权

US06570161B2 X-ray detecting device and fabricating method thereof 有权
标题翻译： X射线检测装置及其制造方法
公开(公告)号：US06570161B2
公开(公告)日：2003-05-27
申请号：US09749671
申请日：2000-12-28
申请人： Myung Ho You , Byoung Ho Lim
发明人： Myung Ho You , Byoung Ho Lim
IPC分类号： H01L2500
CPC分类号： H01L27/14658
摘要： An X-ray detecting device and a fabricating method thereof capable of preventing a short between a lower electrode of a capacitor and a data line are presented. In the device, a data line insulating layer is formed to cover the data line and a gate line. The gate line is exposed through a contact hole defined in the data line insulating. Then a lower electrode is formed on the data line insulating layer and is electrically connected to the gate line via the contact hole. Subsequently, an upper electrode is formed to complete the device. The data line insulating layer prevents a short between the data line and the lower electrode when residual conductive materials are formed when the lower electrode is formed.
摘要翻译：提出了能够防止电容器的下部电极与数据线之间短路的X射线检测装置及其制造方法。在该器件中，形成数据线绝缘层以覆盖数据线和栅极线。栅极线通过数据线绝缘中限定的接触孔露出。然后在数据线绝缘层上形成下电极，并通过接触孔与栅极线电连接。随后，形成上电极以完成该装置。当形成下电极时，当残留的导电材料形成时，数据线绝缘层防止数据线和下电极之间的短路。

6. 发明授权

US06563340B1 Architecture for implementing two chips in a package 有权
标题翻译：在一个包中实现两个芯片的架构
公开(公告)号：US06563340B1
公开(公告)日：2003-05-13
申请号：US09862668
申请日：2001-05-21
申请人： Christopher W. Jones
发明人： Christopher W. Jones
IPC分类号： H01L2500
CPC分类号： H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： A device having two or more programmable logic devices within an assembly apparatus. A first programmable logic device may be configured to have (i) a first signal interface and (ii) a second signal interface. A second programmable logic device may be configured to have (i) a third signal interface and (ii) a fourth signal interface. The assembly apparatus is generally configured to (i) mount the first programmable logic device and (ii) mount the second programmable logic device. A first external contact may be connected to the first signal interface. A second external contact may be connected to the fourth signal interface. A direct connection may be provided between the second signal interface and the third signal interface.
摘要翻译：一种在组装装置内具有两个或多个可编程逻辑装置的装置。第一可编程逻辑器件可以被配置为具有（i）第一信号接口和（ii）第二信号接口。第二可编程逻辑器件可以被配置为具有（i）第三信号接口和（ii）第四信号接口。组装装置通常被配置为（i）安装第一可编程逻辑器件和（ii）安装第二可编程逻辑器件。第一外部接点可以连接到第一信号接口。第二外部接点可以连接到第四信号接口。可以在第二信号接口和第三信号接口之间提供直接连接。

7. 发明授权

US06521821B2 Fixing member, a solar cell module array using said fixing member, and a method for installing a solar cell module or a roofing member using said fixing member 失效
标题翻译：固定构件，使用所述固定构件的太阳能电池模块阵列，以及使用所述固定构件安装太阳能电池模块或屋顶构件的方法
公开(公告)号：US06521821B2
公开(公告)日：2003-02-18
申请号：US09221145
申请日：1998-12-28
申请人： Hidehisa Makita , Kimitoshi Fukae , Tatsuo Fujisaki
发明人： Hidehisa Makita , Kimitoshi Fukae , Tatsuo Fujisaki
IPC分类号： H01L2500
CPC分类号： H02S20/23 , F24S20/67 , F24S25/33 , F24S2020/13 , H01L31/048 , Y02B10/12 , Y02B10/20 , Y02E10/47 , Y02E10/50 , Y10S136/291
摘要： A fixing member for fixing a solar cell module or a roofing member with no solar cell onto an installation face, said fixing member comprising a meshing portion to mesh at least a solar cell module or a part of a roofing member with no solar cell; a fixing portion to fix said fixing member to said installation face; and a raised portion to connect said meshing portion and said fixing portion, wherein said raised portion has a height which is greater than the thickness of a portion of said solar cell module or said roofing member which is engaged in the meshing by said meshing portion.
摘要翻译：一种用于将太阳能电池模块或没有太阳能电池的屋顶构件固定到安装面上的固定构件，所述固定构件包括至少将太阳能电池模块或屋顶构件的一部分没有太阳能电池的网状部分啮合; 固定部，其将所述固定部件固定在所述安装面上; 以及用于连接所述啮合部分和所述固定部分的凸起部分，其中所述凸起部分的高度大于所述太阳能电池模块或所述屋顶部件的与所述啮合部分啮合的部分的厚度。

8. 发明授权

US06504424B1 Low voltage metal oxide semiconductor threshold referenced voltage regulator and method of using 失效
标题翻译：低电压金属氧化物半导体阈值参考电压调节器及其使用方法
公开(公告)号：US06504424B1
公开(公告)日：2003-01-07
申请号：US09942053
申请日：2001-08-29
申请人： David M. Heminger , Stephen P. Robb , Margaret E. Fuchs
发明人： David M. Heminger , Stephen P. Robb , Margaret E. Fuchs
IPC分类号： H01L2500
CPC分类号： G05F1/56 , H01L2924/0002 , H01L2924/00
摘要： Depletion mode pass transistor (38) accepts input voltage Vin and provides regulated output voltage Vout. The regulated output voltage is referenced to the threshold voltage of MOSFET (40) and is directly proportional to the ratio of resistors (50 and 52). MOSFET (58) provides enabling and disabling of voltage regulator (54). Multiple voltage regulators (FIG. 5) having multiple output potentials are realized on the same semiconductor die producing the same threshold potential for MOSFET's (40), whereby the output potentials are selectable using the ratio of resistors 50 and 52. Constant current source (56) reduces output voltage variation due to input voltage variation.
摘要翻译：耗尽模式传递晶体管（38）接受输入电压Vin并提供调节的输出电压Vout。调节输出电压参考MOSFET（40）的阈值电压，并与电阻（50和52）的比例成正比。 MOSFET（58）提供电压调节器（54）的使能和禁用。在相同的半导体管芯上实现具有多个输出电位的多个电压调节器（图5），为MOSFET（40）产生相同的阈值电位，从而可以使用电阻50和52的比例来选择输出电位。恒流源）降低了输入电压变化引起的输出电压变化。

9. 发明授权

US06501301B2 Semiconductor integrated circuit and an electronic apparatus incorporating a multiplicity of semiconductor integrated circuits 失效
标题翻译：半导体集成电路和并入有多个半导体集成电路的电子设备
公开(公告)号：US06501301B2
公开(公告)日：2002-12-31
申请号：US09945064
申请日：2001-08-30
申请人： Masahiko Taguchi
发明人： Masahiko Taguchi
IPC分类号： H01L2500
CPC分类号： H05K1/0262 , H01L2924/0002 , H03K19/0175 , H05K1/181 , H05K2201/10689 , H01L2924/00
摘要： An electronic apparatus having a multiplicity of operably connected semiconductor integrated circuits (ICs) arranged on a substrate and operable at different operating voltages. The interface voltages between two ICs is set to the lowest operating voltage of the ICs. Each IC other than those operating at the lowest operating voltage has an input circuit for converting the lowest operating voltage of an input signal to its operating voltage and an output circuit for converting the voltage of its output signal to the lowest operating voltage.
摘要翻译：一种具有多个可操作地连接的半导体集成电路（IC）的电子设备，其布置在基板上并且可在不同的工作电压下操作。两个IC之间的接口电压设置为IC的最低工作电压。除了在最低工作电压下工作的IC以外的每个IC都具有用于将输入信号的最低工作电压转换为其工作电压的输入电路和用于将其输出信号的电压转换为最低工作电压的输出电路。

10. 发明授权

US06496058B1 Method for designing an integrated circuit containing multiple integrated circuit designs and an integrated circuit so designed 失效
标题翻译：用于设计包含多个集成电路设计的集成电路的方法和如此设计的集成电路
公开(公告)号：US06496058B1
公开(公告)日：2002-12-17
申请号：US09912588
申请日：2001-07-24
申请人： Joseph Hong
发明人： Joseph Hong
IPC分类号： H01L2500
CPC分类号： G06F17/5045
摘要： A multi-design integrated circuit having I/O buffers that are shared by multiple designs in the integrated circuit, the multi-design integrated circuit being designed by combining netlists and pin-pad assignment lists for the individual designs into one overall netlist or multi-design netlist.
摘要翻译：具有由集成电路中的多个设计共享的I / O缓冲器的多设计集成电路，多设计集成电路通过将各个设计的网表和引脚分配列表组合成一个整体网表或多个集成电路而设计，设计网表。

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