专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06977128B2 Multi-layered semiconductor structure 失效
标题翻译：多层半导体结构
公开(公告)号：US06977128B2
公开(公告)日：2005-12-20
申请号：US10704449
申请日：2003-11-07
申请人： David M. Boulin , Reginald C. Farrow , Isik C. Kizilyalli , Nace Layadi , Masis Mkrtchyan
发明人： David M. Boulin , Reginald C. Farrow , Isik C. Kizilyalli , Nace Layadi , Masis Mkrtchyan
IPC分类号： G03F7/20 , G03F9/00 , H01J37/304 , H01J37/305 , H01L21/027 , H01L23/544 , G03C5/00
CPC分类号： H01J37/3045 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S430/143 , Y10S438/975 , H01L2924/00
摘要： A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.
摘要翻译：一种多层半导体结构，其具有用于对准光刻掩模并且可以与SCALPEL工具结合使用的对准特征。本发明特别适用于亚微米CMOS工艺器件和电路，但不限于此。本发明有利地允许使用电子束源用于半导体晶片上的光刻掩模的对准和曝光。本发明还有利地使得能够在半导体器件制造工艺中早期（即零电平）形成对准特征。

2. 发明申请

US20050134857A1 Method to monitor silicide formation on product wafers 审中-公开
标题翻译：监测产品晶圆上硅化物形成的方法
公开(公告)号：US20050134857A1
公开(公告)日：2005-06-23
申请号：US10742986
申请日：2003-12-22
申请人： Alvaro Maury , Nace Layadi , Jovin Lim
发明人： Alvaro Maury , Nace Layadi , Jovin Lim
IPC分类号： G01N21/17 , G01R31/28 , H01L21/66 , G01N21/00 , G01R31/26
CPC分类号： G01R31/2831 , G01N21/1717
摘要： A new method to monitor sheet resistance of a metal silicide layer in the manufacture of an integrated circuit device is achieved. The method comprises providing a metal silicide layer overlying an exposed silicon layer on a substrate. A thermal wave intensity signal is generated for the metal silicide layer by an optical measurement system. The optical measurement system comprises a first laser beam that is intensity modulated and a second laser beam. The first and second laser beams comprise different wavelengths. A dichroic mirror is used to combine the first and second laser beams and to project the first and second laser beams onto the metal silicide layer. A detector is used to gather the second laser beam reflected from the metal silicide layer and to generate a thermal wave intensity signal based on the reflected second laser beam. Sheet resistance of the metal silicide layer is calculated by a linear equation based on the thermal wave intensity signal.
摘要翻译：实现了在制造集成电路器件时监测金属硅化物层的薄层电阻的新方法。该方法包括提供覆盖衬底上暴露的硅层的金属硅化物层。通过光学测量系统为金属硅化物层产生热波强度信号。光学测量系统包括强度调制的第一激光束和第二激光束。第一和第二激光束包括不同的波长。分色镜用于组合第一和第二激光束并将第一和第二激光束投影到金属硅化物层上。检测器用于收集从金属硅化物层反射的第二激光束，并产生基于反射的第二激光束的热波强度信号。通过基于热波强度信号的线性方程来计算金属硅化物层的薄层电阻。

3. 发明授权

US06727588B1 Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics 有权
标题翻译：集成电路金属间介质中的防扩散阻挡层
公开(公告)号：US06727588B1
公开(公告)日：2004-04-27
申请号：US09377386
申请日：1999-08-19
申请人： Mahjoub Ali Abdelgadir , Nace Layadi , Sailesh Mansinh Merchant , Vivek Saxena , Pei H. Yih
发明人： Mahjoub Ali Abdelgadir , Nace Layadi , Sailesh Mansinh Merchant , Vivek Saxena , Pei H. Yih
IPC分类号： H01L2348
CPC分类号： H01L23/5329 , H01L21/76829 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A cap or barrier layer that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit by may be fabricated by disposing the diffusion-preventing barrier layer between a first dielectric layer and the conductive layer at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiOx, where x is preferably less than 2.
摘要翻译：可以防止杂质在低介电常数材料中迁移的帽或阻挡层，从而防止杂质在多级集成电路结构的后续级别中侵袭导电元件。集成电路可以通过在集成电路的上层设置第一介电层和导电层之间设置防扩散阻挡层来制造。扩散防止阻挡层可以在含杂质的电介质材料上的原位形成，随后在其上布置金属层，并且进一步处理多层电介质结构以包括抛光。帽或阻挡层的原位沉积防止了含杂质层暴露于大气中，从而避免了由吸湿，吸氢等引起的层的污染。在示例性实施例中，防扩散阻挡层是含有氧化硅或富硅氧化硅SiO x的材料，其中x优选小于2。

4. 发明授权

US06548906B2 Method for reducing a metal seam in an interconnect structure and a device manufactured thereby 有权
标题翻译：用于减少互连结构中的金属接缝的方法和由此制造的器件
公开(公告)号：US06548906B2
公开(公告)日：2003-04-15
申请号：US09935241
申请日：2001-08-22
申请人： Nace Layadi , Alvaro Maury
发明人： Nace Layadi , Alvaro Maury
IPC分类号： H01L2348
CPC分类号： H01L21/76877 , H01L21/76847 , H01L23/485 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of manufacturing an interconnect structure. The method may include forming a nucleation layer, including a first metal, over a barrier layer and within an opening formed in a dielectric layer, forming an intermediate layer, including a second metal such as titanium nitride, over the nucleation layer and within the opening, and forming a plug portion layer, including the first metal, over the intermediate layer and within the opening. The first metal may be tungsten and the second metal may be a titanium nitride layer.
摘要翻译：本发明提供一种制造互连结构的方法。该方法可以包括在阻挡层上形成包含第一金属的成核层，并在形成于电介质层中的开口内形成包括第二金属如氮化钛在内的中间层，并在开口内并且在中间层之上和开口内形成包括第一金属的塞子部分层。第一金属可以是钨，第二金属可以是氮化钛层。

5. 发明授权

US07163438B2 Zone polishing using variable slurry solid content 有权
标题翻译：使用可变浆料固体含量进行区域抛光
公开(公告)号：US07163438B2
公开(公告)日：2007-01-16
申请号：US11208829
申请日：2005-08-22
申请人： Alvaro Maury , Jovin Lim , Nace Layadi , Sebastian Ouek
发明人： Alvaro Maury , Jovin Lim , Nace Layadi , Sebastian Ouek
IPC分类号： B24B49/00 , B24B7/00 , B24B1/00
CPC分类号： B24B37/04 , B24B57/02
摘要： A slurry dispensing apparatus for use with a chemical mechanical polishing tool for planarizing semiconductor substrates having irregular topology. The apparatus includes a slurry dispensing manifold with a first end suspended over a polishing pad, and a second end for mounting to the chemical mechanical polishing tool. The slurry dispensing manifold has a linear array of nozzles positioned under the suspended manifold. Each nozzle provides an adjusted slurry mixture that is supplied from bifurcated supply lines. A first branch supplying a slurry, and a second branch supplying deionized water. Each nozzle is capable of providing a particular slurry concentration to either decrease or to increase polishing rate in specific zonal areas on a substrate according to its surface topology.
摘要翻译：一种用于与化学机械抛光工具一起用于平坦化具有不规则拓扑的半导体衬底的浆料分配装置。该设备包括具有悬挂在抛光垫上的第一端的浆料分配歧管和用于安装到化学机械抛光工具的第二端。浆料分配歧管具有位于悬浮歧管下方的线性阵列的喷嘴。每个喷嘴提供从分叉供应管线供应的经调节的浆料混合物。供应浆料的第一分支和供应去离子水的第二分支。根据其表面拓扑结构，每个喷嘴能够提供特定的浆料浓度以降低或提高基材上特定区带区域的抛光速率。

6. 发明授权

US06910907B2 Contact for use in an integrated circuit and a method of manufacture therefor 失效
标题翻译：用于集成电路的接触及其制造方法
公开(公告)号：US06910907B2
公开(公告)日：2005-06-28
申请号：US10716299
申请日：2003-11-18
申请人： Nace Layadi , Alvaro Maury
发明人： Nace Layadi , Alvaro Maury
IPC分类号： H01L21/768 , H01R13/28 , H01R25/00
CPC分类号： H01L21/76877
摘要： The present invention provides a contact for use in an integrated circuit, a method of manufacture therefor, and an integrated circuit including the aforementioned contact. The contact, in accordance with the principles of the present invention, may include a via located in a substrate, and a contact plug located in the via, wherein the contact plug has a first portion having a notch removed therefrom and a second portion filling the notch.
摘要翻译：本发明提供了一种用于集成电路的接点及其制造方法，以及包括上述接触的集成电路。根据本发明的原理的触点可以包括位于基板中的通孔和位于通孔中的接触塞，其中接触插塞具有从其中移除的凹口的第一部分和填充该通孔的第二部分缺口。

7. 发明授权

US06656850B2 Method for in-situ removal of side walls in MOM capacitor formation 有权
公开(公告)号：US06656850B2
公开(公告)日：2003-12-02
申请号：US10215170
申请日：2002-08-08
申请人： Simon J. Molloy , Nace Layadi , Edward Belden Harris , Sidhartha Sen
发明人： Simon J. Molloy , Nace Layadi , Edward Belden Harris , Sidhartha Sen
IPC分类号： H01L21362
CPC分类号： H01L28/40 , H01L21/31116 , H01L21/32136
摘要： A method for fabricating an MOM capacitor (10) includes forming a first conductive layer (18) on an insulating support (12, 14), depositing a dielectric film (20) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers (22, 24, 26). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material (38) around the capacitor feature. Sidewalls (40), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF6 plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

8. 发明授权

US06395639B1 Process for improving line width variations between tightly spaced and isolated features in integrated circuits 有权
标题翻译：用于改善集成电路中紧密间隔和隔离特征之间的线宽变化的过程
公开(公告)号：US06395639B1
公开(公告)日：2002-05-28
申请号：US09397458
申请日：1999-09-16
申请人： Thomas Craig Esry , Nace Layadi , Sylvia Marci Luque , Simon John Molloy , Mario Pita
发明人： Thomas Craig Esry , Nace Layadi , Sylvia Marci Luque , Simon John Molloy , Mario Pita
IPC分类号： H01L213065
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/32139
摘要： A process for forming a patterned film structure within a semiconductor device. The process sequentially forms a pattern within a hardmask film and than within a semiconductor or other film formed beneath the hardmask film. The etch bias of both isolated and nested features formed within the films, is substantially the same with respect to a masking film formed over the hardmask film. The process includes a hardmask film etching sequence including an argon treatment step and a hardmask film etching step which is resistant to localized etching effects and includes O2 and C2F6 as etchant gasses.
摘要翻译：一种用于在半导体器件内形成图案化膜结构的工艺。该过程在硬掩模膜内依次形成图案，而不是形成在硬掩膜下方的半导体或其它膜内。在膜内形成的隔离和嵌套特征的蚀刻偏压对于在硬掩模膜上形成的掩模膜基本相同。该方法包括硬掩模膜蚀刻序列，其包括氩处理步骤和耐局部蚀刻效应的硬掩模膜蚀刻步骤，并且包括作为蚀刻剂气体的O 2和C 2 F 6。

9. 发明授权

US06218255B1 Method of making a capacitor 有权
标题翻译：制作电容器的方法
公开(公告)号：US06218255B1
公开(公告)日：2001-04-17
申请号：US09277778
申请日：1999-03-29
申请人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Larry Bruce Fritzinger , Nace Layadi , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L2120
CPC分类号： H01L28/60 , H01L21/3212 , H01L21/32136 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/90
摘要： The present invention provides a method for fabricating a capacitor, comprising the steps of forming a trench in a substrate, forming a layer of a first material selected from the group consisting of titanium and titanium nitride in the trench, filling the trench with a conductive material to form a conductive plug, planarizing the substrate, patterning the substrate to partially expose the first material and to create a top portion and a bottom portion to the plug, wherein the bottom portion is in the substrate, and removing the first material from the top portion of the plug.
摘要翻译：本发明提供一种制造电容器的方法，包括以下步骤：在衬底中形成沟槽，在沟槽中形成从由钛和氮化钛组成的组中选择的第一材料的层，用导电材料填充沟槽以形成导电插塞，平坦化基板，图案化基板以部分地暴露第一材料并且产生到插头的顶部部分和底部部分，其中底部部分在基板中，并且从顶部移除第一材料插头的一部分。

10. 发明授权

US06180518B2 Method for forming vias in a low dielectric constant material 有权
标题翻译：在低介电常数材料中形成通孔的方法
公开(公告)号：US06180518B2
公开(公告)日：2001-01-30
申请号：US09430226
申请日：1999-10-29
申请人： Nace Layadi , Sailesh Mansinh Merchant , Simon John Molloy , Pradip Kumar Roy
发明人： Nace Layadi , Sailesh Mansinh Merchant , Simon John Molloy , Pradip Kumar Roy
IPC分类号： H01L214763
CPC分类号： H01L21/02063 , H01L21/31138 , H01L21/76802 , H01L21/76814 , H01L21/76831
摘要： A method for making a semiconductor device includes the steps of forming a first conductive layer adjacent a substrate, forming an etch stop layer on the conductive layer, and forming a dielectric layer on the etch stop layer. The dielectric layer includes a material having a low dielectric constant, and a via is formed through the dielectric layer to expose the etch stop layer at the bottom, with porous sidewalls being produced. The exposed etch stop layer is etched using an etchant that cooperates with etched material from the etch stop layer to form a polymeric layer to coat the porous sidewalls of the via. Since the etchant cooperates with the etched material from the etch stop layer to form the polymeric layer coating the porous sidewalls of the via, a separate coating layer deposition step is not required after the via is etched and cleaned. After the porous sidewalls have been coated and polymeric material has been etched from the bottom of the via, a barrier metal layer is formed on the polymeric layer, a seed layer is formed on the barrier metal layer, and a second conductive layer is formed on the seed layer contacting the first conductive layer in the via.
摘要翻译：制造半导体器件的方法包括以下步骤：在衬底附近形成第一导电层，在导电层上形成蚀刻停止层，并在蚀刻停止层上形成介电层。电介质层包括具有低介电常数的材料，并且通过介电层形成通孔以暴露底部的蚀刻停止层，产生多孔侧壁。使用与蚀刻停止层的蚀刻材料配合的蚀刻剂来蚀刻暴露的蚀刻停止层，以形成聚合物层以涂覆通孔的多孔侧壁。由于蚀刻剂与来自蚀刻停止层的蚀刻材料配合以形成涂覆通孔的多孔侧壁的聚合物层，在蚀刻和清洁通孔之后不需要单独的涂层沉积步骤。在已经涂覆多孔侧壁并且已经从通孔的底部蚀刻聚合物材料之后，在聚合物层上形成阻挡金属层，在阻挡金属层上形成种子层，并且在第二导电层上形成第二导电层种子层与通孔中的第一导电层接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式