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1. 发明授权

US06458648B1 Method for in-situ removal of side walls in MOM capacitor formation 有权
公开(公告)号：US06458648B1
公开(公告)日：2002-10-01
申请号：US09466715
申请日：1999-12-17
申请人： Simon J. Molloy , Nace Layadi , Edward Belden Harris , Sidhartha Sen
发明人： Simon J. Molloy , Nace Layadi , Edward Belden Harris , Sidhartha Sen
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L21/31116 , H01L21/32136
摘要： A method for fabricating an MOM capacitor (10) includes forming a first conductive layer (18) on an insulating support (12, 14), depositing a dielectric film (20) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers (22, 24, 26). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material (38) around the capacitor feature. Sidewalls (40), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF6 plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

2. 发明授权

US06656850B2 Method for in-situ removal of side walls in MOM capacitor formation 有权
公开(公告)号：US06656850B2
公开(公告)日：2003-12-02
申请号：US10215170
申请日：2002-08-08
申请人： Simon J. Molloy , Nace Layadi , Edward Belden Harris , Sidhartha Sen
发明人： Simon J. Molloy , Nace Layadi , Edward Belden Harris , Sidhartha Sen
IPC分类号： H01L21362
CPC分类号： H01L28/40 , H01L21/31116 , H01L21/32136
摘要： A method for fabricating an MOM capacitor (10) includes forming a first conductive layer (18) on an insulating support (12, 14), depositing a dielectric film (20) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers (22, 24, 26). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material (38) around the capacitor feature. Sidewalls (40), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF6 plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

3. 发明授权

US06218085B1 Process for photoresist rework to avoid sodium incorporation 失效
标题翻译：光刻胶返修工艺，避免钠掺入
公开(公告)号：US06218085B1
公开(公告)日：2001-04-17
申请号：US09400406
申请日：1999-09-21
申请人： Simon J. Molloy , Nace Layadi , Allen Yen , Brian D. Crevasse , Steven A. Lytle
发明人： Simon J. Molloy , Nace Layadi , Allen Yen , Brian D. Crevasse , Steven A. Lytle
IPC分类号： G03F736
CPC分类号： G03F7/427
摘要： A method for stripping photoresist material (26) from a semiconductor substrate (16) avoids incorporation of sodium and other contaminant ions from a rework solvent. An oxygen and hydrogen plasma mixture strips the photoresist material without significant introduction of oxygen into the titanium nitride layer (24). Any oxidation of the titanium nitride is reversed by exposing the substrate to an oxygen-free, reducing plasma, such as a hydrogen-containing plasma. The titanium nitride layer is thereby much less susceptible to incorporation of contaminant ions in a subsequent cleaning with rework solvent than a layer which has been extensively oxidized during the plasma stripping process.
摘要翻译：用于从半导体衬底（16）剥离光致抗蚀剂材料（26）的方法避免了从返工溶剂中引入钠和其它污染物离子。氧和氢等离子体混合物剥离光致抗蚀剂材料，而不会在氧化钛层（24）内显着引入氧气。通过将衬底暴露于无氧还原等离子体（例如含氢等离子体）中，氮化钛的任何氧化反转。因此，氮化钛层比在等离子体剥离过程中已经被广泛氧化的层更难于掺杂污染物离子以进行随后的返工溶剂清洗。

4. 发明授权

US06472307B1 Methods for improved encapsulation of thick metal features in integrated circuit fabrication 有权
标题翻译：在集成电路制造中改进厚金属特征封装的方法
公开(公告)号：US06472307B1
公开(公告)日：2002-10-29
申请号：US09491644
申请日：2000-01-27
申请人： Donald C. Dennis , Nace Layadi , Simon J. Molloy , Kurt G. Steiner , Sylvia W. Thomas
发明人： Donald C. Dennis , Nace Layadi , Simon J. Molloy , Kurt G. Steiner , Sylvia W. Thomas
IPC分类号： H01L21316
CPC分类号： H01L21/76837 , H01L21/31116 , H01L21/31608 , H01L21/76832 , H01L21/76834 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of manufacturing an integrated circuit having a capping layer over a thick metal feature. In one embodiment, the method comprises forming first and second oxide layers over the thick metal feature, forming a composite oxide layer including an oxide spacer by etching the first and second oxide layers, and forming a capping layer over the composite oxide layer. More specifically, forming the first oxide layer involves using a high density plasma (HDP) process, forming the second oxide layer involves using a plasma enhanced chemical vapor deposition (PECVD) process, and forming the composite oxide layer preferably involves etching with a reactive ion etch.
摘要翻译：本发明提供一种制造在厚金属特征上具有覆盖层的集成电路的方法。在一个实施例中，该方法包括在厚金属特征上形成第一和第二氧化物层，通过蚀刻第一和第二氧化物层形成包含氧化物间隔物的复合氧化物层，并在复合氧化物层上形成覆盖层。更具体地，形成第一氧化物层涉及使用高密度等离子体（HDP）工艺，形成第二氧化物层涉及使用等离子体增强化学气相沉积（PECVD）工艺，并且形成复合氧化物层优选包括用反应离子蚀刻。

5. 发明授权

US06258610B1 Method analyzing a semiconductor surface using line width metrology with auto-correlation operation 有权
标题翻译：使用自相关运算的线宽度量法分析半导体表面的方法
公开(公告)号：US06258610B1
公开(公告)日：2001-07-10
申请号：US09347313
申请日：1999-07-02
申请人： James W. Blatchford , Scott Jessen , Brittin C. Kane , Nace Layadi , John M. McIntosh , Simon J. Molloy
发明人： James W. Blatchford , Scott Jessen , Brittin C. Kane , Nace Layadi , John M. McIntosh , Simon J. Molloy
IPC分类号： G01R3126
CPC分类号： H01L22/12
摘要： A method for analyzing a semiconductor surface having patterned features on the surface is disclosed. At least one patterned feature is scanned to produce a scanned waveform signal having signal segments corresponding to characteristic surface portions of the patterned feature. The signal segments are processed using an auto-correlation function to produce an auto-correlation signal for each characteristic surface portion of the patterned feature. A reference signal having signal segments corresponding to characteristic surface portions of a known patterned feature is provided and each segment of the auto-correlation signal is compared to the respective signal segments of the reference signal.
摘要翻译：公开了一种用于分析表面上具有图案特征的半导体表面的方法。扫描至少一个图案特征以产生具有对应于图案化特征的特征表面部分的信号段的扫描波形信号。使用自相关函数处理信号段，以对图案化特征的每个特征表面部分产生自相关信号。提供具有对应于已知图案特征的特征表面部分的信号段的参考信号，并将自相关信号的每个段与参考信号的相应信号段进行比较。

6. 发明授权

US06977128B2 Multi-layered semiconductor structure 失效
标题翻译：多层半导体结构
公开(公告)号：US06977128B2
公开(公告)日：2005-12-20
申请号：US10704449
申请日：2003-11-07
申请人： David M. Boulin , Reginald C. Farrow , Isik C. Kizilyalli , Nace Layadi , Masis Mkrtchyan
发明人： David M. Boulin , Reginald C. Farrow , Isik C. Kizilyalli , Nace Layadi , Masis Mkrtchyan
IPC分类号： G03F7/20 , G03F9/00 , H01J37/304 , H01J37/305 , H01L21/027 , H01L23/544 , G03C5/00
CPC分类号： H01J37/3045 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S430/143 , Y10S438/975 , H01L2924/00
摘要： A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.
摘要翻译：一种多层半导体结构，其具有用于对准光刻掩模并且可以与SCALPEL工具结合使用的对准特征。本发明特别适用于亚微米CMOS工艺器件和电路，但不限于此。本发明有利地允许使用电子束源用于半导体晶片上的光刻掩模的对准和曝光。本发明还有利地使得能够在半导体器件制造工艺中早期（即零电平）形成对准特征。

7. 发明申请

US20050134857A1 Method to monitor silicide formation on product wafers 审中-公开
标题翻译：监测产品晶圆上硅化物形成的方法
公开(公告)号：US20050134857A1
公开(公告)日：2005-06-23
申请号：US10742986
申请日：2003-12-22
申请人： Alvaro Maury , Nace Layadi , Jovin Lim
发明人： Alvaro Maury , Nace Layadi , Jovin Lim
IPC分类号： G01N21/17 , G01R31/28 , H01L21/66 , G01N21/00 , G01R31/26
CPC分类号： G01R31/2831 , G01N21/1717
摘要： A new method to monitor sheet resistance of a metal silicide layer in the manufacture of an integrated circuit device is achieved. The method comprises providing a metal silicide layer overlying an exposed silicon layer on a substrate. A thermal wave intensity signal is generated for the metal silicide layer by an optical measurement system. The optical measurement system comprises a first laser beam that is intensity modulated and a second laser beam. The first and second laser beams comprise different wavelengths. A dichroic mirror is used to combine the first and second laser beams and to project the first and second laser beams onto the metal silicide layer. A detector is used to gather the second laser beam reflected from the metal silicide layer and to generate a thermal wave intensity signal based on the reflected second laser beam. Sheet resistance of the metal silicide layer is calculated by a linear equation based on the thermal wave intensity signal.
摘要翻译：实现了在制造集成电路器件时监测金属硅化物层的薄层电阻的新方法。该方法包括提供覆盖衬底上暴露的硅层的金属硅化物层。通过光学测量系统为金属硅化物层产生热波强度信号。光学测量系统包括强度调制的第一激光束和第二激光束。第一和第二激光束包括不同的波长。分色镜用于组合第一和第二激光束并将第一和第二激光束投影到金属硅化物层上。检测器用于收集从金属硅化物层反射的第二激光束，并产生基于反射的第二激光束的热波强度信号。通过基于热波强度信号的线性方程来计算金属硅化物层的薄层电阻。

8. 发明授权

US06727588B1 Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics 有权
标题翻译：集成电路金属间介质中的防扩散阻挡层
公开(公告)号：US06727588B1
公开(公告)日：2004-04-27
申请号：US09377386
申请日：1999-08-19
申请人： Mahjoub Ali Abdelgadir , Nace Layadi , Sailesh Mansinh Merchant , Vivek Saxena , Pei H. Yih
发明人： Mahjoub Ali Abdelgadir , Nace Layadi , Sailesh Mansinh Merchant , Vivek Saxena , Pei H. Yih
IPC分类号： H01L2348
CPC分类号： H01L23/5329 , H01L21/76829 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A cap or barrier layer that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit by may be fabricated by disposing the diffusion-preventing barrier layer between a first dielectric layer and the conductive layer at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiOx, where x is preferably less than 2.
摘要翻译：可以防止杂质在低介电常数材料中迁移的帽或阻挡层，从而防止杂质在多级集成电路结构的后续级别中侵袭导电元件。集成电路可以通过在集成电路的上层设置第一介电层和导电层之间设置防扩散阻挡层来制造。扩散防止阻挡层可以在含杂质的电介质材料上的原位形成，随后在其上布置金属层，并且进一步处理多层电介质结构以包括抛光。帽或阻挡层的原位沉积防止了含杂质层暴露于大气中，从而避免了由吸湿，吸氢等引起的层的污染。在示例性实施例中，防扩散阻挡层是含有氧化硅或富硅氧化硅SiO x的材料，其中x优选小于2。

9. 发明授权

US06548906B2 Method for reducing a metal seam in an interconnect structure and a device manufactured thereby 有权
标题翻译：用于减少互连结构中的金属接缝的方法和由此制造的器件
公开(公告)号：US06548906B2
公开(公告)日：2003-04-15
申请号：US09935241
申请日：2001-08-22
申请人： Nace Layadi , Alvaro Maury
发明人： Nace Layadi , Alvaro Maury
IPC分类号： H01L2348
CPC分类号： H01L21/76877 , H01L21/76847 , H01L23/485 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of manufacturing an interconnect structure. The method may include forming a nucleation layer, including a first metal, over a barrier layer and within an opening formed in a dielectric layer, forming an intermediate layer, including a second metal such as titanium nitride, over the nucleation layer and within the opening, and forming a plug portion layer, including the first metal, over the intermediate layer and within the opening. The first metal may be tungsten and the second metal may be a titanium nitride layer.
摘要翻译：本发明提供一种制造互连结构的方法。该方法可以包括在阻挡层上形成包含第一金属的成核层，并在形成于电介质层中的开口内形成包括第二金属如氮化钛在内的中间层，并在开口内并且在中间层之上和开口内形成包括第一金属的塞子部分层。第一金属可以是钨，第二金属可以是氮化钛层。

10. 发明授权

US06984166B2 Zone polishing using variable slurry solid content 失效
标题翻译：使用可变浆料固体含量进行区域抛光
公开(公告)号：US06984166B2
公开(公告)日：2006-01-10
申请号：US10633131
申请日：2003-08-01
申请人： Alvaro Maury , Jovin Lim , Nace Layadi , Sebastian Quek
发明人： Alvaro Maury , Jovin Lim , Nace Layadi , Sebastian Quek
IPC分类号： B24B1/00
CPC分类号： B24B37/04 , B24B57/02
摘要： A slurry dispensing apparatus for use with a chemical mechanical polishing tool for planarizing semiconductor substrates having irregular topology. The apparatus includes a slurry dispensing manifold with a first end suspended over a polishing pad, and a second end for mounting to the chemical mechanical polishing tool. The slurry dispensing manifold has a linear array of nozzles positioned under the suspended manifold. Each nozzle provides an adjusted slurry mixture that is supplied from bifurcated supply lines. A first branch supplying a slurry, and a second branch supplying deionized water. Each nozzle is capable of providing a particular slurry concentration to either decrease or to increase polishing rate in specific zonal areas on a substrate according to its surface topology.
摘要翻译：一种用于与化学机械抛光工具一起用于平坦化具有不规则拓扑的半导体衬底的浆料分配装置。该设备包括具有悬挂在抛光垫上的第一端的浆料分配歧管和用于安装到化学机械抛光工具的第二端。浆料分配歧管具有位于悬浮歧管下方的线性阵列的喷嘴。每个喷嘴提供从分叉供应管线供应的经调节的浆料混合物。供应浆料的第一分支和供应去离子水的第二分支。根据其表面拓扑结构，每个喷嘴能够提供特定的浆料浓度以降低或提高基材上特定区域区域中的抛光速率。

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