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1. 发明授权

US06395639B1 Process for improving line width variations between tightly spaced and isolated features in integrated circuits 有权
标题翻译：用于改善集成电路中紧密间隔和隔离特征之间的线宽变化的过程
公开(公告)号：US06395639B1
公开(公告)日：2002-05-28
申请号：US09397458
申请日：1999-09-16
申请人： Thomas Craig Esry , Nace Layadi , Sylvia Marci Luque , Simon John Molloy , Mario Pita
发明人： Thomas Craig Esry , Nace Layadi , Sylvia Marci Luque , Simon John Molloy , Mario Pita
IPC分类号： H01L213065
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/32139
摘要： A process for forming a patterned film structure within a semiconductor device. The process sequentially forms a pattern within a hardmask film and than within a semiconductor or other film formed beneath the hardmask film. The etch bias of both isolated and nested features formed within the films, is substantially the same with respect to a masking film formed over the hardmask film. The process includes a hardmask film etching sequence including an argon treatment step and a hardmask film etching step which is resistant to localized etching effects and includes O2 and C2F6 as etchant gasses.
摘要翻译：一种用于在半导体器件内形成图案化膜结构的工艺。该过程在硬掩模膜内依次形成图案，而不是形成在硬掩膜下方的半导体或其它膜内。在膜内形成的隔离和嵌套特征的蚀刻偏压对于在硬掩模膜上形成的掩模膜基本相同。该方法包括硬掩模膜蚀刻序列，其包括氩处理步骤和耐局部蚀刻效应的硬掩模膜蚀刻步骤，并且包括作为蚀刻剂气体的O 2和C 2 F 6。

2. 发明授权

US06406999B1 Semiconductor device having reduced line width variations between tightly spaced and isolated features 有权
标题翻译：在紧密间隔和隔离的特征之间具有减小的线宽变化的半导体器件
公开(公告)号：US06406999B1
公开(公告)日：2002-06-18
申请号：US09397459
申请日：1999-09-16
申请人： Thomas Craig Esry , Nace Layadi , Sylvia Marci Luque , Simon John Molloy , Mario Pita
发明人： Thomas Craig Esry , Nace Layadi , Sylvia Marci Luque , Simon John Molloy , Mario Pita
IPC分类号： H01L2144
CPC分类号： H01L21/32139 , H01L21/31116
摘要： A patterned film structure within a semiconductor device includes a pattern formed within a hardmask film, and a pattern formed within an underlying semiconductor or metal film beneath the hardmask film. The etch bias of both isolated and nested features formed within the patterned structure, is substantially the same with respect to a masking film formed over the hardmask film.
摘要翻译：半导体器件内的图案化膜结构包括在硬掩模膜内形成的图案，以及形成在硬掩模膜下面的下面的半导体或金属膜内的图案。在图案化结构中形成的隔离和嵌套特征的蚀刻偏压对于在硬掩模膜上形成的掩模膜基本相同。

3. 发明授权

US06585830B2 Method for cleaning tungsten from deposition wall chambers 失效
公开(公告)号：US06585830B2
公开(公告)日：2003-07-01
申请号：US09727326
申请日：2000-11-30
申请人： Nace Layadi , Sailesh Mansinh Merchant , Simon John Molloy
发明人： Nace Layadi , Sailesh Mansinh Merchant , Simon John Molloy
IPC分类号： B08B500
CPC分类号： C23C16/4405
摘要： An unwanted tungsten film deposit on a Chemical Vapor Deposition chamber is cleaned by adding a mixture of at least two cleaning gases into the chamber at a predetermined temperature and pressure and in contact with said chamber walls for a sufficient length of time. The cleaning gases and reacted tungsten species are removed from the chamber by vacuum, and unreacted cleaning gases are removed by purging the chamber with an inert gas. At least one cleaning gas is selected from the group consisting of bromomethane, dibromomethane, bromoform and mixtures thereof. The temperature of the chamber is preferably at least about 300 degrees Celsius. The cleaning gases in the chamber are at a pressure in the range from about 100 to 200 Torr and the chamber is purged at a pressure in the range from about 200 to 500 Torr.

4. 发明授权

US06730600B2 Method of dry etching a semiconductor device in the absence of a plasma 有权
标题翻译：在不存在等离子体的情况下干法蚀刻半导体器件的方法
公开(公告)号：US06730600B2
公开(公告)日：2004-05-04
申请号：US10259256
申请日：2002-09-27
申请人： Nace Layadi , Simon John Molloy , Sailesh Mansinh Merchant , Isik C. Kizilyalli
发明人： Nace Layadi , Simon John Molloy , Sailesh Mansinh Merchant , Isik C. Kizilyalli
IPC分类号： H01L21465
CPC分类号： H01L21/32135 , C23F1/12
摘要： A method for dry etching a material deposited on semiconductor device is performed by chemically reacting the material with an etchant gas. The etching process is conducted in a reaction chamber at a predetermined temperature and predetermined pressure within the reaction chamber and without the need of generating a plasma within the chamber or applying an electrical bias to the semiconductor device. A sufficient amount of gas is introduced into the reaction chamber to selectively remove the material from the semiconductor device.
摘要翻译：通过使材料与蚀刻剂气体化学反应来进行用于干蚀刻沉积在半导体器件上的材料的方法。蚀刻工艺在反应室内以预定温度和预定压力在反应室内进行，而不需要在室内产生等离子体或向半导体器件施加电偏压。将足够量的气体引入反应室以选择性地从半导体器件中去除材料。

5. 发明授权

US06180518B2 Method for forming vias in a low dielectric constant material 有权
标题翻译：在低介电常数材料中形成通孔的方法
公开(公告)号：US06180518B2
公开(公告)日：2001-01-30
申请号：US09430226
申请日：1999-10-29
申请人： Nace Layadi , Sailesh Mansinh Merchant , Simon John Molloy , Pradip Kumar Roy
发明人： Nace Layadi , Sailesh Mansinh Merchant , Simon John Molloy , Pradip Kumar Roy
IPC分类号： H01L214763
CPC分类号： H01L21/02063 , H01L21/31138 , H01L21/76802 , H01L21/76814 , H01L21/76831
摘要： A method for making a semiconductor device includes the steps of forming a first conductive layer adjacent a substrate, forming an etch stop layer on the conductive layer, and forming a dielectric layer on the etch stop layer. The dielectric layer includes a material having a low dielectric constant, and a via is formed through the dielectric layer to expose the etch stop layer at the bottom, with porous sidewalls being produced. The exposed etch stop layer is etched using an etchant that cooperates with etched material from the etch stop layer to form a polymeric layer to coat the porous sidewalls of the via. Since the etchant cooperates with the etched material from the etch stop layer to form the polymeric layer coating the porous sidewalls of the via, a separate coating layer deposition step is not required after the via is etched and cleaned. After the porous sidewalls have been coated and polymeric material has been etched from the bottom of the via, a barrier metal layer is formed on the polymeric layer, a seed layer is formed on the barrier metal layer, and a second conductive layer is formed on the seed layer contacting the first conductive layer in the via.
摘要翻译：制造半导体器件的方法包括以下步骤：在衬底附近形成第一导电层，在导电层上形成蚀刻停止层，并在蚀刻停止层上形成介电层。电介质层包括具有低介电常数的材料，并且通过介电层形成通孔以暴露底部的蚀刻停止层，产生多孔侧壁。使用与蚀刻停止层的蚀刻材料配合的蚀刻剂来蚀刻暴露的蚀刻停止层，以形成聚合物层以涂覆通孔的多孔侧壁。由于蚀刻剂与来自蚀刻停止层的蚀刻材料配合以形成涂覆通孔的多孔侧壁的聚合物层，在蚀刻和清洁通孔之后不需要单独的涂层沉积步骤。在已经涂覆多孔侧壁并且已经从通孔的底部蚀刻聚合物材料之后，在聚合物层上形成阻挡金属层，在阻挡金属层上形成种子层，并且在第二导电层上形成第二导电层种子层与通孔中的第一导电层接触。

6. 发明授权

US07329605B2 Semiconductor structure formed using a sacrificial structure 有权
标题翻译：使用牺牲结构形成的半导体结构
公开(公告)号：US07329605B2
公开(公告)日：2008-02-12
申请号：US11094975
申请日：2005-03-31
申请人： Bailey R. Jones , Sean Lian , Simon John Molloy
发明人： Bailey R. Jones , Sean Lian , Simon John Molloy
IPC分类号： H01L23/528
CPC分类号： H01L29/66681 , H01L21/76816 , H01L21/76838 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/42368 , H01L29/7816
摘要： A method of forming a buried conductive structure in a semiconductor device includes the steps of forming a first insulating layer on a semiconductor layer; forming a sacrificial structure on at least a portion of the first insulating layer; forming a second insulating layer on at least a portion of the sacrificial structure; forming at least one opening through the second insulating layer to at least partially expose the sacrificial structure; substantially removing the sacrificial structure, leaving a cavity; and substantially filling the cavity and the at least one opening with a conductive material. The sacrificial structure may be substantially removed by etching the sacrificial structure using an isotropic etchant.
摘要翻译：在半导体器件中形成掩埋导电结构的方法包括以下步骤：在半导体层上形成第一绝缘层; 在所述第一绝缘层的至少一部分上形成牺牲结构; 在所述牺牲结构的至少一部分上形成第二绝缘层; 通过所述第二绝缘层形成至少一个开口以至少部分地暴露所述牺牲结构; 基本上去除牺牲结构，留下空腔; 并且用导电材料基本上填充空腔和至少一个开口。可以通过使用各向同性蚀刻剂蚀刻牺牲结构来基本上去除牺牲结构。

7. 发明授权

US06384446B2 Grooved capacitor structure for integrated circuits 失效
标题翻译：用于集成电路的沟槽电容器结构
公开(公告)号：US06384446B2
公开(公告)日：2002-05-07
申请号：US09024601
申请日：1998-02-17
申请人： Kuo-Hua Lee , Simon John Molloy , Daniel Joseph Vitkavage
发明人： Kuo-Hua Lee , Simon John Molloy , Daniel Joseph Vitkavage
IPC分类号： H01L2976
CPC分类号： H01L28/90 , H01L27/10855
摘要： An improved method of capacitor formation is disclosed. A dielectric is etched with an etch recipe which creates grooves within an opening. The opening is filled with metal which conforms to the grooves, thereby creating a capacitor's lower plate with increased surface area. The metal is later surrounded with dielectric and metal, which forms respectively the capacitor's dielectric and upper plate.
摘要翻译：公开了改进的电容器形成方法。用蚀刻配方蚀刻电介质，其在开口内产生凹槽。开口填充符合槽的金属，从而形成具有增加的表面积的电容器的下板。金属后来被电介质和金属包围，分别形成电容器的电介质和上板。

8. 发明授权

US08294210B2 High voltage channel diode 有权
标题翻译：高压通道二极管
公开(公告)号：US08294210B2
公开(公告)日：2012-10-23
申请号：US12815877
申请日：2010-06-15
申请人： Christopher Boguslaw Kocon , John Manning Savidge Neilson , Simon John Molloy , Haian Lin , Charles Walter Pearce , Gary Eugene Daum
发明人： Christopher Boguslaw Kocon , John Manning Savidge Neilson , Simon John Molloy , Haian Lin , Charles Walter Pearce , Gary Eugene Daum
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/861 , H01L29/402 , H01L29/6609 , H01L29/7835
摘要： A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming.
摘要翻译：具有漂移区域和形成方法的沟道二极管结构。具有电极屏蔽的电荷平衡沟道二极管结构和形成方法。

9. 发明授权

US6046115A Method for removing etching residues and contaminants 有权
标题翻译：去除蚀刻残留物和污染物的方法
公开(公告)号：US6046115A
公开(公告)日：2000-04-04
申请号：US164283
申请日：1998-10-01
申请人： Simon John Molloy , Daniel Joseph Vitkavage
发明人： Simon John Molloy , Daniel Joseph Vitkavage
IPC分类号： H01L21/302 , B08B7/00 , G03F7/42 , H01L21/304 , H01L21/311 , H01L21/3065
CPC分类号： H01L21/02063 , B08B7/0035 , G03F7/427 , H01L21/31138 , Y10S438/906
摘要： A gas plasma process without argon sputtering for removing photoresist, etch residues and other contaminants involved in etching vias in integrated circuit devices is disclosed. The process involves placing the substrate having etched vias or contact holes in a suitable low bias reactor; applying to the substrate surface a mixture of gases at low bias selected from the group consisting of oxygen, nitrogen, fluorine, hydrofluorocarbon and fluorinated methane and amine gases to both remove the photoresist layer and alter the composition of the residues such that the residues are soluble in water; and rinsing the substrate with deionized water. The plasma process should be carried out at temperatures of less than about 100 degrees C. to avoid mobile ion contamination problems and oxidation of the etch residues.
摘要翻译：公开了一种没有氩气溅射的气体等离子体工艺，用于去除在集成电路器件中蚀刻过孔中的光致抗蚀剂，蚀刻残余物和其它污染物该方法包括将具有蚀刻过孔或接触孔的基板放置在合适的低偏压反应器中; 以低偏压选择氧气，氮气，氟气，氢氟碳氟化合物和氟化甲烷和胺气体，向基板表面施加气体混合物，以去除光致抗蚀剂层并改变残留物的组成，使残留物溶解在水里; 并用去离子水冲洗底物。等离子体处理应在小于约100摄氏度的温度下进行，以避免移动离子污染问题和蚀刻残留物的氧化。

10. 发明授权

US08288820B2 High voltage power integrated circuit 有权
标题翻译：高压电源集成电路
公开(公告)号：US08288820B2
公开(公告)日：2012-10-16
申请号：US12815766
申请日：2010-06-15
申请人： Christopher Boguslaw Kocon , John Manning Savidge Neilson , Simon John Molloy , Haian Lin , Charles Walter Pearce
发明人： Christopher Boguslaw Kocon , John Manning Savidge Neilson , Simon John Molloy , Haian Lin , Charles Walter Pearce
IPC分类号： H01L29/66 , H01L21/336 , H01L25/00
CPC分类号： H01L29/7835 , H01L27/088 , H01L29/0847 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/66659 , H01L29/66681 , H01L29/7816
摘要： A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS transistor with an n-type substrate source. A charge balanced channel diode (CBCD) with an n-type substrate. A process for forming a high performance, power integrated circuit composed of two CBDENMOS transistors formed on an n-substrate. A process for forming a power integrated circuit composed of one CBDENMOS transistor and one CBCD on an n-type substrate.
摘要翻译：由n型衬底上形成的两个电荷平衡，扩展漏极NMOS晶体管（CBDEMOS）组成的高性能功率集成电路。具有n型衬底源的CBDENMOS晶体管。具有n型衬底的电荷平衡沟道二极管（CBCD）。一种用于形成由在n衬底上形成的两个CBDENMOS晶体管组成的高性能功率集成电路的工艺。一种在n型衬底上形成由一个CBDENMOS晶体管和一个CBCD组成的功率集成电路的工艺。

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