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1. 发明授权

US06458648B1 Method for in-situ removal of side walls in MOM capacitor formation 有权
公开(公告)号：US06458648B1
公开(公告)日：2002-10-01
申请号：US09466715
申请日：1999-12-17
申请人： Simon J. Molloy , Nace Layadi , Edward Belden Harris , Sidhartha Sen
发明人： Simon J. Molloy , Nace Layadi , Edward Belden Harris , Sidhartha Sen
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L21/31116 , H01L21/32136
摘要： A method for fabricating an MOM capacitor (10) includes forming a first conductive layer (18) on an insulating support (12, 14), depositing a dielectric film (20) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers (22, 24, 26). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material (38) around the capacitor feature. Sidewalls (40), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF6 plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

2. 发明授权

US06656850B2 Method for in-situ removal of side walls in MOM capacitor formation 有权
公开(公告)号：US06656850B2
公开(公告)日：2003-12-02
申请号：US10215170
申请日：2002-08-08
申请人： Simon J. Molloy , Nace Layadi , Edward Belden Harris , Sidhartha Sen
发明人： Simon J. Molloy , Nace Layadi , Edward Belden Harris , Sidhartha Sen
IPC分类号： H01L21362
CPC分类号： H01L28/40 , H01L21/31116 , H01L21/32136
摘要： A method for fabricating an MOM capacitor (10) includes forming a first conductive layer (18) on an insulating support (12, 14), depositing a dielectric film (20) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers (22, 24, 26). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material (38) around the capacitor feature. Sidewalls (40), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF6 plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

3. 发明授权

US07068139B2 Inductor formed in an integrated circuit 有权
公开(公告)号：US07068139B2
公开(公告)日：2006-06-27
申请号：US10953475
申请日：2004-09-29
申请人： Edward Belden Harris , Sailesh Mansinh Merchant , Kurt George Steiner , Susan Clay Vitkavage
发明人： Edward Belden Harris , Sailesh Mansinh Merchant , Kurt George Steiner , Susan Clay Vitkavage
IPC分类号： H01F5/00
CPC分类号： H01L24/10 , H01F41/041 , H01L23/5227 , H01L24/13 , H01L27/08 , H01L28/10 , H01L2224/05001 , H01L2224/05027 , H01L2224/0508 , H01L2224/05124 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2224/45124 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , Y10T29/4902 , H01L2924/00 , H01L2224/48
摘要： An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.

4. 发明申请

US20100032766A1 Bipolar Junction Transistor with a Reduced Collector-Substrate Capacitance 审中-公开
标题翻译：具有减少集电极 - 基板电容的双极结晶体管
公开(公告)号：US20100032766A1
公开(公告)日：2010-02-11
申请号：US12308158
申请日：2006-06-02
申请人： Alan Sangone Chen , Mark Victor Dyson , Edward Belden Harris , Daniel Charles Kerr , William John Nagy
发明人： Alan Sangone Chen , Mark Victor Dyson , Edward Belden Harris , Daniel Charles Kerr , William John Nagy
IPC分类号： H01L27/102 , H01L21/331 , H01L21/8249 , H01L29/73
CPC分类号： H01L29/0821 , H01L29/404
摘要： A process for forming a bipolar junction transistor (BJT) in a semiconductor substrate and a BJT formed according to the process. A buried isolation region is formed underlying BJT structures to isolate the BJT structures from the p-type semi-conductor substrate. To reduce capacitance between a BJT subcollector and the buried isolation region, prior to implanting the subcollector spaced-apart structures are formed on a surface of the substrate. The subcollector is formed by implanting ions through the spaced-apart structures and through a region intermediate the spaced-apart structures. The formed BJT subcollector therefore comprises a body portion and end portions extending therefrom, with the end portions disposed at a shallower depth than the body portion, since the ions implanting the end portions must pass through the spaced-apart structures. The shallower depth of the end portions reduces the capacitance.
摘要翻译：在半导体衬底中形成双极结型晶体管（BJT）的工艺和根据该工艺形成的BJT。在BJT结构之下形成掩埋隔离区，以将BJT结构与p型半导体衬底隔离。为了减小BJT子集电极和掩埋隔离区之间的电容，在植入之前，在基板的表面上形成间接分离结构的子集电极。子集电极通过将离子注入间隔开的结构并通过间隔开的结构之间的区域而形成。因此，形成的BJT子集电极包括主体部分和从其延伸的端部，其端部设置在比主体部分更浅的深度，因为注入端部的离子必须通过间隔开的结构。端部较浅的深度减小了电容。

5. 发明授权

US06323044B1 Method of forming capacitor having the lower metal electrode for preventing undesired defects at the surface of the metal plug 有权
标题翻译：形成具有下金属电极的电容器的方法，用于防止金属插头表面的不期望的缺陷
公开(公告)号：US06323044B1
公开(公告)日：2001-11-27
申请号：US09408299
申请日：1999-09-29
申请人： Edward Belden Harris , Sailesh Mansinh Merchant , Yifeng Winston Yan
发明人： Edward Belden Harris , Sailesh Mansinh Merchant , Yifeng Winston Yan
IPC分类号： H01L2100
CPC分类号： H01L28/60 , H01L21/28568
摘要： An integrated circuit capacitor includes a metal plug in a dielectric layer adjacent a substrate. The metal plug has at least one topographical defect in an uppermost surface portion thereof. A lower metal electrode overlies the dielectric layer and the metal plug. The lower metal electrode includes, in stacked relation, a metal layer, a lower metal nitride layer, an aluminum layer, and an upper metal nitride layer. A capacitor dielectric layer overlies the lower metal electrode, and an upper metal electrode overlies the capacitor dielectric layer. An advantage of this structure is that the stack of metal layers of the lower metal electrode, will prevent undesired defects at the surface of the metal plug from adversely effecting device reliability or manufacturing yield.
摘要翻译：集成电路电容器包括邻近衬底的电介质层中的金属插塞。金属插塞在其最上表面部分具有至少一个形貌缺陷。下部金属电极覆盖在电介质层和金属插头上。下部金属电极以堆叠关系包括金属层，下部金属氮化物层，铝层和上部金属氮化物层。电容器电介质层覆盖在下金属电极上，并且上金属电极覆盖在电容器介电层上。这种结构的优点是，下金属电极的金属层堆叠将防止在金属插塞表面的不期望的缺陷不利地影响器件的可靠性或制造成品率。

6. 发明授权

US07541238B2 Inductor formed in an integrated circuit 有权
标题翻译：集成电路中形成的电感器
公开(公告)号：US07541238B2
公开(公告)日：2009-06-02
申请号：US11414902
申请日：2006-05-01
申请人： Edward Belden Harris , Sailesh Mansinh Merchant , Kurt George Steiner , Susan Clay Vitkavage
发明人： Edward Belden Harris , Sailesh Mansinh Merchant , Kurt George Steiner , Susan Clay Vitkavage
IPC分类号： H01L21/8238
CPC分类号： H01L24/10 , H01F41/041 , H01L23/5227 , H01L24/13 , H01L27/08 , H01L28/10 , H01L2224/05001 , H01L2224/05027 , H01L2224/0508 , H01L2224/05124 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2224/45124 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , Y10T29/4902 , H01L2924/00 , H01L2224/48
摘要： An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.
摘要翻译：在集成电路内形成的电感器和形成电感器的方法。该电感器包括形成在第一金属化层中并被图案化并蚀刻成所需形状的铝的下层。在一个实施例中，铝线包括螺旋形状。根据镶嵌工艺，在覆盖铝线并且与其电接触的介电层中形成优选铜的导电流道。铝线和导电流道配合形成电感器。在另一个实施例中，铝线和导电流道以垂直间隔的方向形成，其中形成钨塞或导电通孔以提供电连接。形成电感器的方法包括形成铝导线并在导线上形成导电流道。

7. 发明申请

US20090100668A1 INDUCTOR FORMED IN AN INTEGRATED CIRCUIT 有权
标题翻译：在一体化电路中形成的电感器
公开(公告)号：US20090100668A1
公开(公告)日：2009-04-23
申请号：US12340813
申请日：2008-12-22
申请人： Edward Belden Harris , Sailesh Mansinh Merchant , Kurt George Steiner , Susan Clay Vitkavage
发明人： Edward Belden Harris , Sailesh Mansinh Merchant , Kurt George Steiner , Susan Clay Vitkavage
IPC分类号： H01F41/00
CPC分类号： H01L24/10 , H01F41/041 , H01L23/5227 , H01L24/13 , H01L27/08 , H01L28/10 , H01L2224/05001 , H01L2224/05027 , H01L2224/0508 , H01L2224/05124 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2224/45124 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , Y10T29/4902 , H01L2924/00 , H01L2224/48
摘要： An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.
摘要翻译：在集成电路内形成的电感器和形成电感器的方法。该电感器包括形成在第一金属化层中并被图案化并蚀刻成所需形状的铝的下层。在一个实施例中，铝线包括螺旋形状。根据镶嵌工艺，在覆盖铝线并且与其电接触的介电层中形成优选铜的导电流道。铝线和导电流道配合形成电感器。在另一个实施例中，铝线和导电流道以垂直间隔的方向形成，其中形成钨塞或导电通孔以提供电连接。形成电感器的方法包括形成铝导线并在导线上形成导电流道。

8. 发明授权

US06287952B1 Method of etching self-aligned vias to metal using a silicon nitride spacer 有权
标题翻译：使用氮化硅间隔物将自对准通孔蚀刻到金属的方法
公开(公告)号：US06287952B1
公开(公告)日：2001-09-11
申请号：US09473876
申请日：1999-12-28
申请人： Edward Belden Harris
发明人： Edward Belden Harris
IPC分类号： H01L214763
CPC分类号： H01L21/76802 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing integrated circuits uses a silicon nitride spacer for etching self-aligned vias. The method is accomplished by (1) providing a first inter-level dielectric layer having metal lines formed on it; (2) depositing a silicon nitride layer over the metal lines and the first inter-level dielectric layer; (3) depositing a second inter-level dielectric layer on the silicon nitride layer; (4) depositing a photoresist on that second inter-level dielectric layer; (5) patterning vias on that second inter-level dielectric layer; (6) non-selectively oxide etching the second inter-level dielectric layer and the silicon nitride layer to form the vias; and (7) selectively nitride-to-oxide etching the silicon nitride layer to remove the silicon nitride layer surrounding the metal lines, where the etching stops at the first inter-level dielectric layer. This forms an access window.
摘要翻译：集成电路的制造方法使用氮化硅间隔物来蚀刻自对准的通孔。该方法通过（1）提供其上形成有金属线的第一层间介电层来实现; （2）在金属线和第一层间电介质层上沉积氮化硅层; （3）在氮化硅层上沉积第二层间电介质层; （4）在该第二层间电介质层上沉积光致抗蚀剂; （5）在该第二层间电介质层上形成通孔; （6）非选择性氧化物蚀刻第二层间电介质层和氮化硅层以形成通孔; 和（7）选择性地氮化物 - 氧化物蚀刻氮化硅层以去除围绕金属线的氮化硅层，其中蚀刻在第一层间介电层处停止。这形成一个访问窗口。

9. 发明授权

US06847077B2 Capacitor for a semiconductor device and method for fabrication therefor 有权
标题翻译：一种用于半导体器件的电容器及其制造方法
公开(公告)号：US06847077B2
公开(公告)日：2005-01-25
申请号：US10180910
申请日：2002-06-25
申请人： Sylvia W. Thomas , Michael Jay Parrish , Tony G. Ivanov , Edward Belden Harris , Richard William Gregor , Michael Scott Carroll
发明人： Sylvia W. Thomas , Michael Jay Parrish , Tony G. Ivanov , Edward Belden Harris , Richard William Gregor , Michael Scott Carroll
IPC分类号： H01L21/3205 , H01L21/02 , H01L21/768 , H01L21/822 , H01L23/522 , H01L23/532 , H01L27/04 , H01L27/108
CPC分类号： H01L28/40 , H01L21/76838 , H01L23/5223 , H01L23/53228 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a capacitor integrated in a damascene structure. In one embodiment, the capacitor is formed entirely within a metallization layer of a damascene structure, having therein a semiconductor device component. Preferably, the capacitor is formed within a trench, having been etched in the dielectric material of the metal layer and the capacitor includes a first capacitor electrode formed within the recess in electrical contact with the device component of the metallization layer. An insulator may be formed over the first capacitor electrode, with a second capacitor electrode formed over the insulator. These elements are preferably conformally deposited within the trench, thereby forming a recess, a portion of which extends within the trench. A subsequently fabricated device component may then be placed in electrical contact with the second capacitor electrode.
摘要翻译：具有集成在镶嵌结构中的电容器的半导体器件。在一个实施例中，电容器完全形成在其中具有半导体器件部件的镶嵌结构的金属化层内。优选地，电容器形成在已经在金属层的介电材料中蚀刻的沟槽内，并且电容器包括形成在凹部内的与金属化层的器件部件电接触的第一电容器电极。可以在第一电容器电极上形成绝缘体，在绝缘体上形成第二电容器电极。这些元件优选地在沟槽内共形沉积，从而形成凹槽，其中一部分在沟槽内延伸。然后可以将随后制造的器件部件放置成与第二电容器电极电接触。

10. 发明授权

US06525358B2 Capacitor having the lower electrode for preventing undesired defects at the surface of the metal plug 有权
标题翻译：电容器具有用于防止在金属插头表面的不期望的缺陷的下电极
公开(公告)号：US06525358B2
公开(公告)日：2003-02-25
申请号：US09951178
申请日：2001-09-13
申请人： Edward Belden Harris , Sailesh Mansinh Merchant , Yifeng Winston Yan
发明人： Edward Belden Harris , Sailesh Mansinh Merchant , Yifeng Winston Yan
IPC分类号： H01L2976
CPC分类号： H01L28/60 , H01L21/28568
摘要： An integrated circuit capacitor includes a metal plug in a dielectric layer adjacent a substrate. The metal plug has at least one topographical defect in an uppermost surface portion thereof. A lower metal electrode overlies the dielectric layer and the metal plug. The lower metal electrode includes, in stacked relation, a metal layer, a lower metal nitride layer, an aluminum layer, and an upper metal nitride layer. A capacitor dielectric layer overlies the lower metal electrode, and an upper metal electrode: overlies the capacitor dielectric layer. An advantage of this structure is that the stack of metal layers of the lower metal electrode, will prevent undesired defects at the surface of the metal plug from adversely effecting device reliability or manufacturing yield.
摘要翻译：集成电路电容器包括邻近衬底的电介质层中的金属插塞。金属插塞在其最上表面部分具有至少一个形貌缺陷。下部金属电极覆盖在电介质层和金属插头上。下部金属电极以堆叠关系包括金属层，下部金属氮化物层，铝层和上部金属氮化物层。电容器电介质层覆盖在下金属电极上，上金属电极覆盖在电容器介电层上。这种结构的优点是，下金属电极的金属层堆叠将防止金属插塞表面的不期望的缺陷不利地影响器件的可靠性或制造成品率。

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