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1. 发明申请

US20110256700A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20110256700A1
公开(公告)日：2011-10-20
申请号：US13087522
申请日：2011-04-15
申请人： Chong-Kwang Chang , Sung-Hon Chi , Young-Mook Oh , Ju-Beom Yi
发明人： Chong-Kwang Chang , Sung-Hon Chi , Young-Mook Oh , Ju-Beom Yi
IPC分类号： H01L21/28
CPC分类号： H01L21/823842 , H01L21/82345 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： A method of fabricating a semiconductor device capable of simplifying a fabrication process is provided. The method includes providing a substrate on which first and second regions are defined, forming an interlayer insulating film including first and second trenches on the substrate, the first and second trenches being formed in the first and second regions, respectively, forming a work function adjusting metal film on an upper surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench, forming a mask film on the interlayer insulating film to fill in the first and second trenches, the mask film including a developable material, forming a mask pattern by developing the mask film, the mask pattern exposing the work function adjusting metal film formed in the first region, removing the work function adjusting metal film formed in the first region by using the mask pattern, removing the mask pattern, and forming a first metal gate in the first trench and a second metal gate in the second trench.
摘要翻译：提供了一种制造能够简化制造工艺的半导体器件的方法。该方法包括提供在其上限定了第一和第二区域的基板，在基板上形成包括第一和第二沟槽的层间绝缘膜，第一和第二沟槽分别形成在第一和第二区域中，形成功函数调整层间绝缘膜的上表面的金属膜，第一沟槽的侧表面和底表面以及第二沟槽的侧表面和底表面，在层间绝缘膜上形成掩模膜以填充第一和第二沟槽，包含可显影材料的掩模膜，通过显影掩模膜形成掩模图案，掩模图案暴露在第一区域中形成的功函数调整金属膜，通过使用掩模图案去除形成在第一区域中的功函数调节金属膜去除掩模图案，以及在第一沟槽中形成第一金属栅极和在第二沟槽中形成第二金属栅极。

2. 发明申请

US20110201202A1 METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：形成半导体器件精细图案的方法
公开(公告)号：US20110201202A1
公开(公告)日：2011-08-18
申请号：US13007071
申请日：2011-01-14
申请人： Chong-Kwang CHANG , Young-Mook OH , Seo-Woo NAM , Woo-Cheol JEON , Ju-Beom YI , Myung-Joo LEE
发明人： Chong-Kwang CHANG , Young-Mook OH , Seo-Woo NAM , Woo-Cheol JEON , Ju-Beom YI , Myung-Joo LEE
IPC分类号： H01L21/3105
CPC分类号： H01L21/0337 , H01L21/0338
摘要： A method of forming fine patterns of a semiconductor device, the method including providing a patternable layer; forming a plurality of first photoresist layer patterns on the patternable layer; forming an interfacial layer on the patternable layer and the plurality of first photoresist layer patterns; forming a planarization layer on the interfacial layer; forming a plurality of second photoresist layer patterns on the planarization layer; forming a plurality of planarization layer patterns using the plurality of second photoresist layer patterns; and forming a plurality of layer patterns using the plurality of planarization layer patterns and the plurality of first photoresist layer patterns.
摘要翻译：一种形成半导体器件的精细图案的方法，所述方法包括提供可图案化层; 在所述可图案层上形成多个第一光致抗蚀剂层图案; 在所述可图案层和所述多个第一光致抗蚀剂层图案上形成界面层; 在界面层上形成平坦化层; 在平坦化层上形成多个第二光致抗蚀剂层图案; 使用所述多个第二光致抗蚀剂层图案形成多个平坦化图案; 以及使用所述多个平坦化层图案和所述多个第一光致抗蚀剂层图案形成多个层图案。

3. 发明申请

US20100230758A1 SEMICONDUCTOR DEVICE WITH IMPROVED STRESSOR SHAPE 审中-公开
标题翻译：具有改进的压力形状的半导体器件
公开(公告)号：US20100230758A1
公开(公告)日：2010-09-16
申请号：US12697572
申请日：2010-02-01
申请人： Chong Kwang CHANG , HwaSung Rhee , MyungSun Kim , NaeIn Lee , HongJae Shin
发明人： Chong Kwang CHANG , HwaSung Rhee , MyungSun Kim , NaeIn Lee , HongJae Shin
IPC分类号： H01L27/088 , H01L21/71
CPC分类号： H01L29/0847 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A formation method and resulting strained semiconductor device are provided, the formation method including forming transistors on a substrate, each transistor having a gate disposed over a channel region, etching or annealing an elongated trench between adjacent channel regions, where the trench has a lower boundary that is deeper towards its ends than towards its center, and conformably embedding an elongated stress region in the trench between adjacent channel regions; and the resulting strained semiconductor device including transistors, each having a gate disposed over a channel region, and elongated stress regions disposed between adjacent channel regions, wherein each of the elongated stress regions has a lower boundary that is deeper towards its ends than towards its center.
摘要翻译：提供一种形成方法和产生的应变半导体器件，所述形成方法包括在衬底上形成晶体管，每个晶体管具有设置在沟道区上方的栅极，蚀刻或退火相邻沟道区之间的细长沟槽，其中沟槽具有下边界其端部比朝向其中心更深，并且在相邻通道区域之间的沟槽中顺应地嵌入细长的应力区域; 并且所得到的应变半导体器件包括晶体管，每个晶体管均具有设置在沟道区域上的栅极，以及设置在相邻沟道区域之间的细长应力区域，其中每个细长应力区域具有朝向其端部比其中心更深的下边界。

4. 发明申请

US20090017630A1 Methods For Forming Contacts For Dual Stress Liner CMOS Semiconductor Devices 有权
标题翻译：双应力衬片CMOS半导体器件形成触点的方法
公开(公告)号：US20090017630A1
公开(公告)日：2009-01-15
申请号：US11778039
申请日：2007-07-14
申请人： Kyoung Woo Lee , Ja Hum Ku , WanJae Park , Chong Kwang Chang , Theodorus E. Standaert
发明人： Kyoung Woo Lee , Ja Hum Ku , WanJae Park , Chong Kwang Chang , Theodorus E. Standaert
IPC分类号： H01L21/311
CPC分类号： H01L21/76816 , H01L21/76829 , H01L21/823807 , H01L21/823871
摘要： Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL.
摘要翻译：提供了在DSL（双重应力衬垫）半导体器件中形成通孔接触的半导体制造方法，其中实现改进的蚀刻工艺流程，以便能够通过双重应力衬垫结构的重叠和非重叠区域蚀刻通孔接触开口以暴露底层的水银触点和其他设备触点，同时减轻或消除缺陷机制，例如对DSL的非重叠区域下的接触区域进行过蚀刻。

5. 发明申请

US20080220609A1 Methods of Forming Mask Patterns on Semiconductor Wafers that Compensate for Nonuniform Center-to-Edge Etch Rates During Photolithographic Processing 有权
标题翻译：在光刻处理中补偿不均匀的中心到边缘蚀刻速率的半导体晶片上形成掩模图案的方法
公开(公告)号：US20080220609A1
公开(公告)日：2008-09-11
申请号：US11683648
申请日：2007-03-08
申请人： Chong Kwang Chang , Wan Jae Park , Len Yuan Tsou , Haoren Zhuang , Matthias Lipinski , Shailendra Mishra
发明人： Chong Kwang Chang , Wan Jae Park , Len Yuan Tsou , Haoren Zhuang , Matthias Lipinski , Shailendra Mishra
IPC分类号： H01L21/302
CPC分类号： H01L21/31144
摘要： Methods of forming integrated circuit devices include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are performed so that more uniform center-to-edge critical dimensions (CD) can be achieved when the mask pattern is used to support photolithographically patterning of underlying layers (e.g., insulating layers, antireflective coatings, etc.).
摘要翻译：形成集成电路器件的方法包括选择性地加宽邻近半导体晶片的外边缘延伸的掩模图案的部分的步骤。执行选择性拓宽掩模图案部分的这些步骤，使得当掩模图案用于支持下层（例如，绝缘层，抗反射涂层）的光刻图案化时，可以实现更均匀的中心至边缘临界尺寸（CD）等）。

6. 发明授权

US6028141A Polyfunctional crosslinking agents and curable compositions containing the same 失效
标题翻译：多官能交联剂和含有它们的可固化组合物
公开(公告)号：US6028141A
公开(公告)日：2000-02-22
申请号：US881780
申请日：1997-06-24
申请人： Balwant Singh , Laurence Wu-Kwang Chang
发明人： Balwant Singh , Laurence Wu-Kwang Chang
IPC分类号： C07D233/40 , C08F8/30 , C08G71/02 , C08G73/02 , C08G73/06 , C08K5/3445 , C07D233/38 , C08F226/06 , C08G63/91
CPC分类号： C08G71/02 , C07D233/40 , C08F8/30 , C08G73/0273 , C08G73/0677 , C08K5/3445
摘要： Novel polyfunctonal glyoxylated compounds and compositions containing the same are disclosed which are particularly suitable for use as crosslinking components in curable compositions and also find use in imparting wet adhesion properties to water-based paints and coatings. A process for preparing novel polyfunctional glyoxylated compounds is also disclosed.
摘要翻译：公开了新颖的多聚乙醛醛化合物和含有它们的组合物，其特别适合用作可固化组合物中的交联组分，并且还可用于赋予水性涂料和涂料湿粘合性能。还公开了制备新型多官能乙醛化化合物的方法。

7. 发明申请

US20160293600A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20160293600A1
公开(公告)日：2016-10-06
申请号：US14995511
申请日：2016-01-14
申请人： Jung-Gun YOU , Hyung-Jong LEE , Chong-Kwang CHANG , Sung-Min KIM
发明人： Jung-Gun YOU , Hyung-Jong LEE , Chong-Kwang CHANG , Sung-Min KIM
IPC分类号： H01L27/088 , H01L27/02 , H01L23/535 , H01L29/06
CPC分类号： H01L27/0886 , H01L21/823431 , H01L21/823475 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L27/0924 , H01L29/0649 , H01L29/41791 , H01L29/7854
摘要： A semiconductor device, including a first fin type pattern and a second fin type pattern defined by a trench, the first fin type pattern and the second fin type pattern extending in a first direction, the first fin type pattern and the second fin type pattern being closest to each other; a field insulation layer filling a portion of the trench; and a contact contacting the field insulation layer, the first fin type pattern, and the second fin type pattern, the contact having a bottom surface in a shape of a wave.
摘要翻译：一种半导体器件，包括由沟槽限定的第一鳍式图案和第二鳍型图案，所述第一鳍型图案和所述第二鳍片图案沿第一方向延伸，所述第一鳍片型图案和所述第二鳍片图案为最接近; 填充所述沟槽的一部分的场绝缘层; 以及与场绝缘层，第一鳍式图案和第二鳍型图案接触的接触件，该接触件具有波形形状的底面。

8. 发明授权

US08697339B2 Semiconductor device manufacturing methods 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08697339B2
公开(公告)日：2014-04-15
申请号：US13081377
申请日：2011-04-06
申请人： Haoren Zhuang , Chong Kwang Chang , Alois Gutmann , Jingyu Lian , Matthias Lipinski , Len Yuan Tsou , Helen Wang
发明人： Haoren Zhuang , Chong Kwang Chang , Alois Gutmann , Jingyu Lian , Matthias Lipinski , Len Yuan Tsou , Helen Wang
IPC分类号： G03F7/20
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/84
摘要： Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. A polymer material is disposed over the masking material. The masking material and the polymer layer are used to pattern the material layer of the workpiece.
摘要翻译：公开了制造半导体器件的方法。一个优选实施例是一种处理半导体器件的方法。该方法包括提供具有设置在其上的待图案化材料层的工件。在工件的材料层上形成掩模材料。掩模材料包括下部和设置在下部上的上部。用第一图案对掩模材料的上部进行图案化。聚合物材料设置在掩蔽材料上方。掩模材料和聚合物层用于对工件的材料层进行图案化。

9. 发明申请

US20100173497A1 Method of fabricating semiconductor integrated circuit device 审中-公开
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20100173497A1
公开(公告)日：2010-07-08
申请号：US12655837
申请日：2010-01-06
申请人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Seo-Woo Nam , In-Keun Lee , Jung-Hoon Lee
发明人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Seo-Woo Nam , In-Keun Lee , Jung-Hoon Lee
IPC分类号： H01L21/306
CPC分类号： H01L21/32139
摘要： A method manufacturing a semiconductor integrated circuit device includes providing a substrate; sequentially forming a layer to be etched, a first layer, and a second layer on the substrate; forming on the first and second layers a first etch mask having a plurality of first line patterns separated from each other by a first pitch and extending in a first direction; sequentially performing first etching on the second layer and the first layer using the first etch mask to form an intermediate mask pattern with second and first patterns; forming on the intermediate mask pattern a second etch mask including a plurality of second line patterns separated from each other by a second pitch and extending in a second direction other than the first direction; performing second etching using the second etch mask on a portion of the second pattern so that the remaining portion of the second pattern is left on the first pattern; performing third etching using the second etch mask under different conditions than the second etching on the first pattern and the remaining portion of second pattern of the intermediate mask pattern and forming a final mask pattern; and patterning the layer to be etched using the final mask pattern.
摘要翻译：制造半导体集成电路器件的方法包括：提供衬底; 在基板上依次形成被蚀刻层，第一层和第二层; 在所述第一层和第二层上形成第一蚀刻掩模，所述第一蚀刻掩模具有以第一间距彼此分开并沿第一方向延伸的多个第一线图案; 使用第一蚀刻掩模在第二层和第一层上顺序地执行第一蚀刻以形成具有第二和第一图案的中间掩模图案; 在所述中间掩模图案上形成第二蚀刻掩模，所述第二蚀刻掩模包括以第二间距彼此分开并沿除了所述第一方向之外的第二方向延伸的多个第二线图案; 在第二图案的一部分上使用第二蚀刻掩模进行第二蚀刻，使得第二图案的剩余部分留在第一图案上; 在与第一图案上的第二蚀刻和中间掩模图案的第二图案的剩余部分不同的条件下，使用第二蚀刻掩模进行第三蚀刻，并形成最终的掩模图案; 并使用最终的掩模图案来图案化待蚀刻的层。

10. 发明申请

US20060173790A1 Optical payment transceiver and system using the same 审中-公开
公开(公告)号：US20060173790A1
公开(公告)日：2006-08-03
申请号：US11291291
申请日：2005-12-01
申请人： Kyung Park , Chul Kim , Que Hwang , Bong Jung , Kwang Sung , Do Kim , Hoon Jung , Bog Kang , Eun Cho , Won Kim , Dae Kim , Kwang Chang , Hee Woo
发明人： Kyung Park , Chul Kim , Que Hwang , Bong Jung , Kwang Sung , Do Kim , Hoon Jung , Bog Kang , Eun Cho , Won Kim , Dae Kim , Kwang Chang , Hee Woo
IPC分类号： G06Q99/00
CPC分类号： G07B15/063
摘要： An optical payment transceiver and an optical settlement system using the same uses a personal portable terminal incorporated with an optical transceiver as a card substitute payment unit for settlement. Here, card information is incorporated in a personal portable terminal incorporated with an optical transceiver such as a portable phone or a PDA and the optical transceiver is connected to a card inquiry machine to thereby optically transmit and receive card information. The card inquiry machine recognizes the received card information in the same manner as that of the card reader reading a magnetic card, and transmits the card information to a VAN company server or a card company server, to then request for an approval and settle transactions. The present invention is applied to most fields where financial transactions are performed as in a general commerce, a toll gate fee or tunnel passage fee collection system, a subway or bus fare levying system, a gas station, a department store, a drive-thru ordering system, a vending machine, and a fee payment system of kiosks. Also, the present invention can be applied to an entrance/exit security system requiring personal identification. Thus, the present invention can use a portable terminal as a payment unit without carrying a cash or cards, to thereby provide an effect of performing a safer and more reliable credit transaction.

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