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1. 发明授权

US08021954B2 Integrated circuit system with hierarchical capacitor and method of manufacture thereof 有权
标题翻译：具有层状电容器的集成电路系统及其制造方法
公开(公告)号：US08021954B2
公开(公告)日：2011-09-20
申请号：US12471007
申请日：2009-05-22
申请人： Shao-fu Sanford Chu , Shaoqing Zhang , Johnny Kok Wai Chew , Chit Hwei Ng
发明人： Shao-fu Sanford Chu , Shaoqing Zhang , Johnny Kok Wai Chew , Chit Hwei Ng
IPC分类号： H01L21/20 , H01L21/02
CPC分类号： H01L23/5223 , H01L27/0207 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers with the second group of metal layers to form a capacitor.
摘要翻译：一种制造集成电路系统的方法包括：提供包括前端电路的基板; 利用第一设计规则在所述衬底上形成包括第一手指和第二手指的第一组金属层，所述第一组金属层形成为没有手指通孔; 利用大于第一设计规则的第二设计规则，在第一组金属层上形成包括第一手指，第二手指和手指通孔的第二组金属层; 并且将所述第一组金属层与所述第二组金属层互连以形成电容器。

2. 发明授权

US07721414B2 Method of manufacturing 3-D spiral stacked inductor on semiconductor material 有权
标题翻译：在半导体材料上制造三维螺旋堆叠电感器的方法
公开(公告)号：US07721414B2
公开(公告)日：2010-05-25
申请号：US10962007
申请日：2004-10-08
申请人： Choon-Beng Sia , Kiat Seng Yeo , Shao-fu Sanford Chu , Cheng Yeow Ng , Kok Wai Chew , Wang Ling Goh
发明人： Choon-Beng Sia , Kiat Seng Yeo , Shao-fu Sanford Chu , Cheng Yeow Ng , Kok Wai Chew , Wang Ling Goh
IPC分类号： H01F7/06 , H01F3/00
CPC分类号： H01L28/10 , H01L27/08 , Y10T29/4902 , Y10T29/4906 , Y10T29/49073 , Y10T29/49165
摘要： A method of manufacturing a 3-D spiral stacked inductor is provided having a substrate with a plurality of turns in a plurality of levels wherein the number of levels increases from an inner turn to the outer turn of the inductor. First and second connecting portions are respectively connected to an inner turn and an outermost turn, and a dielectric material contains the first and second connecting portions and the plurality of turns over the substrate.
摘要翻译：提供了一种制造3-D螺旋堆叠电感器的方法，其具有多个电平的多个匝数的基板，其中电平的数量从电感器的内部匝数增加到外部匝数。第一连接部分和第二连接部分分别连接到内匝和最外匝，电介质材料包含基片上的第一和第二连接部分和多个匝。

3. 发明申请

US20100109097A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING AN ELEVATED DRAIN 有权
标题翻译：集成电路系统采用高压排水
公开(公告)号：US20100109097A1
公开(公告)日：2010-05-06
申请号：US12262120
申请日：2008-10-30
申请人： Guowei Zhang , Yisuo Li , Ming Li , Purakh Raj Verma , Shao-fu Sanford Chu
发明人： Guowei Zhang , Yisuo Li , Ming Li , Purakh Raj Verma , Shao-fu Sanford Chu
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/66659 , H01L29/7834
摘要： A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above the drift region.
摘要翻译：一种用于制造集成电路系统的方法，包括：提供包括有源器件的衬底; 在所述衬底中形成漂移区域，所述漂移区域部分地由所述衬底的顶表面限定并与源极隔开; 并在漂移区上方形成漏极。

4. 发明授权

US07078998B2 Via/line inductor on semiconductor material 有权
标题翻译：半导体材料上的通/线电感
公开(公告)号：US07078998B2
公开(公告)日：2006-07-18
申请号：US10754973
申请日：2004-01-09
申请人： Jiong Zhang , Yi Min Wang , Shao-fu Sanford Chu
发明人： Jiong Zhang , Yi Min Wang , Shao-fu Sanford Chu
IPC分类号： H01F5/00
CPC分类号： H01L28/10 , H01L27/08 , Y10T29/4902
摘要： A spiral inductor is provided including a substrate and an inductor dielectric layer over the substrate having a spiral opening provided therein. The spiral inductor is in the spiral opening with the spiral inductor including a plurality of parallel spiral vias connected together at center proximate and center distal ends of the spiral inductor.
摘要翻译：提供螺旋电感器，其包括衬底和在其上设置有螺旋开口的衬底上的电感器电介质层。螺旋电感器处于螺旋形开口中，螺旋电感器包括在螺旋电感器的中心近端和中心远端处连接在一起的多个平行螺旋通孔。

5. 发明授权

US07049201B2 Method and apparatus for a heterojunction bipolar transistor using self-aligned epitaxy 有权
标题翻译：使用自对准外延的异质结双极晶体管的方法和装置
公开(公告)号：US07049201B2
公开(公告)日：2006-05-23
申请号：US10703297
申请日：2003-11-06
申请人： Purakh Raj Verma , Shao-Fu Sanford Chu , Lap Chan , Jian Xun Li , Jia Zhen Zheng
发明人： Purakh Raj Verma , Shao-Fu Sanford Chu , Lap Chan , Jian Xun Li , Jia Zhen Zheng
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, a number of insulating layers over the semiconductor substrate, at least one of the number of insulating layers having a base cavity over the collector region, a base structure of a compound semiconductive material in the base cavity, a window in the insulating layer over the base cavity, an emitter structure in the window, an interlevel dielectric layer, and connections through the interlevel dielectric layer to the base structure, the emitter structure, and the collector region. The base structure and the emitter structure preferably are formed in the same processing chamber.
摘要翻译：一种异质结双极晶体管（HBT）及其制造方法，包括具有集电极区域，半导体衬底上的多个绝缘层的半导体衬底，在集电极区域上具有基腔的多个绝缘层中的至少一个，基腔中的复合半导体材料的基底结构，在基底腔上的绝缘层中的窗口，窗口中的发射极结构，层间介电层以及通过层间介电层到基底结构的连接，发射极结构和收集器区域。基底结构和发射极结构优选地形成在相同的处理室中。

6. 发明授权

US06924202B2 Heterojunction bipolar transistor with self-aligned emitter and sidewall base contact 有权
标题翻译：具有自对准发射极和侧壁基极接触的异质结双极晶体管
公开(公告)号：US06924202B2
公开(公告)日：2005-08-02
申请号：US10683142
申请日：2003-10-09
申请人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
发明人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
IPC分类号： H01L21/331 , H01L29/08 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/0817 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT), and manufacturing method therfor, comprising a semiconductor substrate having a collector region is provided. A base contact layer is formed over the collector region, and a base trench is formed in the base contact layer and the collector region. An intrinsic base structure having a sidewall portion and a bottom portion is formed in the base trench. An insulating spacer is formed over the sidewall portion of the intrinsic base structure, and an emitter structure is formed over the insulating spacer and the bottom portion of the intrinsic base structure. An interlevel dielectric layer is formed over the base contact layer and the emitter structure. Connections are formed through the interlevel dielectric layer to the collector region, the base contact layer, and the emitter structure. The intrinsic base structure is silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：提供了具有集电极区域的半导体衬底的异质结双极晶体管（HBT）及其制造方法。基极接触层形成在集电极区域上，基底沟槽形成在基极接触层和集电极区域中。在基底沟槽中形成具有侧壁部分和底部的本征基底结构。在本征基底结构的侧壁部分上形成绝缘间隔物，并且在绝缘间隔物和本征基底结构的底部上形成发射极结构。在基极接触层和发射极结构之上形成层间电介质层。通过层间绝缘层到集电极区，基极接触层和发射极结构形成连接。本征基础结构是硅和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

7. 发明授权

US06908824B2 Self-aligned lateral heterojunction bipolar transistor 有权
标题翻译：自对准横向异质结双极晶体管
公开(公告)号：US06908824B2
公开(公告)日：2005-06-21
申请号：US10703284
申请日：2003-11-06
申请人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
发明人： Jian Xun Li , Lap Chan , Purakh Raj Verma , Jia Zhen Zheng , Shao-fu Sanford Chu
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/737
摘要： A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.
摘要翻译：提供一种用于制造横向异质结双极晶体管（HBT）的方法，包括半导体衬底上的第一绝缘层的半导体衬底。基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。基底结构形成在基底沟槽中。通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

8. 发明授权

US06881976B1 Heterojunction BiCMOS semiconductor 失效
标题翻译：异质结BiCMOS半导体
公开(公告)号：US06881976B1
公开(公告)日：2005-04-19
申请号：US10705163
申请日：2003-11-06
申请人： Jia Zhen Zheng , Lap Chan , Shao-fu Sanford Chu
发明人： Jia Zhen Zheng , Lap Chan , Shao-fu Sanford Chu
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/108 , H01L29/04 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L29/66242 , H01L21/8249 , H01L27/0623
摘要： A BiCMOS semiconductor, and manufacturing method therefore, is provided. A semiconductor substrate having a collector region is provided. A pseudo-gate is formed over the collector region. An emitter window is formed in the pseudo-gate to form an extrinsic base structure. An undercut region beneath a portion of the pseudo-gate is formed to provide an intrinsic base structure in the undercut region. An emitter structure is formed in the emitter window over the intrinsic base structure. An interlevel dielectric layer is formed over the semiconductor substrate, and connections are formed through the interlevel dielectric layer to the collector region, the extrinsic base structure, and the emitter structure. The intrinsic base structure comprises a compound semiconductive material such as silicon and silicon-germanium, or silicon-germanium-carbon, or combinations thereof.
摘要翻译：因此，提供BiCMOS半导体及其制造方法。提供具有集电极区域的半导体衬底。在集电极区域上形成伪栅极。在伪栅极中形成发射器窗口以形成外部基极结构。在伪栅极的一部分下面的底切区域形成为在底切区域中提供内部基极结构。发射极结构在内部基极结构的发射极窗口中形成。在半导体衬底上形成层间电介质层，并且通过层间电介质层到集电极区域，非本征基极结构和发射极结构形成连接。本征基础结构包括诸如硅和硅 - 锗的复合半导体材料或硅 - 锗 - 碳或其组合。

9. 发明授权

US06410394B1 Method for forming self-aligned channel implants using a gate poly reverse mask 失效
标题翻译：使用栅极多反向掩模形成自对准沟道植入物的方法
公开(公告)号：US06410394B1
公开(公告)日：2002-06-25
申请号：US09465305
申请日：1999-12-17
申请人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
发明人： Kai Shao , Yimin Wang , Jian Xun Li , Shao-Fu Sanford Chu
IPC分类号： H01L21336
CPC分类号： H01L21/823807 , Y10S977/712
摘要： A method for forming a CMOS transistor gate with a self-aligned channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a first threshold adjust region and a first anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the first gate layer is planarized to form a gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.
摘要翻译：一种用于形成具有自对准沟道植入物的CMOS晶体管栅极的方法。提供具有第一有源区的半导体结构。在半导体结构上形成第一绝缘层，在第一绝缘层上形成第二绝缘层。使用多反向掩模和对第一绝缘层选择性地蚀刻第二绝缘层以形成第一沟道注入开口，并且去除多反向掩模。形成暴露第一通道植入物开口的第一通道植入物掩模。杂质离子通过第一通道注入开口注入，以形成第一阈值调整区域和第一抗穿通区域。在半导体结构上形成栅极层，并且第一栅极层被平坦化以形成栅电极。去除第二绝缘层，并且可以在栅电极附近形成轻掺杂的源极和漏极区域，侧壁间隔物和源极和漏极区域。

10. 发明授权

US6124194A Method of fabrication of anti-fuse integrated with dual damascene process 有权
标题翻译：与双镶嵌工艺集成的抗熔丝的制造方法
公开(公告)号：US6124194A
公开(公告)日：2000-09-26
申请号：US439365
申请日：1999-11-15
申请人： Kai Shao , Yi Xu , Cerdin Lee , Shao-Fu Sanford Chu
发明人： Kai Shao , Yi Xu , Cerdin Lee , Shao-Fu Sanford Chu
IPC分类号： H01L21/768 , H01L23/525 , H07L29/00
CPC分类号： H01L21/7681 , H01L23/5252 , H01L2924/0002
摘要： A method of fabricating an anti-fuse module and dual damascene interconnect structure comprises the following steps. A semiconductor structure having at least two exposed metal lines covered by a first dielectric layer is provided. A first metal line is within an anti-fuse area and a second metal line is within an interconnect area. A first metal via is formed within the first dielectric layer within the anti-fuse area with the first metal via contacting the first metal line. A SiN layer is deposited over the first dielectric layer and the first metal via. The SiN layer is patterned to form at least two openings. A first opening exposes the first metal via, and a second opening exposes a portion of the first dielectric layer above the second metal line. A fusing element layer is deposited and patterned over the patterned SiN layered structure to form a fusing element over the first metal via. Simultaneously, an anti-fuse metal line is formed over the fusing element to form an anti-fuse module within the anti-fuse area, and a dual damascene interconnect is formed over, and contacting with, the second metal line and within the interconnect area.
摘要翻译：一种制造抗熔丝模块和双镶嵌互连结构的方法包括以下步骤。提供具有被第一介电层覆盖的至少两个暴露的金属线的半导体结构。第一金属线在反熔丝区内，第二金属线在互连区内。第一金属通孔形成在反熔丝区域内的第一电介质层内，第一金属通孔接触第一金属线。在第一介电层和第一金属通孔上沉积SiN层。图案化SiN层以形成至少两个开口。第一开口暴露第一金属通孔，第二开口暴露第二电介质层的第二金属线上方的一部分。在图案化的SiN层状结构上沉积并图案化定影元件层，以在第一金属通孔之上形成定影元件。同时，在熔断元件上方形成抗熔丝金属线，以在反熔丝区域内形成反熔丝模块，并且在第二金属线之间和互连区内形成双面镶嵌互连。

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